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-rw-r--r--board/freescale/mpc8315erdb/config.mk8
-rw-r--r--board/freescale/mpc8315erdb/mpc8315erdb.c42
-rw-r--r--board/freescale/mpc8315erdb/sdram.c9
3 files changed, 58 insertions, 1 deletions
diff --git a/board/freescale/mpc8315erdb/config.mk b/board/freescale/mpc8315erdb/config.mk
index f768264..bf972fb 100644
--- a/board/freescale/mpc8315erdb/config.mk
+++ b/board/freescale/mpc8315erdb/config.mk
@@ -1 +1,9 @@
+ifndef NAND_SPL
+ifeq ($(CONFIG_MK_NAND), y)
+TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+endif
+endif
+
+ifndef TEXT_BASE
TEXT_BASE = 0xFE000000
+endif
diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c
index dea4d6f..d5e71dc 100644
--- a/board/freescale/mpc8315erdb/mpc8315erdb.c
+++ b/board/freescale/mpc8315erdb/mpc8315erdb.c
@@ -32,6 +32,8 @@
#include <mpc83xx.h>
#include <netdev.h>
#include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -45,6 +47,8 @@ int board_early_init_f(void)
return 0;
}
+#ifndef CONFIG_NAND_SPL
+
static u8 read_board_info(void)
{
u8 val8;
@@ -220,3 +224,41 @@ int board_eth_init(bd_t *bis)
cpu_eth_init(bis); /* Initialize TSECs first */
return pci_eth_init(bis);
}
+
+#else /* CONFIG_NAND_SPL */
+
+int checkboard(void)
+{
+ puts("Board: Freescale MPC8315ERDB\n");
+ return 0;
+}
+
+void board_init_f(ulong bootflag)
+{
+ board_early_init_f();
+ NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
+ CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+ puts("NAND boot... ");
+ init_timebase();
+ initdram(0);
+ relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
+ CONFIG_SYS_NAND_U_BOOT_RELOC);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (gd->flags & GD_FLG_SILENT)
+ return;
+
+ if (c == '\n')
+ NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
+
+ NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
+}
+
+#endif /* CONFIG_NAND_SPL */
diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c
index ead7b1e..fe8ec1e 100644
--- a/board/freescale/mpc8315erdb/sdram.c
+++ b/board/freescale/mpc8315erdb/sdram.c
@@ -54,6 +54,7 @@ static void resume_from_sleep(void)
* This is useful for faster booting in configs where the RAM is unlikely
* to be changed, or for things like NAND booting where space is tight.
*/
+#ifndef CONFIG_SYS_RAMBOOT
static long fixed_sdram(void)
{
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
@@ -68,7 +69,7 @@ static long fixed_sdram(void)
* Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
* or the DDR2 controller may fail to initialize correctly.
*/
- udelay(50000);
+ __udelay(50000);
im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
@@ -100,6 +101,12 @@ static long fixed_sdram(void)
return msize;
}
+#else
+static long fixed_sdram(void)
+{
+ return CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+}
+#endif /* CONFIG_SYS_RAMBOOT */
phys_size_t initdram(int board_type)
{