summaryrefslogtreecommitdiff
path: root/board/freescale
diff options
context:
space:
mode:
Diffstat (limited to 'board/freescale')
-rw-r--r--board/freescale/mpc8569mds/mpc8569mds.c26
-rw-r--r--board/freescale/mpc8569mds/tlb.c15
2 files changed, 36 insertions, 5 deletions
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
index 01b7dcb..795e565 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -27,6 +27,7 @@
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
+#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
@@ -211,6 +212,31 @@ int board_early_init_f (void)
return 0;
}
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
+ const u8 flash_esel = 0;
+
+ /*
+ * Remap Boot flash to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
+ 0, flash_esel, /* ts, esel */
+ BOOKE_PAGESZ_64M, 1); /* tsize, iprot */
+
+ return 0;
+}
+
int checkboard (void)
{
printf ("Board: 8569 MDS\n");
diff --git a/board/freescale/mpc8569mds/tlb.c b/board/freescale/mpc8569mds/tlb.c
index 73dcc3e..f852fc3 100644
--- a/board/freescale/mpc8569mds/tlb.c
+++ b/board/freescale/mpc8569mds/tlb.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -46,15 +46,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 1 Initializations */
/*
- * TLBe 0: 64M Non-cacheable, guarded
+ * TLBe 0: 64M write-through, guarded
* Out of reset this entry is only 4K.
- * 0xfc000000 256K NAND FLASH (CS3)
- * 0xfe000000 32M NOR FLASH (CS0)
+ * 0xfc000000 32MB NAND FLASH (CS3)
+ * 0xfe000000 32MB NOR FLASH (CS0)
*/
+#ifdef CONFIG_NAND_SPL
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 0, BOOKE_PAGESZ_64M, 1),
-
+#endif
/*
* TLBe 1: 256KB Non-cacheable, guarded
* 0xf8000000 32K BCSR