diff options
Diffstat (limited to 'board/freescale')
-rw-r--r-- | board/freescale/mx28evk/iomux.c | 21 | ||||
-rw-r--r-- | board/freescale/mx53loco/mx53loco.c | 146 | ||||
-rw-r--r-- | board/freescale/mx6qsabrelite/mx6qsabrelite.c | 155 |
3 files changed, 316 insertions, 6 deletions
diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c index 396761b..6587c45 100644 --- a/board/freescale/mx28evk/iomux.c +++ b/board/freescale/mx28evk/iomux.c @@ -26,6 +26,7 @@ #include <asm/arch/sys_proto.h> #define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) #define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) #define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) #define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) @@ -55,6 +56,26 @@ const iomux_cfg_t iomux_setup[] = { MX28_PAD_PWM3__GPIO_3_28 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), +#ifdef CONFIG_NAND_MXS + /* GPMI NAND */ + MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RDN__GPMI_RDN | + (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), + MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, +#endif + /* FEC0 */ MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index d736141..dec966d 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -27,6 +27,7 @@ #include <asm/arch/mx5x_pins.h> #include <asm/arch/sys_proto.h> #include <asm/arch/crm_regs.h> +#include <asm/arch/clock.h> #include <asm/arch/iomux.h> #include <asm/arch/clock.h> #include <asm/errno.h> @@ -35,6 +36,9 @@ #include <mmc.h> #include <fsl_esdhc.h> #include <asm/gpio.h> +#include <pmic.h> +#include <dialog_pmic.h> +#include <fsl_pmic.h> DECLARE_GLOBAL_DATA_PTR; @@ -58,6 +62,18 @@ void dram_init_banksize(void) gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; } +u32 get_board_rev(void) +{ + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; + struct fuse_bank *bank = &iim->bank[0]; + struct fuse_bank0_regs *fuse = + (struct fuse_bank0_regs *)bank->fuse_regs; + + int rev = readl(&fuse->gp[6]); + + return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; +} + static void setup_iomux_uart(void) { /* UART1 RXD */ @@ -81,10 +97,9 @@ static void setup_iomux_uart(void) #ifdef CONFIG_USB_EHCI_MX5 int board_ehci_hcd_init(int port) { - /* request VBUS power enable pin, GPIO[8}, gpio7 */ + /* request VBUS power enable pin, GPIO7_8 */ mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1); - gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 0); - gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1); + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1); return 0; } #endif @@ -290,6 +305,103 @@ int board_mmc_init(bd_t *bis) } #endif +static void setup_iomux_i2c(void) +{ + /* I2C1 SDA */ + mxc_request_iomux(MX53_PIN_CSI0_D8, + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_CSI0_D8, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | + PAD_CTL_ODE_OPENDRAIN_ENABLE); + /* I2C1 SCL */ + mxc_request_iomux(MX53_PIN_CSI0_D9, + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_CSI0_D9, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | + PAD_CTL_ODE_OPENDRAIN_ENABLE); +} + +static int power_init(void) +{ + unsigned int val; + int ret = -1; + struct pmic *p; + + if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) { + pmic_dialog_init(); + p = get_pmic(); + + /* Set VDDA to 1.25V */ + val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V; + ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val); + + ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val); + val |= DA9052_SUPPLY_VBCOREGO; + ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val); + + /* Set Vcc peripheral to 1.30V */ + ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62); + ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62); + } + + if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) { + pmic_init(); + p = get_pmic(); + + /* Set VDDGP to 1.25V for 1GHz on SW1 */ + pmic_reg_read(p, REG_SW_0, &val); + val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708; + ret = pmic_reg_write(p, REG_SW_0, val); + + /* Set VCC as 1.30V on SW2 */ + pmic_reg_read(p, REG_SW_1, &val); + val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708; + ret |= pmic_reg_write(p, REG_SW_1, val); + + /* Set global reset timer to 4s */ + pmic_reg_read(p, REG_POWER_CTL2, &val); + val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708; + ret |= pmic_reg_write(p, REG_POWER_CTL2, val); + + /* Set VUSBSEL and VUSBEN for USB PHY supply*/ + pmic_reg_read(p, REG_MODE_0, &val); + val |= (VUSBSEL_MC34708 | VUSBEN_MC34708); + ret |= pmic_reg_write(p, REG_MODE_0, val); + + /* Set SWBST to 5V in auto mode */ + val = SWBST_AUTO; + ret |= pmic_reg_write(p, SWBST_CTRL, val); + } + + return ret; +} + +static void clock_1GHz(void) +{ + int ret; + u32 ref_clk = CONFIG_SYS_MX5_HCLK; + /* + * After increasing voltage to 1.25V, we can switch + * CPU clock to 1GHz and DDR to 400MHz safely + */ + ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); + if (ret) + printf("CPU: Switch CPU clock to 1GHZ failed\n"); + + ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); + ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); + if (ret) + printf("CPU: Switch DDR clock to 400MHz failed\n"); +} + int board_early_init_f(void) { setup_iomux_uart(); @@ -298,10 +410,38 @@ int board_early_init_f(void) return 0; } +int print_cpuinfo(void) +{ + u32 cpurev; + + cpurev = get_cpu_rev(); + printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n", + (cpurev & 0xFF000) >> 12, + (cpurev & 0x000F0) >> 4, + (cpurev & 0x0000F) >> 0, + mxc_get_clock(MXC_ARM_CLK) / 1000000); + printf("Reset cause: %s\n", get_reset_cause()); + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + setup_iomux_i2c(); + if (!power_init()) + clock_1GHz(); + print_cpuinfo(); + + return 0; +} +#endif + int board_init(void) { gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + mxc_set_sata_internal_clock(); + return 0; } diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index fda3e41..29cbfed 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -25,6 +25,7 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/mx6x_pins.h> #include <asm/arch/iomux-v3.h> +#include <asm/arch/clock.h> #include <asm/errno.h> #include <asm/gpio.h> #include <mmc.h> @@ -50,6 +51,10 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) +#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -122,6 +127,22 @@ iomux_v3_cfg_t enet_pads2[] = { MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), }; +/* Button assignments for J14 */ +static iomux_v3_cfg_t button_pads[] = { + /* Menu */ + MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Back */ + MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Labelled Search (mapped to Power under Android) */ + MX6Q_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Home */ + MX6Q_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Volume Down */ + MX6Q_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Volume Up */ + MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), +}; + static void setup_iomux_enet(void) { gpio_direction_output(87, 0); /* GPIO 3-23 */ @@ -135,7 +156,7 @@ static void setup_iomux_enet(void) /* Need delay 10ms according to KSZ9021 spec */ udelay(1000 * 10); - gpio_direction_output(87, 1); /* GPIO 3-23 */ + gpio_set_value(87, 1); /* GPIO 3-23 */ imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); } @@ -267,11 +288,44 @@ int board_eth_init(bd_t *bis) return 0; } +static void setup_buttons(void) +{ + imx_iomux_v3_setup_multiple_pads(button_pads, + ARRAY_SIZE(button_pads)); +} + +#ifdef CONFIG_CMD_SATA + +int setup_sata(void) +{ + struct iomuxc_base_regs *const iomuxc_regs + = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR; + int ret = enable_sata_clock(); + if (ret) + return ret; + + clrsetbits_le32(&iomuxc_regs->gpr[13], + IOMUXC_GPR13_SATA_MASK, + IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB + |IOMUXC_GPR13_SATA_PHY_7_SATA2M + |IOMUXC_GPR13_SATA_SPEED_3G + |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT) + |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED + |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 + |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB + |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V + |IOMUXC_GPR13_SATA_PHY_1_SLOW); + + return 0; +} +#endif + int board_early_init_f(void) { - setup_iomux_uart(); + setup_iomux_uart(); + setup_buttons(); - return 0; + return 0; } int board_init(void) @@ -283,6 +337,10 @@ int board_init(void) setup_spi(); #endif +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif + return 0; } @@ -292,3 +350,94 @@ int checkboard(void) return 0; } + +struct button_key { + char const *name; + unsigned gpnum; + char ident; +}; + +static struct button_key const buttons[] = { + {"back", GPIO_NUMBER(2, 2), 'B'}, + {"home", GPIO_NUMBER(2, 4), 'H'}, + {"menu", GPIO_NUMBER(2, 1), 'M'}, + {"search", GPIO_NUMBER(2, 3), 'S'}, + {"volup", GPIO_NUMBER(7, 13), 'V'}, + {"voldown", GPIO_NUMBER(4, 5), 'v'}, +}; + +/* + * generate a null-terminated string containing the buttons pressed + * returns number of keys pressed + */ +static int read_keys(char *buf) +{ + int i, numpressed = 0; + for (i = 0; i < ARRAY_SIZE(buttons); i++) { + if (!gpio_get_value(buttons[i].gpnum)) + buf[numpressed++] = buttons[i].ident; + } + buf[numpressed] = '\0'; + return numpressed; +} + +static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char envvalue[ARRAY_SIZE(buttons)+1]; + int numpressed = read_keys(envvalue); + setenv("keybd", envvalue); + return numpressed == 0; +} + +U_BOOT_CMD( + kbd, 1, 1, do_kbd, + "Tests for keypresses, sets 'keybd' environment variable", + "Returns 0 (true) to shell if key is pressed." +); + +#ifdef CONFIG_PREBOOT +static char const kbd_magic_prefix[] = "key_magic"; +static char const kbd_command_prefix[] = "key_cmd"; + +static void preboot_keys(void) +{ + int numpressed; + char keypress[ARRAY_SIZE(buttons)+1]; + numpressed = read_keys(keypress); + if (numpressed) { + char *kbd_magic_keys = getenv("magic_keys"); + char *suffix; + /* + * loop over all magic keys + */ + for (suffix = kbd_magic_keys; *suffix; ++suffix) { + char *keys; + char magic[sizeof(kbd_magic_prefix) + 1]; + sprintf(magic, "%s%c", kbd_magic_prefix, *suffix); + keys = getenv(magic); + if (keys) { + if (!strcmp(keys, keypress)) + break; + } + } + if (*suffix) { + char cmd_name[sizeof(kbd_command_prefix) + 1]; + char *cmd; + sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix); + cmd = getenv(cmd_name); + if (cmd) { + setenv("preboot", cmd); + return; + } + } + } +} +#endif + +int misc_init_r(void) +{ +#ifdef CONFIG_PREBOOT + preboot_keys(); +#endif + return 0; +} |