summaryrefslogtreecommitdiff
path: root/board/freescale
diff options
context:
space:
mode:
Diffstat (limited to 'board/freescale')
-rw-r--r--board/freescale/mx6qarm2/Kconfig3
-rw-r--r--board/freescale/mx6qsabreauto/Kconfig3
-rw-r--r--board/freescale/mx6qsabreauto/MAINTAINERS2
-rw-r--r--board/freescale/mx6sabresd/Kconfig3
-rw-r--r--board/freescale/mx6slevk/Kconfig3
-rw-r--r--board/freescale/mx6slevk/MAINTAINERS2
-rw-r--r--board/freescale/mx6sxsabresd/Kconfig3
-rw-r--r--board/freescale/mx6ul_14x14_evk/Kconfig5
-rw-r--r--board/freescale/mx6ul_14x14_evk/MAINTAINERS1
-rw-r--r--board/freescale/mx6ul_14x14_evk/README32
-rw-r--r--board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c235
-rw-r--r--board/freescale/mx7dsabresd/Kconfig12
-rw-r--r--board/freescale/mx7dsabresd/MAINTAINERS6
-rw-r--r--board/freescale/mx7dsabresd/Makefile6
-rw-r--r--board/freescale/mx7dsabresd/imximage.cfg94
-rw-r--r--board/freescale/mx7dsabresd/mx7dsabresd.c507
-rw-r--r--board/freescale/vf610twr/vf610twr.c156
17 files changed, 921 insertions, 152 deletions
diff --git a/board/freescale/mx6qarm2/Kconfig b/board/freescale/mx6qarm2/Kconfig
index 4af33af..8ab8b46 100644
--- a/board/freescale/mx6qarm2/Kconfig
+++ b/board/freescale/mx6qarm2/Kconfig
@@ -6,9 +6,6 @@ config SYS_BOARD
config SYS_VENDOR
default "freescale"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "mx6qarm2"
diff --git a/board/freescale/mx6qsabreauto/Kconfig b/board/freescale/mx6qsabreauto/Kconfig
index cc2a140..e579c0f 100644
--- a/board/freescale/mx6qsabreauto/Kconfig
+++ b/board/freescale/mx6qsabreauto/Kconfig
@@ -6,9 +6,6 @@ config SYS_BOARD
config SYS_VENDOR
default "freescale"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "mx6qsabreauto"
diff --git a/board/freescale/mx6qsabreauto/MAINTAINERS b/board/freescale/mx6qsabreauto/MAINTAINERS
index fb65ce4..75a8862 100644
--- a/board/freescale/mx6qsabreauto/MAINTAINERS
+++ b/board/freescale/mx6qsabreauto/MAINTAINERS
@@ -1,7 +1,9 @@
MX6QSABREAUTO BOARD
M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Peng Fan <Peng.Fan@freescale.com>
S: Maintained
F: board/freescale/mx6qsabreauto/
F: include/configs/mx6qsabreauto.h
F: configs/mx6dlsabreauto_defconfig
F: configs/mx6qsabreauto_defconfig
+F: configs/mx6qpsabreauto_defconfig
diff --git a/board/freescale/mx6sabresd/Kconfig b/board/freescale/mx6sabresd/Kconfig
index fa6ddb2..e87dea0 100644
--- a/board/freescale/mx6sabresd/Kconfig
+++ b/board/freescale/mx6sabresd/Kconfig
@@ -6,9 +6,6 @@ config SYS_BOARD
config SYS_VENDOR
default "freescale"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "mx6sabresd"
diff --git a/board/freescale/mx6slevk/Kconfig b/board/freescale/mx6slevk/Kconfig
index d32da90..18482b5 100644
--- a/board/freescale/mx6slevk/Kconfig
+++ b/board/freescale/mx6slevk/Kconfig
@@ -6,9 +6,6 @@ config SYS_BOARD
config SYS_VENDOR
default "freescale"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "mx6slevk"
diff --git a/board/freescale/mx6slevk/MAINTAINERS b/board/freescale/mx6slevk/MAINTAINERS
index 18d31a8..f4e74ba 100644
--- a/board/freescale/mx6slevk/MAINTAINERS
+++ b/board/freescale/mx6slevk/MAINTAINERS
@@ -1,7 +1,9 @@
MX6SLEVK BOARD
M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Peng Fan <Peng.Fan@freescale.com>
S: Maintained
F: board/freescale/mx6slevk/
F: include/configs/mx6slevk.h
F: configs/mx6slevk_defconfig
+F: configs/mx6slevk_spl_defconfig
F: configs/mx6slevk_spinor_defconfig
diff --git a/board/freescale/mx6sxsabresd/Kconfig b/board/freescale/mx6sxsabresd/Kconfig
index 940983e..fcfac0a 100644
--- a/board/freescale/mx6sxsabresd/Kconfig
+++ b/board/freescale/mx6sxsabresd/Kconfig
@@ -6,9 +6,6 @@ config SYS_BOARD
config SYS_VENDOR
default "freescale"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "mx6sxsabresd"
diff --git a/board/freescale/mx6ul_14x14_evk/Kconfig b/board/freescale/mx6ul_14x14_evk/Kconfig
index 393aca6..8210cd3 100644
--- a/board/freescale/mx6ul_14x14_evk/Kconfig
+++ b/board/freescale/mx6ul_14x14_evk/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_MX6UL_14X14_EVK
+if TARGET_MX6UL_14X14_EVK || TARGET_MX6UL_9X9_EVK
config SYS_BOARD
default "mx6ul_14x14_evk"
@@ -6,9 +6,6 @@ config SYS_BOARD
config SYS_VENDOR
default "freescale"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "mx6ul_14x14_evk"
diff --git a/board/freescale/mx6ul_14x14_evk/MAINTAINERS b/board/freescale/mx6ul_14x14_evk/MAINTAINERS
index 611feca..d5f74b7 100644
--- a/board/freescale/mx6ul_14x14_evk/MAINTAINERS
+++ b/board/freescale/mx6ul_14x14_evk/MAINTAINERS
@@ -4,3 +4,4 @@ S: Maintained
F: board/freescale/mx6ul_14x14_evk/
F: include/configs/mx6ul_14x14_evk.h
F: configs/mx6ul_14x14_evk_defconfig
+F: configs/mx6ul_9x9_evk_defconfig
diff --git a/board/freescale/mx6ul_14x14_evk/README b/board/freescale/mx6ul_14x14_evk/README
new file mode 100644
index 0000000..d48c7ba
--- /dev/null
+++ b/board/freescale/mx6ul_14x14_evk/README
@@ -0,0 +1,32 @@
+How to use U-boot on Freescale MX6UL 14x14 EVK
+-----------------------------------------------
+
+- Build U-boot for MX6UL 14x14 EVK:
+
+$ make mrproper
+$ make mx6ul_14x14_evk_defconfig
+$ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the micro SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot.img image into the micro SD card:
+
+sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Jumper settings:
+
+SW601: 0 0 1 0
+Sw602: 1 0
+
+where 0 means bottom position and 1 means top position (from the
+switch label numbers reference).
+
+- Connect the USB cable between the EVK and the PC for the console.
+(The USB console connector is the one close the push buttons)
+
+- Insert the micro SD card in the board, power it up and U-boot messages should
+come up.
diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index c09d84e..8650f35 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -23,6 +23,9 @@
#include <linux/sizes.h>
#include <mmc.h>
#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+#include "../common/pfuze.h"
#include <usb.h>
#include <usb/ehci-fsl.h>
@@ -152,53 +155,10 @@ static void iox74lv_init(void)
gpio_direction_output(IOX_OE, 1);
};
-void iox74lv_set(int index)
-{
- int i;
-
- gpio_direction_output(IOX_OE, 0);
-
- for (i = 7; i >= 0; i--) {
- gpio_direction_output(IOX_SHCP, 0);
-
- if (i == index)
- gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
- else
- gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
- udelay(500);
- gpio_direction_output(IOX_SHCP, 1);
- udelay(500);
- }
-
- gpio_direction_output(IOX_STCP, 0);
- udelay(500);
- /*
- * shift register will be output to pins
- */
- gpio_direction_output(IOX_STCP, 1);
-
- for (i = 7; i >= 0; i--) {
- gpio_direction_output(IOX_SHCP, 0);
- gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
- udelay(500);
- gpio_direction_output(IOX_SHCP, 1);
- udelay(500);
- }
-
- gpio_direction_output(IOX_STCP, 0);
- udelay(500);
- /*
- * shift register will be output to pins
- */
- gpio_direction_output(IOX_STCP, 1);
-
- gpio_direction_output(IOX_OE, 1);
-};
-
#ifdef CONFIG_SYS_I2C_MXC
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1 for PMIC and EEPROM */
-struct i2c_pads_info i2c_pad_info1 = {
+static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC,
.gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC,
@@ -210,11 +170,56 @@ struct i2c_pads_info i2c_pad_info1 = {
.gp = IMX_GPIO_NR(1, 29),
},
};
+
+#ifdef CONFIG_POWER
+#define I2C_PMIC 0
+int power_init_board(void)
+{
+ if (is_mx6ul_9x9_evk()) {
+ struct pmic *pfuze;
+ int ret;
+ unsigned int reg, rev_id;
+
+ ret = power_pfuze3000_init(I2C_PMIC);
+ if (ret)
+ return ret;
+
+ pfuze = pmic_get("PFUZE3000");
+ ret = pmic_probe(pfuze);
+ if (ret)
+ return ret;
+
+ pmic_reg_read(pfuze, PFUZE3000_DEVICEID, &reg);
+ pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
+ printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n",
+ reg, rev_id);
+
+ /* disable Low Power Mode during standby mode */
+ pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, &reg);
+ reg |= 0x1;
+ pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg);
+
+ /* SW1B step ramp up time from 2us to 4us/25mV */
+ reg = 0x40;
+ pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg);
+
+ /* SW1B mode to APS/PFM */
+ reg = 0xc;
+ pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg);
+
+ /* SW1B standby voltage set to 0.975V */
+ reg = 0xb;
+ pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg);
+ }
+
+ return 0;
+}
+#endif
#endif
int dram_init(void)
{
- gd->ram_size = PHYS_SDRAM_SIZE;
+ gd->ram_size = imx_ddr_size();
return 0;
}
@@ -308,7 +313,7 @@ static iomux_v3_cfg_t const quadspi_pads[] = {
MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
};
-int board_qspi_init(void)
+static int board_qspi_init(void)
{
/* Set the iomux */
imx_iomux_v3_setup_multiple_pads(quadspi_pads,
@@ -614,17 +619,24 @@ int board_late_init(void)
add_board_boot_modes(board_boot_modes);
#endif
- return 0;
-}
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ setenv("board_name", "EVK");
-u32 get_board_rev(void)
-{
- return get_cpu_rev();
+ if (is_mx6ul_9x9_evk())
+ setenv("board_rev", "9X9");
+ else
+ setenv("board_rev", "14X14");
+#endif
+
+ return 0;
}
int checkboard(void)
{
- puts("Board: MX6UL 14x14 EVK\n");
+ if (is_mx6ul_9x9_evk())
+ puts("Board: MX6UL 9x9 EVK\n");
+ else
+ puts("Board: MX6UL 14x14 EVK\n");
return 0;
}
@@ -634,7 +646,76 @@ int checkboard(void)
#include <spl.h>
#include <asm/arch/mx6-ddr.h>
-const struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+ .grp_addds = 0x00000030,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_b0ds = 0x00000030,
+ .grp_ctlds = 0x00000030,
+ .grp_b1ds = 0x00000030,
+ .grp_ddrpke = 0x00000000,
+ .grp_ddrmode = 0x00020000,
+#ifdef CONFIG_TARGET_MX6UL_9X9_EVK
+ .grp_ddr_type = 0x00080000,
+#else
+ .grp_ddr_type = 0x000c0000,
+#endif
+};
+
+#ifdef CONFIG_TARGET_MX6UL_9X9_EVK
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+ .dram_dqm0 = 0x00000030,
+ .dram_dqm1 = 0x00000030,
+ .dram_ras = 0x00000030,
+ .dram_cas = 0x00000030,
+ .dram_odt0 = 0x00000000,
+ .dram_odt1 = 0x00000000,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdclk_0 = 0x00000030,
+ .dram_sdqs0 = 0x00003030,
+ .dram_sdqs1 = 0x00003030,
+ .dram_reset = 0x00000030,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x00000000,
+ .p0_mpdgctrl0 = 0x20000000,
+ .p0_mprddlctl = 0x4040484f,
+ .p0_mpwrdlctl = 0x40405247,
+ .mpzqlp2ctl = 0x1b4700c7,
+};
+
+static struct mx6_lpddr2_cfg mem_ddr = {
+ .mem_speed = 800,
+ .density = 2,
+ .width = 16,
+ .banks = 4,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .trcd_lp = 1500,
+ .trppb_lp = 1500,
+ .trpab_lp = 2000,
+ .trasmin = 4250,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+ .dsize = 0,
+ .cs_density = 18,
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .walat = 0,
+ .ralat = 5,
+ .mif3_mode = 3,
+ .bi_on = 1,
+ .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
+ .rtt_nom = 0,
+ .sde_to_rst = 0, /* LPDDR2 does not need this field */
+ .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
+ .ddr_type = DDR_TYPE_LPDDR2,
+};
+
+#else
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_dqm0 = 0x00000030,
.dram_dqm1 = 0x00000030,
.dram_ras = 0x00000030,
@@ -648,24 +729,29 @@ const struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_reset = 0x00000030,
};
-const struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
- .grp_addds = 0x00000030,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_b0ds = 0x00000030,
- .grp_ctlds = 0x00000030,
- .grp_b1ds = 0x00000030,
- .grp_ddrpke = 0x00000000,
- .grp_ddrmode = 0x00020000,
- .grp_ddr_type = 0x000c0000,
-};
-
-const struct mx6_mmdc_calibration mx6_mmcd_calib = {
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
.p0_mpwldectrl0 = 0x00070007,
.p0_mpdgctrl0 = 0x41490145,
.p0_mprddlctl = 0x40404546,
.p0_mpwrdlctl = 0x4040524D,
};
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+ .dsize = 0,
+ .cs_density = 20,
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 2,
+ .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
+ .walat = 1, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .ddr_type = DDR_TYPE_DDR3,
+};
+
static struct mx6_ddr3_cfg mem_ddr = {
.mem_speed = 800,
.density = 4,
@@ -678,6 +764,7 @@ static struct mx6_ddr3_cfg mem_ddr = {
.trcmin = 4875,
.trasmin = 3500,
};
+#endif
static void ccgr_init(void)
{
@@ -695,24 +782,8 @@ static void ccgr_init(void)
static void spl_dram_init(void)
{
- struct mx6_ddr_sysinfo sysinfo = {
- .dsize = 0,
- .cs_density = 20,
- .ncs = 1,
- .cs1_mirror = 0,
- .rtt_wr = 2,
- .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
- .walat = 1, /* Write additional latency */
- .ralat = 5, /* Read additional latency */
- .mif3_mode = 3, /* Command prediction working mode */
- .bi_on = 1, /* Bank interleaving enabled */
- .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
- .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
- .ddr_type = DDR_TYPE_DDR3,
- };
-
mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
- mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
+ mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
}
void board_init_f(ulong dummy)
diff --git a/board/freescale/mx7dsabresd/Kconfig b/board/freescale/mx7dsabresd/Kconfig
new file mode 100644
index 0000000..c6a969c
--- /dev/null
+++ b/board/freescale/mx7dsabresd/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX7DSABRESD
+
+config SYS_BOARD
+ default "mx7dsabresd"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "mx7dsabresd"
+
+endif
diff --git a/board/freescale/mx7dsabresd/MAINTAINERS b/board/freescale/mx7dsabresd/MAINTAINERS
new file mode 100644
index 0000000..3910ee4
--- /dev/null
+++ b/board/freescale/mx7dsabresd/MAINTAINERS
@@ -0,0 +1,6 @@
+MX7DSABRESD BOARD
+M: Adrian Alonso <aalonso@freescale.com>
+S: Maintained
+F: board/freescale/mx7dsabresd
+F: include/configs/mx7dsabresd.h
+F: configs/mx7dsabresd_defconfig
diff --git a/board/freescale/mx7dsabresd/Makefile b/board/freescale/mx7dsabresd/Makefile
new file mode 100644
index 0000000..14336ab
--- /dev/null
+++ b/board/freescale/mx7dsabresd/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2015 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx7dsabresd.o
diff --git a/board/freescale/mx7dsabresd/imximage.cfg b/board/freescale/mx7dsabresd/imximage.cfg
new file mode 100644
index 0000000..91b70ee
--- /dev/null
+++ b/board/freescale/mx7dsabresd/imximage.cfg
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : sd
+ */
+
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+DATA 4 0x30340004 0x4F400005
+
+DATA 4 0x30391000 0x00000002
+DATA 4 0x307a0000 0x01040001
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+DATA 4 0x307a0064 0x00400046
+DATA 4 0x307a0490 0x00000001
+DATA 4 0x307a00d0 0x00020083
+DATA 4 0x307a00d4 0x00690000
+DATA 4 0x307a00dc 0x09300004
+DATA 4 0x307a00e0 0x04080000
+DATA 4 0x307a00e4 0x00100004
+DATA 4 0x307a00f4 0x0000033f
+DATA 4 0x307a0100 0x09081109
+DATA 4 0x307a0104 0x0007020d
+DATA 4 0x307a0108 0x03040407
+DATA 4 0x307a010c 0x00002006
+DATA 4 0x307a0110 0x04020205
+DATA 4 0x307a0114 0x03030202
+DATA 4 0x307a0120 0x00000803
+DATA 4 0x307a0180 0x00800020
+DATA 4 0x307a0184 0x02000100
+DATA 4 0x307a0190 0x02098204
+DATA 4 0x307a0194 0x00030303
+DATA 4 0x307a0200 0x00000016
+DATA 4 0x307a0204 0x00171717
+DATA 4 0x307a0214 0x04040404
+DATA 4 0x307a0218 0x0f040404
+DATA 4 0x307a0240 0x06000604
+DATA 4 0x307a0244 0x00000001
+DATA 4 0x30391000 0x00000000
+DATA 4 0x30790000 0x17420f40
+DATA 4 0x30790004 0x10210100
+DATA 4 0x30790010 0x00060807
+DATA 4 0x307900b0 0x1010007e
+DATA 4 0x3079009c 0x00000d6e
+DATA 4 0x30790020 0x08080808
+DATA 4 0x30790030 0x08080808
+DATA 4 0x30790050 0x01000010
+DATA 4 0x30790050 0x00000010
+
+DATA 4 0x307900c0 0x0e407304
+DATA 4 0x307900c0 0x0e447304
+DATA 4 0x307900c0 0x0e447306
+
+CHECK_BITS_SET 4 0x307900c4 0x1
+
+DATA 4 0x307900c0 0x0e447304
+DATA 4 0x307900c0 0x0e407304
+
+DATA 4 0x30384130 0x00000000
+DATA 4 0x30340020 0x00000178
+DATA 4 0x30384130 0x00000002
+DATA 4 0x30790018 0x0000000f
+
+CHECK_BITS_SET 4 0x307a0004 0x1
diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c
new file mode 100644
index 0000000..ee9890b
--- /dev/null
+++ b/board/freescale/mx7dsabresd/mx7dsabresd.c
@@ -0,0 +1,507 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+#include "../common/pfuze.h"
+#include <i2c.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/arch/crm_regs.h>
+#include <usb/ehci-fsl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
+ PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+ PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
+#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
+
+#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
+
+#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+ PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
+
+#ifdef CONFIG_SYS_I2C_MXC
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC */
+static struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
+ .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
+ .gp = IMX_GPIO_NR(4, 8),
+ },
+ .sda = {
+ .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
+ .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
+ .gp = IMX_GPIO_NR(4, 9),
+ },
+};
+#endif
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
+ MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+#define IOX_SDI IMX_GPIO_NR(1, 9)
+#define IOX_STCP IMX_GPIO_NR(1, 12)
+#define IOX_SHCP IMX_GPIO_NR(1, 13)
+
+static iomux_v3_cfg_t const iox_pads[] = {
+ /* IOX_SDI */
+ MX7D_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* IOX_STCP */
+ MX7D_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* IOX_SHCP */
+ MX7D_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+/*
+ * PCIE_DIS_B --> Q0
+ * PCIE_RST_B --> Q1
+ * HDMI_RST_B --> Q2
+ * PERI_RST_B --> Q3
+ * SENSOR_RST_B --> Q4
+ * ENET_RST_B --> Q5
+ * PERI_3V3_EN --> Q6
+ * LCD_PWR_EN --> Q7
+ */
+enum qn {
+ PCIE_DIS_B,
+ PCIE_RST_B,
+ HDMI_RST_B,
+ PERI_RST_B,
+ SENSOR_RST_B,
+ ENET_RST_B,
+ PERI_3V3_EN,
+ LCD_PWR_EN,
+};
+
+enum qn_func {
+ qn_reset,
+ qn_enable,
+ qn_disable,
+};
+
+enum qn_level {
+ qn_low = 0,
+ qn_high = 1,
+};
+
+static enum qn_level seq[3][2] = {
+ {0, 1}, {1, 1}, {0, 0}
+};
+
+static enum qn_func qn_output[8] = {
+ qn_disable, qn_reset, qn_reset, qn_reset, qn_reset, qn_reset, qn_enable,
+ qn_enable
+};
+
+static void iox74lv_init(void)
+{
+ int i;
+
+ for (i = 7; i >= 0; i--) {
+ gpio_direction_output(IOX_SHCP, 0);
+ gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
+ udelay(500);
+ gpio_direction_output(IOX_SHCP, 1);
+ udelay(500);
+ }
+
+ gpio_direction_output(IOX_STCP, 0);
+ udelay(500);
+ /*
+ * shift register will be output to pins
+ */
+ gpio_direction_output(IOX_STCP, 1);
+
+ for (i = 7; i >= 0; i--) {
+ gpio_direction_output(IOX_SHCP, 0);
+ gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
+ udelay(500);
+ gpio_direction_output(IOX_SHCP, 1);
+ udelay(500);
+ }
+ gpio_direction_output(IOX_STCP, 0);
+ udelay(500);
+ /*
+ * shift register will be output to pins
+ */
+ gpio_direction_output(IOX_STCP, 1);
+};
+
+#ifdef CONFIG_FEC_MXC
+static iomux_v3_cfg_t const fec1_pads[] = {
+ MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
+ MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
+};
+
+static void setup_iomux_fec(void)
+{
+ imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
+}
+#endif
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+
+#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2)
+#define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11)
+
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+ {USDHC1_BASE_ADDR, 0, 4},
+ {USDHC3_BASE_ADDR},
+};
+
+static int mmc_get_env_devno(void)
+{
+ struct bootrom_sw_info **p =
+ (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
+
+ u8 boot_type = (*p)->boot_dev_type;
+ u8 dev_no = (*p)->boot_dev_instance;
+
+ /* If not boot from sd/mmc, use default value */
+ if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
+ return CONFIG_SYS_MMC_ENV_DEV;
+
+ if (dev_no == 2)
+ dev_no--;
+
+ return dev_no;
+}
+
+static int mmc_map_to_kernel_blk(int dev_no)
+{
+ if (dev_no == 1)
+ dev_no++;
+
+ return dev_no;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ ret = !gpio_get_value(USDHC1_CD_GPIO);
+ break;
+ case USDHC3_BASE_ADDR:
+ ret = 1; /* Assume uSDHC3 emmc is always present */
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int i, ret;
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 USDHC1
+ * mmc2 USDHC3 (eMMC)
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
+ gpio_direction_input(USDHC1_CD_GPIO);
+ gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr");
+ gpio_direction_output(USDHC1_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(USDHC1_PWR_GPIO, 1);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));
+ gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr");
+ gpio_direction_output(USDHC3_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(USDHC3_PWR_GPIO, 1);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) than supported by the board\n", i + 1);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int check_mmc_autodetect(void)
+{
+ char *autodetect_str = getenv("mmcautodetect");
+
+ if ((autodetect_str != NULL) &&
+ (strcmp(autodetect_str, "yes") == 0)) {
+ return 1;
+ }
+
+ return 0;
+}
+
+static void mmc_late_init(void)
+{
+ char cmd[32];
+ char mmcblk[32];
+ u32 dev_no = mmc_get_env_devno();
+
+ if (!check_mmc_autodetect())
+ return;
+
+ setenv_ulong("mmcdev", dev_no);
+
+ /* Set mmcblk env */
+ sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
+ mmc_map_to_kernel_blk(dev_no));
+ setenv("mmcroot", mmcblk);
+
+ sprintf(cmd, "mmc dev %d", dev_no);
+ run_command(cmd, 0);
+}
+
+#endif
+
+#ifdef CONFIG_FEC_MXC
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+
+ setup_iomux_fec();
+
+ ret = fecmxc_initialize_multi(bis, 0,
+ CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+ if (ret)
+ printf("FEC1 MXC: %s:failed\n", __func__);
+
+ return ret;
+}
+
+static int setup_fec(void)
+{
+ struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
+ = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
+
+ /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
+ clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+ (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
+ IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
+
+ return set_clk_enet(ENET_125MHz);
+}
+
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /* enable rgmii rxc skew and phy mode select to RGMII copper */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+ return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));
+
+ iox74lv_init();
+
+#ifdef CONFIG_FEC_MXC
+ setup_fec();
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_POWER
+#define I2C_PMIC 0
+int power_init_board(void)
+{
+ struct pmic *p;
+ int ret;
+ unsigned int reg, rev_id;
+
+ ret = power_pfuze3000_init(I2C_PMIC);
+ if (ret)
+ return ret;
+
+ p = pmic_get("PFUZE3000");
+ ret = pmic_probe(p);
+ if (ret)
+ return ret;
+
+ pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
+ pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
+ printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
+
+ /* disable Low Power Mode during standby mode */
+ pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);
+ reg |= 0x1;
+ pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
+
+ return 0;
+}
+#endif
+
+int board_late_init(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+ mmc_late_init();
+#endif
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+ set_wdog_reset(wdog);
+
+ /*
+ * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
+ * since we use PMIC_PWRON to reset the board.
+ */
+ clrsetbits_le16(&wdog->wcr, 0, 0x10);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: i.MX7D SABRESD\n");
+
+ return 0;
+}
+
+#ifdef CONFIG_USB_EHCI_MX7
+static iomux_v3_cfg_t const usb_otg1_pads[] = {
+ MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usb_otg2_pads[] = {
+ MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_ehci_hcd_init(int port)
+{
+ switch (port) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
+ ARRAY_SIZE(usb_otg1_pads));
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
+ ARRAY_SIZE(usb_otg2_pads));
+ break;
+ default:
+ printf("MXC USB port %d not yet supported\n", port);
+ return -EINVAL;
+ }
+ return 0;
+}
+#endif
diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c
index 4160acd..7834931 100644
--- a/board/freescale/vf610twr/vf610twr.c
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -28,63 +28,117 @@ DECLARE_GLOBAL_DATA_PTR;
#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
+static struct ddrmc_cr_setting vf610twr_cr_settings[] = {
+ /* levelling */
+ { DDRMC_CR97_WRLVL_EN, 97 },
+ { DDRMC_CR98_WRLVL_DL_0(0), 98 },
+ { DDRMC_CR99_WRLVL_DL_1(0), 99 },
+ { DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 },
+ { DDRMC_CR105_RDLVL_DL_0(0), 105 },
+ { DDRMC_CR106_RDLVL_GTDL_0(4), 106 },
+ { DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 },
+ /* AXI */
+ { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
+ { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
+ { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
+ DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
+ { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
+ DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
+ { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
+ DDRMC_CR122_AXI0_PRIRLX(100), 122 },
+ { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
+ DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
+ { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
+ { DDRMC_CR126_PHY_RDLAT(8), 126 },
+ { DDRMC_CR132_WRLAT_ADJ(5) |
+ DDRMC_CR132_RDLAT_ADJ(6), 132 },
+ { DDRMC_CR137_PHYCTL_DL(2), 137 },
+ { DDRMC_CR138_PHY_WRLV_MXDL(256) |
+ DDRMC_CR138_PHYDRAM_CK_EN(1), 138 },
+ { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
+ DDRMC_CR139_PHY_WRLV_DLL(3) |
+ DDRMC_CR139_PHY_WRLV_EN(3), 139 },
+ { DDRMC_CR140_PHY_WRLV_WW(64), 140 },
+ { DDRMC_CR143_RDLV_GAT_MXDL(1536) |
+ DDRMC_CR143_RDLV_MXDL(128), 143 },
+ { DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
+ DDRMC_CR144_PHY_RDLV_DLL(3) |
+ DDRMC_CR144_PHY_RDLV_EN(3), 144 },
+ { DDRMC_CR145_PHY_RDLV_RR(64), 145 },
+ { DDRMC_CR146_PHY_RDLVL_RESP(64), 146 },
+ { DDRMC_CR147_RDLV_RESP_MASK(983040), 147 },
+ { DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 },
+ { DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
+ DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 },
+
+ { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
+ DDRMC_CR154_PAD_ZQ_MODE(1) |
+ DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
+ DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
+ { DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 },
+ { DDRMC_CR158_TWR(6), 158 },
+ { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
+ DDRMC_CR161_TODTH_WR(2), 161 },
+ /* end marker */
+ { 0, -1 }
+};
+
int dram_init(void)
{
- struct ddrmc_lvl_info lvl = {
- .wrlvl_reg_en = 1,
- .wrlvl_dl_0 = 0,
- .wrlvl_dl_1 = 0,
- .rdlvl_gt_reg_en = 1,
- .rdlvl_gt_dl_0 = 4,
- .rdlvl_gt_dl_1 = 4,
- .rdlvl_reg_en = 1,
- .rdlvl_dl_0 = 0,
- .rdlvl_dl_1 = 0,
- };
-
static const struct ddr3_jedec_timings timings = {
- .tinit = 5,
- .trst_pwron = 80000,
- .cke_inactive = 200000,
- .wrlat = 5,
- .caslat_lin = 12,
- .trc = 21,
- .trrd = 4,
- .tccd = 4,
- .tfaw = 20,
- .trp = 6,
- .twtr = 4,
- .tras_min = 15,
- .tmrd = 4,
- .trtp = 4,
- .tras_max = 28080,
- .tmod = 12,
- .tckesr = 4,
- .tcke = 3,
- .trcd_int = 6,
- .tdal = 12,
- .tdll = 512,
- .trp_ab = 6,
- .tref = 3120,
- .trfc = 44,
- .tpdex = 3,
- .txpdll = 10,
- .txsnr = 48,
- .txsr = 468,
- .cksrx = 5,
- .cksre = 5,
- .zqcl = 256,
- .zqinit = 512,
- .zqcs = 64,
- .ref_per_zq = 64,
- .aprebit = 10,
- .wlmrd = 40,
- .wldqsen = 25,
+ .tinit = 5,
+ .trst_pwron = 80000,
+ .cke_inactive = 200000,
+ .wrlat = 5,
+ .caslat_lin = 12,
+ .trc = 21,
+ .trrd = 4,
+ .tccd = 4,
+ .tbst_int_interval = 0,
+ .tfaw = 20,
+ .trp = 6,
+ .twtr = 4,
+ .tras_min = 15,
+ .tmrd = 4,
+ .trtp = 4,
+ .tras_max = 28080,
+ .tmod = 12,
+ .tckesr = 4,
+ .tcke = 3,
+ .trcd_int = 6,
+ .tras_lockout = 0,
+ .tdal = 12,
+ .bstlen = 0,
+ .tdll = 512,
+ .trp_ab = 6,
+ .tref = 3120,
+ .trfc = 44,
+ .tref_int = 0,
+ .tpdex = 3,
+ .txpdll = 10,
+ .txsnr = 48,
+ .txsr = 468,
+ .cksrx = 5,
+ .cksre = 5,
+ .freq_chg_en = 0,
+ .zqcl = 256,
+ .zqinit = 512,
+ .zqcs = 64,
+ .ref_per_zq = 64,
+ .zqcs_rotate = 0,
+ .aprebit = 10,
+ .cmd_age_cnt = 64,
+ .age_cnt = 64,
+ .q_fullness = 7,
+ .odt_rd_mapcs0 = 0,
+ .odt_wr_mapcs0 = 1,
+ .wlmrd = 40,
+ .wldqsen = 25,
};
- ddrmc_setup_iomux();
+ ddrmc_setup_iomux(NULL, 0);
- ddrmc_ctrl_init_ddr3(&timings, &lvl, 1, 3);
+ ddrmc_ctrl_init_ddr3(&timings, vf610twr_cr_settings, NULL, 1, 3);
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
return 0;
generated by cgit v0.10.2 at 2024-08-04 13:47:08 (GMT)