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-rw-r--r--board/freescale/m52277evb/README231
-rw-r--r--board/freescale/m5253evbe/README103
-rw-r--r--board/freescale/m53017evb/README180
-rw-r--r--board/freescale/m5373evb/README326
-rw-r--r--board/freescale/m54455evb/README409
-rw-r--r--board/freescale/m547xevb/README272
-rw-r--r--board/freescale/mpc7448hpc2/README184
-rw-r--r--board/freescale/mpc8313erdb/README111
-rw-r--r--board/freescale/mpc8315erdb/README105
-rw-r--r--board/freescale/mpc8323erdb/README71
-rw-r--r--board/freescale/mpc832xemds/README128
-rw-r--r--board/freescale/mpc8349itx/README187
-rw-r--r--board/freescale/mpc8360emds/README155
-rw-r--r--board/freescale/mpc837xemds/README104
-rw-r--r--board/freescale/mpc837xerdb/README97
-rw-r--r--board/freescale/mpc8536ds/README127
-rw-r--r--board/freescale/mpc8544ds/README122
-rw-r--r--board/freescale/mpc8569mds/README77
-rw-r--r--board/freescale/mpc8572ds/README166
-rw-r--r--board/freescale/mpc8610hpcd/README73
-rw-r--r--board/freescale/mpc8641hpcn/README186
-rw-r--r--board/freescale/mx35pdk/README188
-rw-r--r--board/freescale/mx6qsabrelite/README72
-rw-r--r--board/freescale/p1022ds/README23
-rw-r--r--board/freescale/p1023rds/README101
-rw-r--r--board/freescale/p1_p2_rdb/README145
-rw-r--r--board/freescale/p1_p2_rdb_pc/README46
-rw-r--r--board/freescale/p2041rdb/README123
-rw-r--r--board/freescale/p3060qds/README110
29 files changed, 4222 insertions, 0 deletions
diff --git a/board/freescale/m52277evb/README b/board/freescale/m52277evb/README
new file mode 100644
index 0000000..b6e955b
--- /dev/null
+++ b/board/freescale/m52277evb/README
@@ -0,0 +1,231 @@
+Freescale MCF52277EVB ColdFire Development Board
+================================================
+
+TsiChung Liew(Tsi-Chung.Liew@freescale.com)
+Created Jan 8, 2008
+===========================================
+
+
+Changed files:
+==============
+
+- board/freescale/m52277evb/m52277evb.c Dram setup
+- board/freescale/m52277evb/Makefile Makefile
+- board/freescale/m52277evb/config.mk config make
+- board/freescale/m52277evb/u-boot.lds Linker description
+
+- arch/m68k/cpu/mcf5227x/cpu.c cpu specific code
+- arch/m68k/cpu/mcf5227x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
+- arch/m68k/cpu/mcf5227x/interrupts.c cpu specific interrupt support
+- arch/m68k/cpu/mcf5227x/speed.c system, flexbus, and cpu clock
+- arch/m68k/cpu/mcf5227x/Makefile Makefile
+- arch/m68k/cpu/mcf5227x/config.mk config make
+- arch/m68k/cpu/mcf5227x/start.S start up assembly code
+
+- doc/README.m52277evb This readme file
+
+- drivers/serial/mcfuart.c ColdFire common UART driver
+- drivers/rtc/mcfrtc.c Realtime clock Driver
+
+- include/asm-m68k/bitops.h Bit operation function export
+- include/asm-m68k/byteorder.h Byte order functions
+- include/asm-m68k/crossbar.h CrossBar structure and definition
+- include/asm-m68k/dspi.h DSPI structure and definition
+- include/asm-m68k/edma.h eDMA structure and definition
+- include/asm-m68k/flexbus.h FlexBus structure and definition
+- include/asm-m68k/fsl_i2c.h I2C structure and definition
+- include/asm-m68k/global_data.h Global data structure
+- include/asm-m68k/immap.h ColdFire specific header file and driver macros
+- include/asm-m68k/immap_5227x.h mcf5227x specific header file
+- include/asm-m68k/io.h io functions
+- include/asm-m68k/lcd.h LCD structure and definition
+- include/asm-m68k/m5227x.h mcf5227x specific header file
+- include/asm-m68k/posix_types.h Posix
+- include/asm-m68k/processor.h header file
+- include/asm-m68k/ptrace.h Exception structure
+- include/asm-m68k/rtc.h Realtime clock header file
+- include/asm-m68k/ssi.h SSI structure and definition
+- include/asm-m68k/string.h String function export
+- include/asm-m68k/timer.h Timer structure and definition
+- include/asm-m68k/types.h Data types definition
+- include/asm-m68k/uart.h Uart structure and definition
+- include/asm-m68k/u-boot.h u-boot structure
+
+- include/configs/M52277EVB.h Board specific configuration file
+
+- arch/m68k/lib/board.c board init function
+- arch/m68k/lib/cache.c
+- arch/m68k/lib/interrupts Coldfire common interrupt functions
+- arch/m68k/lib/m68k_linux.c
+- arch/m68k/lib/time.c Timer functions (Dma timer and PIT)
+- arch/m68k/lib/traps.c Exception init code
+
+1 MCF52277 specific Options/Settings
+====================================
+1.1 pre-loader is no longer suppoer in this coldfire family
+
+1.2 Configuration settings for M52277EVB Development Board
+CONFIG_MCF5227x -- define for all MCF5227x CPUs
+CONFIG_M52277 -- define for all Freescale MCF52277 CPUs
+CONFIG_M52277EVB -- define for M52277EVB board
+
+CONFIG_MCFUART -- define to use common CF Uart driver
+CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
+CONFIG_BAUDRATE -- define UART baudrate
+
+CONFIG_MCFRTC -- define to use common CF RTC driver
+CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h
+CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency
+RTC_DEBUG -- define to show RTC debug message
+CONFIG_CMD_DATE -- enable to use date feature in u-boot
+
+CONFIG_MCFTMR -- define to use DMA timer
+CONFIG_MCFPIT -- define to use PIT timer
+
+CONFIG_FSL_I2C -- define to use FSL common I2C driver
+CONFIG_HARD_I2C -- define for I2C hardware support
+CONFIG_SOFT_I2C -- define for I2C bit-banged
+CONFIG_SYS_I2C_SPEED -- define for I2C speed
+CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
+CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
+CONFIG_SYS_IMMR -- define for MBAR offset
+
+CONFIG_SYS_MBAR -- define MBAR offset
+
+CONFIG_MONITOR_IS_IN_RAM -- Not support
+
+CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF52277 internal SRAM
+
+CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
+CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
+CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
+
+CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
+
+CONFIG_LCD and CONFIG_CMD_USB are not supported in this current u-boot,
+update will be provided at later time
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. System memory map:
+ Flash: 0x00000000-0x3FFFFFFF (1024MB)
+ DDR: 0x40000000-0x7FFFFFFF (1024MB)
+ SRAM: 0x80000000-0x8FFFFFFF (256MB)
+ IP: 0xF0000000-0xFFFFFFFF (256MB)
+
+2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and
+ linux kernel, you can customize it based on your system requirements:
+ Flash0: 0x00000000-0x00FFFFFF (16MB)
+
+ DDR: 0x40000000-0x4FFFFFFF (64MB)
+ SRAM: 0x80000000-0x80007FFF (32KB)
+ IP: 0xFC000000-0xFC0FFFFF (64KB)
+
+3. COMPILATION
+==============
+3.1 To create U-Boot the gcc-4.1-xx compiler set (ColdFire ELF or
+uClinux version) from codesourcery.com was used. Download it from:
+http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+3.2 Compilation
+ export CROSS_COMPILE=cross-compile-prefix
+ cd u-boot-1.x.x
+ make distclean
+ make M52277EVB_config
+ make
+
+4. SCREEN DUMP
+==============
+4.1 M52277EVB Development board
+ (NOTE: May not show exactly the same)
+
+U-Boot 1.3.1 (Jan 8 2008 - 12:44:08)
+
+CPU: Freescale MCF52277 (Mask:6c Version:0)
+ CPU CLK 160 Mhz BUS CLK 80 Mhz FLB CLK 80 MHZ
+ INP CLK 16 Mhz VCO CLK 480 Mhz
+Board: Freescale 52277 EVB
+I2C: ready
+DRAM: 64 MB
+FLASH: 16 MB
+In: serial
+Out: serial
+Err: serial
+-> print
+baudrate=115200
+hostname=M52277EVB
+inpclk=16000000
+loadaddr=(0x40000000 + 0x10000)
+load=tftp ${loadaddr) ${u-boot}
+upd=run load; run prog
+prog=prot off 0 3ffff;era 0 3ffff;cp.b ${loadaddr} 0 ${filesize};save
+u-boot=u-boot.bin
+stdin=serial
+stdout=serial
+stderr=serial
+mem=65024k
+
+Environment size: 280/32764 bytes
+-> bdinfo
+memstart = 0x40000000
+memsize = 0x04000000
+flashstart = 0x00000000
+flashsize = 0x01000000
+flashoffset = 0x00000000
+sramstart = 0x80000000
+sramsize = 0x00008000
+mbar = 0xFC000000
+busfreq = 80 MHz
+flbfreq = 80 Mhz
+inpfreq = 16 Mhz
+vcofreq = 480 Mhz
+
+baudrate = 115200 bps
+->
+-> help
+? - alias for 'help'
+base - print or set address offset
+bdinfo - print Board Info structure
+boot - boot default, i.e., run 'bootcmd'
+bootd - boot default, i.e., run 'bootcmd'
+bootelf - Boot from an ELF image in memory
+bootm - boot application image from memory
+bootp - boot image via network using BootP/TFTP protocol
+bootvx - Boot vxWorks from an ELF image
+cmp - memory compare
+coninfo - print console devices and information
+cp - memory copy
+crc32 - checksum calculation
+date - get/set/reset date & time
+dcache - enable or disable data cache
+echo - echo args to console
+erase - erase FLASH memory
+flinfo - print FLASH memory information
+go - start application at address 'addr'
+help - print online help
+i2c - I2C sub-system
+icache - enable or disable instruction cache
+iminfo - print header information for application image
+imls - list all images found in flash
+itest - return true/false on integer compare
+loadb - load binary file over serial line (kermit mode)
+loads - load S-Record file over serial line
+loady - load binary file over serial line (ymodem mode)
+loop - infinite loop on address range
+ls - list files in a directory (default /)
+md - memory display
+mm - memory modify (auto-incrementing)
+mtest - simple RAM test
+mw - memory write (fill)
+nm - memory modify (constant address)
+ping - send ICMP ECHO_REQUEST to network host
+printenv- print environment variables
+protect - enable or disable FLASH write protection
+reset - Perform RESET of the CPU
+run - run commands in an environment variable
+saveenv - save environment variables to persistent storage
+setenv - set environment variables
+sleep - delay execution for some time
+source - run script from memory
+version - print monitor version
+->
diff --git a/board/freescale/m5253evbe/README b/board/freescale/m5253evbe/README
new file mode 100644
index 0000000..f51609f
--- /dev/null
+++ b/board/freescale/m5253evbe/README
@@ -0,0 +1,103 @@
+Freescale Amadeus Plus M5253EVBE board
+======================================
+
+Hayden Fraser(Hayden.Fraser@freescale.com)
+Created 06/05/2007
+===========================================
+
+
+1. SWITCH SETTINGS
+==================
+1.1 N/A
+
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. For the initial bringup, we adopted a consistent memory scheme between u-boot and
+ linux kernel, you can customize it based on your system requirements:
+ SDR: 0x00000000-0x00ffffff
+ SRAM0: 0x20010000-0x20017fff
+ SRAM1: 0x20000000-0x2000ffff
+ MBAR1: 0x10000000-0x4fffffff
+ MBAR2: 0x80000000-0xCfffffff
+ Flash: 0xffe00000-0xffffffff
+
+3. DEFINITIONS AND COMPILATION
+==============================
+3.1 Explanation on NEW definitions in include/configs/M5253EVBE.h
+ CONFIG_MCF52x2 Processor family
+ CONFIG_MCF5253 MCF5253 specific
+ CONFIG_M5253EVBE Amadeus Plus board specific
+ CONFIG_SYS_CLK Define Amadeus Plus CPU Clock
+ CONFIG_SYS_MBAR MBAR base address
+ CONFIG_SYS_MBAR2 MBAR2 base address
+
+3.2 Compilation
+ export CROSS_COMPILE=/usr/local/freescale-coldfire-4.1-elf/bin/m68k-elf-
+ cd u-boot-1-2-x
+ make distclean
+ make M5253EVBE_config
+ make
+
+
+4. SCREEN DUMP
+==============
+4.1 U-Boot 1.2.0 (Jun 18 2007 - 18:20:00)
+
+CPU: Freescale Coldfire MCF5253 at 62 MHz
+Board: Freescale MCF5253 EVBE
+DRAM: 16 MB
+FLASH: 2 MB
+In: serial
+Out: serial
+Err: serial
+=> flinfo
+
+Bank # 1: CFI conformant FLASH (16 x 16) Size: 2 MB in 35 Sectors
+ AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x49
+ Erase timeout: 16384 ms, write timeout: 1 ms
+
+ Sector Start Addresses:
+ FFE00000 RO FFE04000 RO FFE06000 RO FFE08000 RO FFE10000 RO
+ FFE20000 FFE30000 FFE40000 FFE50000 FFE60000
+ FFE70000 FFE80000 FFE90000 FFEA0000 FFEB0000
+ FFEC0000 FFED0000 FFEE0000 FFEF0000 FFF00000
+ FFF10000 FFF20000 FFF30000 FFF40000 FFF50000
+ FFF60000 FFF70000 FFF80000 FFF90000 FFFA0000
+ FFFB0000 FFFC0000 FFFD0000 FFFE0000 FFFF0000
+
+=> bdinfo
+boot_params = 0x00F62F90
+memstart = 0x00000000
+memsize = 0x01000000
+flashstart = 0xFFE00000
+flashsize = 0x00200000
+flashoffset = 0x00000000
+baudrate = 19200 bps
+
+=> printenv
+bootdelay=5
+baudrate=19200
+stdin=serial
+stdout=serial
+stderr=serial
+
+Environment size: 134/8188 bytes
+=> saveenv
+Saving Environment to Flash...
+Un-Protected 1 sectors
+Erasing Flash...
+. done
+Erased 1 sectors
+Writing to Flash... done
+Protected 1 sectors
+=>
+
+5. COMPILER
+-----------
+To create U-Boot the CodeSourcery's version of the GNU Toolchain for the ColdFire architecture
+compiler set (freescale-coldfire-4.1-elf) from www.codesourcery.com was used.
+You can download it from:http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+compiler that you used - for example, codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M
+codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M
diff --git a/board/freescale/m53017evb/README b/board/freescale/m53017evb/README
new file mode 100644
index 0000000..64a3d42
--- /dev/null
+++ b/board/freescale/m53017evb/README
@@ -0,0 +1,180 @@
+Freescale MCF53017EVB ColdFire Development Board
+================================================
+
+TsiChung Liew(Tsi-Chung.Liew@freescale.com)
+Created 10/22/08
+===========================================
+
+
+Changed files:
+==============
+
+- board/freescale/m53017evb/m53017evb.c Dram setup
+- board/freescale/m53017evb/mii.c Mii access
+- board/freescale/m53017evb/Makefile Makefile
+- board/freescale/m53017evb/config.mk config make
+- board/freescale/m53017evb/u-boot.lds Linker description
+
+- arch/m68k/cpu/mcf532x/cpu.c cpu specific code
+- arch/m68k/cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
+- arch/m68k/cpu/mcf532x/interrupts.c cpu specific interrupt support
+- arch/m68k/cpu/mcf532x/speed.c system, flexbus, and cpu clock
+- arch/m68k/cpu/mcf532x/Makefile Makefile
+- arch/m68k/cpu/mcf532x/config.mk config make
+- arch/m68k/cpu/mcf532x/start.S start up assembly code
+
+- doc/README.m53017evb This readme file
+
+- drivers/net/mcffec.c ColdFire common FEC driver
+- drivers/net/mcfmii.c ColdFire common Mii driver
+- drivers/serial/mcfuart.c ColdFire common UART driver
+- drivers/rtc/mcfrtc.c Realtime clock Driver
+
+- include/asm-m68k/bitops.h Bit operation function export
+- include/asm-m68k/byteorder.h Byte order functions
+- include/asm-m68k/fec.h FEC structure and definition
+- include/asm-m68k/fsl_i2c.h I2C structure and definition
+- include/asm-m68k/global_data.h Global data structure
+- include/asm-m68k/immap.h ColdFire specific header file and driver macros
+- include/asm-m68k/immap_5301x.h mcf5301x specific header file
+- include/asm-m68k/io.h io functions
+- include/asm-m68k/m532x.h mcf5301x specific header file
+- include/asm-m68k/posix_types.h Posix
+- include/asm-m68k/processor.h header file
+- include/asm-m68k/ptrace.h Exception structure
+- include/asm-m68k/rtc.h Realtime clock header file
+- include/asm-m68k/string.h String function export
+- include/asm-m68k/timer.h Timer structure and definition
+- include/asm-m68k/types.h Data types definition
+- include/asm-m68k/uart.h Uart structure and definition
+- include/asm-m68k/u-boot.h u-boot structure
+
+- include/configs/M53017EVB.h Board specific configuration file
+
+- arch/m68k/lib/board.c board init function
+- arch/m68k/lib/cache.c
+- arch/m68k/lib/interrupts Coldfire common interrupt functions
+- arch/m68k/lib/m68k_linux.c
+- arch/m68k/lib/time.c Timer functions (Dma timer and PIT)
+- arch/m68k/lib/traps.c Exception init code
+
+1 MCF5301x specific Options/Settings
+====================================
+1.1 pre-loader is no longer suppoer in thie coldfire family
+
+1.2 Configuration settings for M53017EVB Development Board
+CONFIG_MCF5301x -- define for all MCF5301x CPUs
+CONFIG_M53015 -- define for MCF53015 CPUs
+CONFIG_M53017EVB -- define for M53017EVB board
+
+CONFIG_MCFUART -- define to use common CF Uart driver
+CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
+CONFIG_BAUDRATE -- define UART baudrate
+
+CONFIG_MCFRTC -- define to use common CF RTC driver
+CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h
+CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency
+RTC_DEBUG -- define to show RTC debug message
+CONFIG_CMD_DATE -- enable to use date feature in u-boot
+
+CONFIG_MCFFEC -- define to use common CF FEC driver
+CONFIG_MII -- enable to use MII driver
+CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c
+CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery
+CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer
+CONFIG_SYS_FAULT_ECHO_LINK_DOWN --
+CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration
+CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register
+MCFFEC_TOUT_LOOP -- set FEC timeout loop
+
+CONFIG_MCFTMR -- define to use DMA timer
+CONFIG_MCFPIT -- define to use PIT timer
+
+CONFIG_FSL_I2C -- define to use FSL common I2C driver
+CONFIG_HARD_I2C -- define for I2C hardware support
+CONFIG_SOFT_I2C -- define for I2C bit-banged
+CONFIG_SYS_I2C_SPEED -- define for I2C speed
+CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
+CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
+CONFIG_SYS_IMMR -- define for MBAR offset
+
+CONFIG_SYS_MBAR -- define MBAR offset
+
+CONFIG_MONITOR_IS_IN_RAM -- Not support
+
+CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5301x internal SRAM
+
+CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
+CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
+CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
+
+CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. System memory map:
+ Flash: 0x00000000-0x3FFFFFFF (1024MB)
+ DDR: 0x40000000-0x7FFFFFFF (1024MB)
+ SRAM: 0x80000000-0x8FFFFFFF (256MB)
+ IP: 0xFC000000-0xFFFFFFFF (256MB)
+
+2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and
+ linux kernel, you can customize it based on your system requirements:
+ Flash0: 0x00000000-0x00FFFFFF (16MB)
+ DDR: 0x40000000-0x4FFFFFFF (256MB)
+ SRAM: 0x80000000-0x80007FFF (32KB)
+ IP: 0xFC000000-0xFC0FFFFF (64KB)
+
+3. COMPILATION
+==============
+3.1 To create U-Boot the gcc-4.x-xx compiler set (ColdFire ELF or
+uClinux version) from codesourcery.com was used. Download it from:
+http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+3.2 Compilation
+ export CROSS_COMPILE=cross-compile-prefix
+ cd u-boot
+ make distclean
+ make M53017EVB_config
+ make
+
+4. SCREEN DUMP
+==============
+4.1 M53017EVB Development board
+ (NOTE: May not show exactly the same)
+
+U-Boot 2008.10 (Oct 22 2007 - 11:07:57)
+
+CPU: Freescale MCF53015 (Mask:76 Version:0)
+ CPU CLK 240 Mhz BUS CLK 80 Mhz
+Board: Freescale M53017EVB
+I2C: ready
+DRAM: 64 MB
+FLASH: 16 MB
+In: serial
+Out: serial
+Err: serial
+NAND: 16 MiB
+Net: FEC0, FEC1
+-> print
+bootdelay=1
+baudrate=115200
+ethaddr=00:e0:0c:bc:e5:60
+hostname=M53017EVB
+netdev=eth0
+loadaddr=40010000
+u-boot=u-boot.bin
+load=tftp ${loadaddr) ${u-boot}
+upd=run load; run prog
+prog=prot off 0 3ffff;era 0 3ffff;cp.b ${loadaddr} 0 ${filesize};save
+gatewayip=192.168.1.1
+netmask=255.255.255.0
+ipaddr=192.168.1.3
+serverip=192.168.1.2
+stdin=serial
+stdout=serial
+stderr=serial
+mem=65024k
+
+Environment size: 437/4092 bytes
+->
diff --git a/board/freescale/m5373evb/README b/board/freescale/m5373evb/README
new file mode 100644
index 0000000..419d4d6
--- /dev/null
+++ b/board/freescale/m5373evb/README
@@ -0,0 +1,326 @@
+Freescale MCF5373EVB ColdFire Development Board
+================================================
+
+TsiChung Liew(Tsi-Chung.Liew@freescale.com)
+Created 11/08/07
+===========================================
+
+
+Changed files:
+==============
+
+- board/freescale/m5373evb/m5373evb.c Dram setup
+- board/freescale/m5373evb/mii.c Mii access
+- board/freescale/m5373evb/Makefile Makefile
+- board/freescale/m5373evb/config.mk config make
+- board/freescale/m5373evb/u-boot.lds Linker description
+
+- arch/m68k/cpu/mcf532x/cpu.c cpu specific code
+- arch/m68k/cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
+- arch/m68k/cpu/mcf532x/interrupts.c cpu specific interrupt support
+- arch/m68k/cpu/mcf532x/speed.c system, pci, flexbus, and cpu clock
+- arch/m68k/cpu/mcf532x/Makefile Makefile
+- arch/m68k/cpu/mcf532x/config.mk config make
+- arch/m68k/cpu/mcf532x/start.S start up assembly code
+
+- doc/README.m5373evb This readme file
+
+- drivers/net/mcffec.c ColdFire common FEC driver
+- drivers/serial/mcfuart.c ColdFire common UART driver
+- drivers/rtc/mcfrtc.c Realtime clock Driver
+
+- include/asm-m68k/bitops.h Bit operation function export
+- include/asm-m68k/byteorder.h Byte order functions
+- include/asm-m68k/fec.h FEC structure and definition
+- include/asm-m68k/fsl_i2c.h I2C structure and definition
+- include/asm-m68k/global_data.h Global data structure
+- include/asm-m68k/immap.h ColdFire specific header file and driver macros
+- include/asm-m68k/immap_532x.h mcf532x specific header file
+- include/asm-m68k/io.h io functions
+- include/asm-m68k/m532x.h mcf532x specific header file
+- include/asm-m68k/posix_types.h Posix
+- include/asm-m68k/processor.h header file
+- include/asm-m68k/ptrace.h Exception structure
+- include/asm-m68k/rtc.h Realtime clock header file
+- include/asm-m68k/string.h String function export
+- include/asm-m68k/timer.h Timer structure and definition
+- include/asm-m68k/types.h Data types definition
+- include/asm-m68k/uart.h Uart structure and definition
+- include/asm-m68k/u-boot.h u-boot structure
+
+- include/configs/M5373EVB.h Board specific configuration file
+
+- arch/m68k/lib/board.c board init function
+- arch/m68k/lib/cache.c
+- arch/m68k/lib/interrupts Coldfire common interrupt functions
+- arch/m68k/lib/m68k_linux.c
+- arch/m68k/lib/time.c Timer functions (Dma timer and PIT)
+- arch/m68k/lib/traps.c Exception init code
+
+1 MCF5373 specific Options/Settings
+====================================
+1.1 pre-loader is no longer suppoer in thie coldfire family
+
+1.2 Configuration settings for M5373EVB Development Board
+CONFIG_MCF532x -- define for all MCF532x CPUs
+CONFIG_M5373 -- define for all Freescale MCF5373 CPUs
+CONFIG_M5373EVB -- define for M5373EVB board
+
+CONFIG_MCFUART -- define to use common CF Uart driver
+CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
+CONFIG_BAUDRATE -- define UART baudrate
+
+CONFIG_MCFRTC -- define to use common CF RTC driver
+CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h
+CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency
+RTC_DEBUG -- define to show RTC debug message
+CONFIG_CMD_DATE -- enable to use date feature in u-boot
+
+CONFIG_MCFFEC -- define to use common CF FEC driver
+CONFIG_MII -- enable to use MII driver
+CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c
+CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery
+CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer
+CONFIG_SYS_FAULT_ECHO_LINK_DOWN--
+CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration
+CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register
+MCFFEC_TOUT_LOOP -- set FEC timeout loop
+
+CONFIG_MCFTMR -- define to use DMA timer
+CONFIG_MCFPIT -- define to use PIT timer
+
+CONFIG_FSL_I2C -- define to use FSL common I2C driver
+CONFIG_HARD_I2C -- define for I2C hardware support
+CONFIG_SOFT_I2C -- define for I2C bit-banged
+CONFIG_SYS_I2C_SPEED -- define for I2C speed
+CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
+CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
+CONFIG_SYS_IMMR -- define for MBAR offset
+
+CONFIG_SYS_MBAR -- define MBAR offset
+
+CONFIG_MONITOR_IS_IN_RAM -- Not support
+
+CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5373 internal SRAM
+
+CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
+CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
+CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
+
+CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. System memory map:
+ Flash: 0x00000000-0x3FFFFFFF (1024MB)
+ DDR: 0x40000000-0x7FFFFFFF (1024MB)
+ SRAM: 0x80000000-0x8FFFFFFF (256MB)
+ IP: 0xF0000000-0xFFFFFFFF (256MB)
+
+2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and
+ linux kernel, you can customize it based on your system requirements:
+ Flash0: 0x00000000-0x00FFFFFF (16MB)
+
+ DDR: 0x40000000-0x4FFFFFFF (256MB)
+ SRAM: 0x80000000-0x80007FFF (32KB)
+ IP: 0xFC000000-0xFC0FFFFF (64KB)
+
+3. COMPILATION
+==============
+3.1 To create U-Boot the gcc-4.1-xx compiler set (ColdFire ELF or
+uClinux version) from codesourcery.com was used. Download it from:
+http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+3.2 Compilation
+ export CROSS_COMPILE=cross-compile-prefix
+ cd u-boot-1.x.x
+ make distclean
+ make M5373EVB_config
+ make
+
+4. SCREEN DUMP
+==============
+4.1 M5373EVB Development board
+ (NOTE: May not show exactly the same)
+
+U-Boot 1.3.0 (Nov 8 2007 - 12:44:08)
+
+CPU: Freescale MCF5373 (Mask:65 Version:1)
+ CPU CLK 240 Mhz BUS CLK 80 Mhz
+Board: Freescale FireEngine 5373 EVB
+I2C: ready
+DRAM: 32 MB
+FLASH: 2 MB
+In: serial
+Out: serial
+Err: serial
+NAND: 16 MiB
+Net: FEC0
+-> print
+bootdelay=1
+baudrate=115200
+ethaddr=00:e0:0c:bc:e5:60
+hostname=M5373EVB
+netdev=eth0
+loadaddr=40010000
+load=tftp ${loadaddr) ${u-boot}
+upd=run load; run prog
+prog=prot off 0 2ffff;era 0 2ffff;cp.b ${loadaddr} 0 ${filesize};save
+ethact=FEC0
+u-boot=u-boot.bin
+gatewayip=192.168.1.1
+netmask=255.255.255.0
+ipaddr=192.168.1.3
+serverip=192.168.1.2
+stdin=serial
+stdout=serial
+stderr=serial
+mem=261632k
+
+Environment size: 401/8188 bytes
+-> bdinfo
+memstart = 0x40000000
+memsize = 0x02000000
+flashstart = 0x00000000
+flashsize = 0x00200000
+flashoffset = 0x00000000
+sramstart = 0x80000000
+sramsize = 0x00008000
+mbar = 0xFC000000
+busfreq = 80 MHz
+ethaddr = 00:E0:0C:BC:E5:60
+ip_addr = 192.168.1.3
+baudrate = 115200 bps
+->
+-> help
+? - alias for 'help'
+base - print or set address offset
+bdinfo - print Board Info structure
+boot - boot default, i.e., run 'bootcmd'
+bootd - boot default, i.e., run 'bootcmd'
+bootelf - Boot from an ELF image in memory
+bootm - boot application image from memory
+bootp - boot image via network using BootP/TFTP protocol
+bootvx - Boot vxWorks from an ELF image
+cmp - memory compare
+coninfo - print console devices and information
+cp - memory copy
+crc32 - checksum calculation
+date - get/set/reset date & time
+dcache - enable or disable data cache
+echo - echo args to console
+erase - erase FLASH memory
+flinfo - print FLASH memory information
+go - start application at address 'addr'
+help - print online help
+i2c - I2C sub-system
+icache - enable or disable instruction cache
+iminfo - print header information for application image
+imls - list all images found in flash
+itest - return true/false on integer compare
+loadb - load binary file over serial line (kermit mode)
+loads - load S-Record file over serial line
+loady - load binary file over serial line (ymodem mode)
+loop - infinite loop on address range
+ls - list files in a directory (default /)
+md - memory display
+mii - MII utility commands
+mm - memory modify (auto-incrementing)
+mtest - simple RAM test
+mw - memory write (fill)
+nand - NAND sub-system
+nboot - boot from NAND device
+nfs - boot image via network using NFS protocol
+nm - memory modify (constant address)
+ping - send ICMP ECHO_REQUEST to network host
+printenv- print environment variables
+protect - enable or disable FLASH write protection
+rarpboot- boot image via network using RARP/TFTP protocol
+reset - Perform RESET of the CPU
+run - run commands in an environment variable
+saveenv - save environment variables to persistent storage
+setenv - set environment variables
+sleep - delay execution for some time
+source - run script from memory
+tftpboot- boot image via network using TFTP protocol
+version - print monitor version
+-> tftp 0x40800000 uImage
+Using FEC0 device
+TFTP from server 192.168.1.3; our IP address is 192.168.1.3 Filename 'uImage'.
+Load address: 0x40800000
+Loading: #################################################################
+ #################################################################
+ ##########
+done
+Bytes transferred = 2053270 (1f5496 hex)
+-> bootm 0x40800000
+## Booting image at 40800000 ...
+ Image Name: Linux Kernel Image
+ Created: 2007-11-07 20:33:08 UTC
+ Image Type: M68K Linux Kernel Image (gzip compressed)
+ Data Size: 2053206 Bytes = 2 MB
+ Load Address: 40020000
+ Entry Point: 40020000
+ Verifying Checksum ... OK
+ Uncompressing Kernel Image ... OK
+Linux version 2.6.22-uc1 (mattw@loa) (gcc version 4.2.1 (Sourcery G++ Lite 4.2-7
+
+
+uClinux/COLDFIRE(m537x)
+COLDFIRE port done by Greg Ungerer, gerg@snapgear.com Flat model support (C) 1998,1999 Kenneth Albanowski, D. Jeff Dionne Built 1 zonelists. Total pages: 8128 Kernel command line: rootfstype=romfs PID hash table entries: 128 (order: 7, 512 bytes) Dentry cache hash table entries: 4096 (order: 2, 16384 bytes) Inode-cache hash table entries: 2048 (order: 1, 8192 bytes) Memory available: 28092k/32768k RAM, (1788k kernel code, 244k data) Mount-cache hash table entries: 512
+NET: Registered protocol family 16
+USB-MCF537x: (HOST module) EHCI device is registered
+USB-MCF537x: (OTG module) EHCI device is registered
+USB-MCF537x: (OTG module) UDC device is registered
+usbcore: registered new interface driver usbfs
+usbcore: registered new interface driver hub
+usbcore: registered new device driver usb
+NET: Registered protocol family 2
+IP route cache hash table entries: 1024 (order: 0, 4096 bytes) TCP established hash table entries: 1024 (order: 1, 8192 bytes) TCP bind hash table entries: 1024 (order: 0, 4096 bytes)
+TCP: Hash tables configured (established 1024 bind 1024) TCP reno registered
+JFFS2 version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
+io scheduler noop registered
+io scheduler cfq registered (default)
+ColdFire internal UART serial driver version 1.00 ttyS0 at 0xfc060000 (irq = 90) is a builtin ColdFire UART
+ttyS1 at 0xfc064000 (irq = 91) is a builtin ColdFire UART
+ttyS2 at 0xfc068000 (irq = 92) is a builtin ColdFire UART RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
+loop: module loaded
+nbd: registered device at major 43
+usbcore: registered new interface driver ub FEC ENET Version 0.2
+fec: PHY @ 0x1, ID 0x20005c90 -- DP83848
+eth0: ethernet 00:e0:0c:bc:e5:60
+uclinux[mtd]: RAM probe address=0x4021c22c size=0x22b000 Creating 1 MTD partitions on "RAM":
+0x00000000-0x0022b000 : "ROMfs"
+uclinux[mtd]: set ROMfs to be root filesystem NAND device: Manufacturer ID: 0x20, Chip ID: 0x73 (ST Micro NAND 16MiB 3,3V 8-b) Scanning device for bad blocks Creating 1 MTD partitions on "NAND 16MiB 3,3V 8-bit":
+0x00000000-0x01000000 : "M53xx flash partition 1"
+QSPI: spi->max_speed_hz 300000
+QSPI: Baud set to 255
+SPI: Coldfire master initialized
+M537x - Disable UART1 when using Audio
+udc: Freescale MCF53xx UDC driver version 27 October 2006 init
+udc: MCF53xx USB Device is found. ID=0x5 Rev=0x41 i2c /dev entries driver
+usbcore: registered new interface driver usbhid
+drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver TCP cubic registered
+NET: Registered protocol family 1
+NET: Registered protocol family 17
+VFS: Mounted root (romfs filesystem) readonly.
+Freeing unused kernel memory: 64k freed (0x401f5000 - 0x40204000) init started: BusyBox v1.00 (2007.11.07-19:57+0000) multi-call binary?Setting e Mounting filesystems
+mount: Mounting devpts on /dev/pts failed: No such device
+mount: Mounting usbfs on /proc/bus/usb failed: No such file or directory Starting syslogd and klogd Setting up networking on loopback device:
+Setting up networking on eth0:
+info, udhcpc (v0.9.9-pre) started
+eth0: config: auto-negotiation on, 100FDX, 100HDX, 10FDX, 10HDX.
+debug, Sending discover...
+debug, Sending discover...
+debug, Sending select for 172.27.0.130...
+info, Lease of 172.27.0.130 obtained, lease time 43200 deleting routers
+route: SIOC[ADD|DEL]RT: No such process
+adding dns 172.27.0.1
+Starting the boa webserver:
+Setting time from ntp server: ntp.cs.strath.ac.uk
+ntp.cs.strath.ac.uk: Unknown host
+
+
+BusyBox v1.00 (2007.11.07-19:57+0000) Built-in shell (msh) Enter 'help' for a list of built-in commands.
+
+#
diff --git a/board/freescale/m54455evb/README b/board/freescale/m54455evb/README
new file mode 100644
index 0000000..2bc6ce4
--- /dev/null
+++ b/board/freescale/m54455evb/README
@@ -0,0 +1,409 @@
+Freescale MCF54455EVB ColdFire Development Board
+================================================
+
+TsiChung Liew(Tsi-Chung.Liew@freescale.com)
+Created 4/08/07
+===========================================
+
+
+Changed files:
+==============
+
+- board/freescale/m54455evb/m54455evb.c Dram setup, IDE pre init, and PCI init
+- board/freescale/m54455evb/flash.c Atmel and INTEL flash support
+- board/freescale/m54455evb/Makefile Makefile
+- board/freescale/m54455evb/config.mk config make
+- board/freescale/m54455evb/u-boot.lds Linker description
+
+- common/cmd_bdinfo.c Clock frequencies output
+- common/cmd_mii.c mii support
+
+- arch/m68k/cpu/mcf5445x/cpu.c cpu specific code
+- arch/m68k/cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
+- arch/m68k/cpu/mcf5445x/interrupts.c cpu specific interrupt support
+- arch/m68k/cpu/mcf5445x/speed.c system, pci, flexbus, and cpu clock
+- arch/m68k/cpu/mcf5445x/Makefile Makefile
+- arch/m68k/cpu/mcf5445x/config.mk config make
+- arch/m68k/cpu/mcf5445x/start.S start up assembly code
+
+- doc/README.m54455evb This readme file
+
+- drivers/net/mcffec.c ColdFire common FEC driver
+- drivers/serial/mcfuart.c ColdFire common UART driver
+
+- include/asm-m68k/bitops.h Bit operation function export
+- include/asm-m68k/byteorder.h Byte order functions
+- include/asm-m68k/fec.h FEC structure and definition
+- include/asm-m68k/fsl_i2c.h I2C structure and definition
+- include/asm-m68k/global_data.h Global data structure
+- include/asm-m68k/immap.h ColdFire specific header file and driver macros
+- include/asm-m68k/immap_5445x.h mcf5445x specific header file
+- include/asm-m68k/io.h io functions
+- include/asm-m68k/m5445x.h mcf5445x specific header file
+- include/asm-m68k/posix_types.h Posix
+- include/asm-m68k/processor.h header file
+- include/asm-m68k/ptrace.h Exception structure
+- include/asm-m68k/rtc.h Realtime clock header file
+- include/asm-m68k/string.h String function export
+- include/asm-m68k/timer.h Timer structure and definition
+- include/asm-m68k/types.h Data types definition
+- include/asm-m68k/uart.h Uart structure and definition
+- include/asm-m68k/u-boot.h u-boot structure
+
+- include/configs/M54455EVB.h Board specific configuration file
+
+- arch/m68k/lib/board.c board init function
+- arch/m68k/lib/cache.c
+- arch/m68k/lib/interrupts Coldfire common interrupt functions
+- arch/m68k/lib/m68k_linux.c
+- arch/m68k/lib/time.c Timer functions (Dma timer and PIT)
+- arch/m68k/lib/traps.c Exception init code
+
+- rtc/mcfrtc.c Realtime clock Driver
+
+1 MCF5445x specific Options/Settings
+====================================
+1.1 pre-loader is no longer suppoer in thie coldfire family
+
+1.2 Configuration settings for M54455EVB Development Board
+CONFIG_MCF5445x -- define for all MCF5445x CPUs
+CONFIG_M54455 -- define for all Freescale MCF54455 CPUs
+CONFIG_M54455EVB -- define for M54455EVB board
+
+CONFIG_MCFUART -- define to use common CF Uart driver
+CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
+CONFIG_BAUDRATE -- define UART baudrate
+
+CONFIG_MCFRTC -- define to use common CF RTC driver
+CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h
+CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency
+RTC_DEBUG -- define to show RTC debug message
+CONFIG_CMD_DATE -- enable to use date feature in u-boot
+
+CONFIG_MCFFEC -- define to use common CF FEC driver
+CONFIG_MII -- enable to use MII driver
+CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c
+CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery
+CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer
+CONFIG_SYS_FAULT_ECHO_LINK_DOWN--
+CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration
+CONFIG_SYS_FEC1_PINMUX -- Set FEC1 Pin configuration
+CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register
+CONFIG_SYS_FEC1_MIIBASE -- Set FEC0 MII base register
+MCFFEC_TOUT_LOOP -- set FEC timeout loop
+CONFIG_HAS_ETH1 -- define to enable second FEC in u-boot
+
+CONFIG_ISO_PARTITION -- enable ISO read/write
+CONFIG_DOS_PARTITION -- enable DOS read/write
+CONFIG_IDE_RESET -- define ide_reset()
+CONFIG_IDE_PREINIT -- define ide_preinit()
+CONFIG_ATAPI -- define ATAPI support
+CONFIG_LBA48 -- define LBA48 (larger than 120GB) support
+CONFIG_SYS_IDE_MAXBUS -- define max channel
+CONFIG_SYS_IDE_MAXDEVICE -- define max devices per channel
+CONFIG_SYS_ATA_BASE_ADDR -- define ATA base address
+CONFIG_SYS_ATA_IDE0_OFFSET -- define ATA IDE0 offset
+CONFIG_SYS_ATA_DATA_OFFSET -- define ATA data IO
+CONFIG_SYS_ATA_REG_OFFSET -- define for normal register accesses
+CONFIG_SYS_ATA_ALT_OFFSET -- define for alternate registers
+CONFIG_SYS_ATA_STRIDE -- define for Interval between registers
+_IO_BASE -- define for IO base address
+
+CONFIG_MCFTMR -- define to use DMA timer
+CONFIG_MCFPIT -- define to use PIT timer
+
+CONFIG_FSL_I2C -- define to use FSL common I2C driver
+CONFIG_HARD_I2C -- define for I2C hardware support
+CONFIG_SOFT_I2C -- define for I2C bit-banged
+CONFIG_SYS_I2C_SPEED -- define for I2C speed
+CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
+CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
+CONFIG_SYS_IMMR -- define for MBAR offset
+
+CONFIG_PCI -- define for PCI support
+CONFIG_PCI_PNP -- define for Plug n play support
+CONFIG_SYS_PCI_MEM_BUS -- PCI memory logical offset
+CONFIG_SYS_PCI_MEM_PHYS -- PCI memory physical offset
+CONFIG_SYS_PCI_MEM_SIZE -- PCI memory size
+CONFIG_SYS_PCI_IO_BUS -- PCI IO logical offset
+CONFIG_SYS_PCI_IO_PHYS -- PCI IO physical offset
+CONFIG_SYS_PCI_IO_SIZE -- PCI IO size
+CONFIG_SYS_PCI_CFG_BUS -- PCI Configuration logical offset
+CONFIG_SYS_PCI_CFG_PHYS -- PCI Configuration physical offset
+CONFIG_SYS_PCI_CFG_SIZE -- PCI Configuration size
+
+CONFIG_EXTRA_CLOCK -- Enable extra clock such as vco, flexbus, pci, etc
+
+CONFIG_SYS_MBAR -- define MBAR offset
+
+CONFIG_SYS_ATMEL_BOOT -- To determine the u-boot is booted from Atmel or Intel
+
+CONFIG_MONITOR_IS_IN_RAM -- Not support
+
+CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF54455 internal SRAM
+
+CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
+CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
+CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
+
+CONFIG_SYS_ATMEL_BASE -- defines the Atmel Flash base
+CONFIG_SYS_INTEL_BASE -- defines the Intel Flash base
+
+CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
+CONFIG_SYS_SDRAM_BASE1 -- defines the DRAM Base 1
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. System memory map:
+ Flash: 0x00000000-0x3FFFFFFF (1024MB)
+ DDR: 0x40000000-0x7FFFFFFF (1024MB)
+ SRAM: 0x80000000-0x8FFFFFFF (256MB)
+ ATA: 0x90000000-0x9FFFFFFF (256MB)
+ PCI: 0xA0000000-0xBFFFFFFF (512MB)
+ FlexBus: 0xC0000000-0xDFFFFFFF (512MB)
+ IP: 0xF0000000-0xFFFFFFFF (256MB)
+
+2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and
+ linux kernel, you can customize it based on your system requirements:
+ Atmel boot:
+ Flash0: 0x00000000-0x0007FFFF (512KB)
+ Flash1: 0x04000000-0x05FFFFFF (32MB)
+ Intel boot:
+ Flash0: 0x00000000-0x01FFFFFF (32MB)
+ Flash1: 0x04000000-0x0407FFFF (512KB)
+
+ CPLD: 0x08000000-0x08FFFFFF (16MB)
+ FPGA: 0x09000000-0x09FFFFFF (16MB)
+ DDR: 0x40000000-0x4FFFFFFF (256MB)
+ SRAM: 0x80000000-0x80007FFF (32KB)
+ IP: 0xFC000000-0xFC0FFFFF (64KB)
+
+3. SWITCH SETTINGS
+==================
+3.1 SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL
+ SW1 Pin4: 0 - ULPI chip not in reset state or 1 - ULPI chip in reset state
+ SW1 Pin5: 0 - Full ATA Bus enabled, FEC Phy1 powered down
+ 1 - Upper 8 bits ATA data bus disabled, FEC PHY1 active
+ SW1 Pin6: 0 - FEC Phy0 active or 1 - FEC Phy0 powered down
+ SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL
+
+4. COMPILATION
+==============
+4.1 To create U-Boot the gcc-4.1-32 compiler set (ColdFire ELF version)
+from codesourcery.com was used. Download it from:
+http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+4.2 Compilation
+ export CROSS_COMPILE=cross-compile-prefix
+ cd u-boot-1.x.x
+ make distclean
+ make M54455EVB_config, or - default to atmel 33Mhz input clock
+ make M54455EVB_atmel_config, or - default to atmel 33Mhz input clock
+ make M54455EVB_a33_config, or - default to atmel 33Mhz input clock
+ make M54455EVB_a66_config, or - default to atmel 66Mhz input clock
+ make M54455EVB_intel_config, or - default to intel 33Mhz input clock
+ make M54455EVB_i33_config, or - default to intel 33Mhz input clock
+ make M54455EVB_i66_config, or - default to intel 66Mhz input clock
+ make
+
+5. SCREEN DUMP
+==============
+5.1 M54455EVB Development board
+ Boot from Atmel (NOTE: May not show exactly the same)
+
+U-Boot 1.2.0-g98c80b46-dirty (Jul 26 2007 - 12:44:08)
+
+CPU: Freescale MCF54455 (Mask:48 Version:1)
+ CPU CLK 266 Mhz BUS CLK 133 Mhz FLB CLK 66 Mhz
+ PCI CLK 33 Mhz INP CLK 33 Mhz VCO CLK 533 Mhz
+Board: Freescale M54455 EVB
+I2C: ready
+DRAM: 256 MB
+FLASH: 16.5 MB
+In: serial
+Out: serial
+Err: serial
+Net: FEC0, FEC1
+IDE: Bus 0: not available
+-> print
+bootargs=root=/dev/ram rw
+bootdelay=1
+baudrate=115200
+ethaddr=00:e0:0c:bc:e5:60
+eth1addr=00:e0:0c:bc:e5:61
+hostname=M54455EVB
+netdev=eth0
+inpclk=33333333
+loadaddr=40010000
+load=tftp ${loadaddr) ${u-boot}
+upd=run load; run prog
+prog=prot off 0 2ffff;era 0 2ffff;cp.b ${loadaddr} 0 ${filesize};save
+ethact=FEC0
+mtdids=nor0=M54455EVB-1
+mtdparts=M54455EVB-1:16m(user)
+u-boot=u-boot54455.bin
+filesize=292b4
+fileaddr=40010000
+gatewayip=192.168.1.1
+netmask=255.255.255.0
+ipaddr=192.168.1.3
+serverip=192.168.1.2
+stdin=serial
+stdout=serial
+stderr=serial
+mem=261632k
+
+Environment size: 563/8188 bytes
+-> bdinfo
+memstart = 0x40000000
+memsize = 0x10000000
+flashstart = 0x00000000
+flashsize = 0x01080000
+flashoffset = 0x00000000
+sramstart = 0x80000000
+sramsize = 0x00008000
+mbar = 0xFC000000
+busfreq = 133.333 MHz
+pcifreq = 33.333 MHz
+flbfreq = 66.666 MHz
+inpfreq = 33.333 MHz
+vcofreq = 533.333 MHz
+ethaddr = 00:E0:0C:BC:E5:60
+eth1addr = 00:E0:0C:BC:E5:61
+ip_addr = 192.168.1.3
+baudrate = 115200 bps
+->
+-> help
+? - alias for 'help'
+base - print or set address offset
+bdinfo - print Board Info structure
+boot - boot default, i.e., run 'bootcmd'
+bootd - boot default, i.e., run 'bootcmd'
+bootelf - Boot from an ELF image in memory
+bootm - boot application image from memory
+bootp - boot image via network using BootP/TFTP protocol
+bootvx - Boot vxWorks from an ELF image
+cmp - memory compare
+coninfo - print console devices and information
+cp - memory copy
+crc32 - checksum calculation
+date - get/set/reset date & time
+dcache - enable or disable data cache
+diskboot- boot from IDE device
+echo - echo args to console
+erase - erase FLASH memory
+ext2load- load binary file from a Ext2 filesystem
+ext2ls - list files in a directory (default /)
+fatinfo - print information about filesystem
+fatload - load binary file from a dos filesystem
+fatls - list files in a directory (default /)
+flinfo - print FLASH memory information
+fsinfo - print information about filesystems
+fsload - load binary file from a filesystem image
+go - start application at address 'addr'
+help - print online help
+i2c - I2C sub-system
+icache - enable or disable instruction cache
+ide - IDE sub-system
+iminfo - print header information for application image
+imls - list all images found in flash
+itest - return true/false on integer compare
+loadb - load binary file over serial line (kermit mode)
+loads - load S-Record file over serial line
+loady - load binary file over serial line (ymodem mode)
+loop - infinite loop on address range
+ls - list files in a directory (default /)
+md - memory display
+mii - MII utility commands
+mm - memory modify (auto-incrementing)
+mtest - simple RAM test
+mw - memory write (fill)
+nfs - boot image via network using NFS protocol
+nm - memory modify (constant address)
+pci - list and access PCI Configuration Space
+ping - send ICMP ECHO_REQUEST to network host
+printenv- print environment variables
+protect - enable or disable FLASH write protection
+rarpboot- boot image via network using RARP/TFTP protocol
+reset - Perform RESET of the CPU
+run - run commands in an environment variable
+saveenv - save environment variables to persistent storage
+setenv - set environment variables
+sleep - delay execution for some time
+source - run script from memory
+tftpboot- boot image via network using TFTP protocol
+version - print monitor version
+->bootm 4000000
+
+## Booting image at 04000000 ...
+ Image Name: Linux Kernel Image
+ Created: 2007-08-14 15:13:00 UTC
+ Image Type: M68K Linux Kernel Image (uncompressed)
+ Data Size: 2301952 Bytes = 2.2 MB
+ Load Address: 40020000
+ Entry Point: 40020000
+ Verifying Checksum ... OK
+OK
+Linux version 2.6.20-gfe5136d6-dirty (mattw@kea) (gcc version 4.2.0 20070318 (pr
+erelease) (Sourcery G++ Lite 4.2-20)) #108 Mon Aug 13 13:00:13 MDT 2007
+starting up linux startmem 0xc0254000, endmem 0xcfffffff, size 253MB
+Built 1 zonelists. Total pages: 32624
+Kernel command line: root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=ph
+ysmap-flash.0:5M(kernel)ro,-(jffs2)
+PID hash table entries: 1024 (order: 10, 4096 bytes)
+Console: colour dummy device 80x25
+Dentry cache hash table entries: 32768 (order: 4, 131072 bytes)
+Inode-cache hash table entries: 16384 (order: 3, 65536 bytes)
+Memory: 257496k/262136k available (1864k kernel code, 2440k data, 88k init)
+Mount-cache hash table entries: 1024
+NET: Registered protocol family 16
+SCSI subsystem initialized
+NET: Registered protocol family 2
+IP route cache hash table entries: 2048 (order: 0, 8192 bytes)
+TCP established hash table entries: 8192 (order: 2, 32768 bytes)
+TCP bind hash table entries: 4096 (order: 1, 16384 bytes)
+TCP: Hash tables configured (established 8192 bind 4096)
+TCP reno registered
+JFFS2 version 2.2. (NAND) (C) 2001-2006 Red Hat, Inc.
+io scheduler noop registered
+io scheduler anticipatory registered
+io scheduler deadline registered
+io scheduler cfq registered (default)
+ColdFire internal UART serial driver version 1.00
+ttyS0 at 0xfc060000 (irq = 90) is a builtin ColdFire UART
+ttyS1 at 0xfc064000 (irq = 91) is a builtin ColdFire UART
+ttyS2 at 0xfc068000 (irq = 92) is a builtin ColdFire UART
+RAMDISK driver initialized: 16 RAM disks of 64000K size 1024 blocksize
+loop: loaded (max 8 devices)
+FEC ENET Version 0.2
+fec: PHY @ 0x0, ID 0x20005ca2 -- DP83849
+eth0: ethernet 00:08:ee:00:e4:19
+physmap platform flash device: 01000000 at 04000000
+physmap-flash.0: Found 1 x16 devices at 0x0 in 8-bit bank
+ Intel/Sharp Extended Query Table at 0x0031
+Using buffer write method
+cfi_cmdset_0001: Erase suspend on write enabled
+2 cmdlinepart partitions found on MTD device physmap-flash.0
+Creating 2 MTD partitions on "physmap-flash.0":
+0x00000000-0x00500000 : "kernel"
+mtd: Giving out device 0 to kernel
+0x00500000-0x01000000 : "jffs2"
+mtd: Giving out device 1 to jffs2
+mice: PS/2 mouse device common for all mice
+i2c /dev entries driver
+TCP cubic registered
+NET: Registered protocol family 1
+NET: Registered protocol family 17
+NET: Registered protocol family 15
+VFS: Mounted root (jffs2 filesystem).
+Setting the hostname to freescale
+Mounting filesystems
+mount: Mounting usbfs on /proc/bus/usb failed: No such file or directory
+Starting syslogd and klogd
+Setting up networking on loopback device:
+Setting up networking on eth0:
+eth0: config: auto-negotiation on, 100FDX, 100HDX, 10FDX, 10HDX.
+Adding static route for default gateway to 172.27.255.254:
+Setting nameserver to 172.27.0.1 in /etc/resolv.conf:
+Starting inetd:
+/ #
diff --git a/board/freescale/m547xevb/README b/board/freescale/m547xevb/README
new file mode 100644
index 0000000..d3aec20
--- /dev/null
+++ b/board/freescale/m547xevb/README
@@ -0,0 +1,272 @@
+Freescale MCF5475EVB ColdFire Development Board
+================================================
+
+TsiChung Liew(Tsi-Chung.Liew@freescale.com)
+Created Jan 08, 2008
+===========================================
+
+
+Changed files:
+==============
+
+- board/freescale/m547xevb/m547xevb.c Dram setup, IDE pre init, and PCI init
+- board/freescale/m547xevb/mii.c MII init
+- board/freescale/m547xevb/Makefile Makefile
+- board/freescale/m547xevb/config.mk config make
+- board/freescale/m547xevb/u-boot.lds Linker description
+
+- arch/m68k/cpu/mcf547x_8x/cpu.c cpu specific code
+- arch/m68k/cpu/mcf547x_8x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
+- arch/m68k/cpu/mcf547x_8x/interrupts.c cpu specific interrupt support
+- arch/m68k/cpu/mcf547x_8x/slicetimer.c Timer support
+- arch/m68k/cpu/mcf547x_8x/speed.c system, pci, flexbus, and cpu clock
+- arch/m68k/cpu/mcf547x_8x/Makefile Makefile
+- arch/m68k/cpu/mcf547x_8x/config.mk config make
+- arch/m68k/cpu/mcf547x_8x/start.S start up assembly code
+
+- doc/README.m5475evb This readme file
+
+- drivers/dma/MCD_dmaApi.c DMA API functions
+- drivers/dma/MCD_tasks.c DMA Tasks
+- drivers/dma/MCD_tasksInit.c DMA Tasks Init
+- drivers/net/fsl_mcdmafec.c ColdFire common DMA FEC driver
+- drivers/serial/mcfuart.c ColdFire common UART driver
+
+- include/MCD_dma.h DMA header file
+- include/MCD_progCheck.h DMA header file
+- include/MCD_tasksInit.h DMA header file
+- include/asm-m68k/bitops.h Bit operation function export
+- include/asm-m68k/byteorder.h Byte order functions
+- include/asm-m68k/errno.h Error Number definition
+- include/asm-m68k/fec.h FEC structure and definition
+- include/asm-m68k/fsl_i2c.h I2C structure and definition
+- include/asm-m68k/fsl_mcddmafec.h DMA FEC structure and definition
+- include/asm-m68k/global_data.h Global data structure
+- include/asm-m68k/immap.h ColdFire specific header file and driver macros
+- include/asm-m68k/immap_547x_8x.h mcf547x_8x specific header file
+- include/asm-m68k/io.h io functions
+- include/asm-m68k/m547x_8x.h mcf547x_8x specific header file
+- include/asm-m68k/posix_types.h Posix
+- include/asm-m68k/processor.h header file
+- include/asm-m68k/ptrace.h Exception structure
+- include/asm-m68k/rtc.h Realtime clock header file
+- include/asm-m68k/string.h String function export
+- include/asm-m68k/timer.h Timer structure and definition
+- include/asm-m68k/types.h Data types definition
+- include/asm-m68k/uart.h Uart structure and definition
+- include/asm-m68k/u-boot.h u-boot structure
+
+- include/configs/M5475EVB.h Board specific configuration file
+
+- arch/m68k/lib/board.c board init function
+- arch/m68k/lib/cache.c
+- arch/m68k/lib/interrupts Coldfire common interrupt functions
+- arch/m68k/lib/m68k_linux.c
+- arch/m68k/lib/traps.c Exception init code
+
+1 MCF547x specific Options/Settings
+====================================
+1.1 pre-loader is no longer suppoer in thie coldfire family
+
+1.2 Configuration settings for M5475EVB Development Board
+CONFIG_MCF547x_8x -- define for all MCF547x_8x CPUs
+CONFIG_M547x -- define for all Freescale MCF547x CPUs
+CONFIG_M5475 -- define for M5475EVB board
+
+CONFIG_MCFUART -- define to use common CF Uart driver
+CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
+CONFIG_BAUDRATE -- define UART baudrate
+
+CONFIG_FSLDMAFEC -- define to use common dma FEC driver
+CONFIG_MII -- enable to use MII driver
+CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c
+CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery
+CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer
+CONFIG_SYS_FAULT_ECHO_LINK_DOWN--
+CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration
+CONFIG_SYS_FEC1_PINMUX -- Set FEC1 Pin configuration
+CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register
+CONFIG_SYS_FEC1_MIIBASE -- Set FEC0 MII base register
+MCFFEC_TOUT_LOOP -- set FEC timeout loop
+CONFIG_HAS_ETH1 -- define to enable second FEC in u-boot
+
+CONFIG_CMD_USB -- enable USB commands
+CONFIG_USB_OHCI_NEW -- enable USB OHCI driver
+CONFIG_USB_STORAGE -- enable USB Storage device
+CONFIG_DOS_PARTITION -- enable DOS read/write
+
+CONFIG_SLTTMR -- define to use SLT timer
+
+CONFIG_FSL_I2C -- define to use FSL common I2C driver
+CONFIG_HARD_I2C -- define for I2C hardware support
+CONFIG_SOFT_I2C -- define for I2C bit-banged
+CONFIG_SYS_I2C_SPEED -- define for I2C speed
+CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
+CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
+CONFIG_SYS_IMMR -- define for MBAR offset
+
+CONFIG_PCI -- define for PCI support
+CONFIG_PCI_PNP -- define for Plug n play support
+CONFIG_SKIPPCI_HOSTBRIDGE -- SKIP PCI Host bridge
+CONFIG_SYS_PCI_MEM_BUS -- PCI memory logical offset
+CONFIG_SYS_PCI_MEM_PHYS -- PCI memory physical offset
+CONFIG_SYS_PCI_MEM_SIZE -- PCI memory size
+CONFIG_SYS_PCI_IO_BUS -- PCI IO logical offset
+CONFIG_SYS_PCI_IO_PHYS -- PCI IO physical offset
+CONFIG_SYS_PCI_IO_SIZE -- PCI IO size
+CONFIG_SYS_PCI_CFG_BUS -- PCI Configuration logical offset
+CONFIG_SYS_PCI_CFG_PHYS -- PCI Configuration physical offset
+CONFIG_SYS_PCI_CFG_SIZE -- PCI Configuration size
+
+CONFIG_SYS_MBAR -- define MBAR offset
+
+CONFIG_MONITOR_IS_IN_RAM -- Not support
+
+CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF547x internal SRAM
+
+CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
+CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
+CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
+
+CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. System memory map:
+ Flash: 0xFF800000-0xFFFFFFFF (8MB)
+ DDR: 0x00000000-0x3FFFFFFF (1024MB)
+ SRAM: 0xF2000000-0xF2000FFF (4KB)
+ PCI: 0x70000000-0x8FFFFFFF (512MB)
+ IP: 0xF0000000-0xFFFFFFFF (256MB)
+
+3. COMPILATION
+==============
+3.1 To create U-Boot the gcc-4.x compiler set (ColdFire ELF or uclinux
+ version) from codesourcery.com was used. Download it from:
+ http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+3.2 Compilation
+ export CROSS_COMPILE=cross-compile-prefix
+ cd u-boot-1.x.x
+ make distclean
+ make M5475AFE_config, or - boot 2MB, RAM 64MB
+ make M5475BFE_config, or - boot 2MB, code 16MB, RAM 64MB
+ make M5475CFE_config, or - boot 2MB, code 16MB, Video, USB, RAM 64MB
+ make M5475DFE_config, or - boot 2MB, USB, RAM 64MB
+ make M5475EFE_config, or - boot 2MB, Video, USB, RAM 64MB
+ make M5475FFE_config, or - boot 2MB, code 32MB, Video, USB, RAM 128MB
+ make M5475GFE_config, or - boot 2MB, RAM 64MB
+ make
+
+5. SCREEN DUMP
+==============
+5.1
+
+U-Boot 1.3.1 (Jan 8 2008 - 12:47:44)
+
+CPU: Freescale MCF5475
+ CPU CLK 266 Mhz BUS CLK 133 Mhz
+Board: Freescale FireEngine 5475 EVB
+I2C: ready
+DRAM: 64 MB
+FLASH: 18 MB
+In: serial
+Out: serial
+Err: serial
+Net: FEC0, FEC1
+-> pri
+bootdelay=1
+baudrate=115200
+ethaddr=00:e0:0c:bc:e5:60
+eth1addr=00:e0:0c:bc:e5:61
+ipaddr=192.162.1.2
+serverip=192.162.1.1
+gatewayip=192.162.1.1
+netmask=255.255.255.0
+hostname=M547xEVB
+netdev=eth0
+loadaddr=10000
+u-boot=u-boot.bin
+load=tftp ${loadaddr) ${u-boot}
+upd=run load; run prog
+prog=prot off bank 1;era ff800000 ff82ffff;cp.b ${loadaddr} ff800000 ${filesize};save
+stdin=serial
+stdout=serial
+stderr=serial
+ethact=FEC0
+mem=65024k
+
+Environment size: 433/8188 bytes
+-> bdin
+memstart = 0x00000000
+memsize = 0x04000000
+flashstart = 0xFF800000
+flashsize = 0x01200000
+flashoffset = 0x00000000
+sramstart = 0xF2000000
+sramsize = 0x00001000
+mbar = 0xF0000000
+busfreq = 133.333 MHz
+pcifreq = 0 MHz
+ethaddr = 00:E0:0C:BC:E5:60
+eth1addr = 00:E0:0C:BC:E5:61
+ip_addr = 192.162.1.2
+baudrate = 115200 bps
+-> ?
+? - alias for 'help'
+base - print or set address offset
+bdinfo - print Board Info structure
+boot - boot default, i.e., run 'bootcmd'
+bootd - boot default, i.e., run 'bootcmd'
+bootelf - Boot from an ELF image in memory
+bootm - boot application image from memory
+bootp - boot image via network using BootP/TFTP protocol
+bootvx - Boot vxWorks from an ELF image
+cmp - memory compare
+coninfo - print console devices and information
+cp - memory copy
+crc32 - checksum calculation
+dcache - enable or disable data cache
+echo - echo args to console
+erase - erase FLASH memory
+flinfo - print FLASH memory information
+go - start application at address 'addr'
+help - print online help
+i2c - I2C sub-system
+icache - enable or disable instruction cache
+iminfo - print header information for application image
+imls - list all images found in flash
+itest - return true/false on integer compare
+loadb - load binary file over serial line (kermit mode)
+loads - load S-Record file over serial line
+loady - load binary file over serial line (ymodem mode)
+loop - infinite loop on address range
+md - memory display
+mii - MII utility commands
+mm - memory modify (auto-incrementing)
+mtest - simple RAM test
+mw - memory write (fill)
+nfs - boot image via network using NFS protocol
+nm - memory modify (constant address)
+pci - list and access PCI Configuration Space
+ping - send ICMP ECHO_REQUEST to network host
+printenv- print environment variables
+protect - enable or disable FLASH write protection
+rarpboot- boot image via network using RARP/TFTP protocol
+reset - Perform RESET of the CPU
+run - run commands in an environment variable
+saveenv - save environment variables to persistent storage
+setenv - set environment variables
+sleep - delay execution for some time
+source - run script from memory
+tftpboot- boot image via network using TFTP protocol
+usb - USB sub-system
+usbboot - boot from USB device
+version - print monitor version
+-> usb start
+(Re)start USB...
+USB: OHCI pci controller (1131, 1561) found @(0:17:0)
+OHCI regs address 0x80000000
+scanning bus for devices... 2 USB Device(s) found
+ scanning bus for storage devices... 1 Storage Device(s) found
+->
diff --git a/board/freescale/mpc7448hpc2/README b/board/freescale/mpc7448hpc2/README
new file mode 100644
index 0000000..cbb043e
--- /dev/null
+++ b/board/freescale/mpc7448hpc2/README
@@ -0,0 +1,184 @@
+Freescale MPC7448hpc2 (Taiga) board
+===================================
+
+Created 08/11/2006 Roy Zang
+--------------------------
+MPC7448hpc2 (Taiga) board is a high-performance PowerPC server reference
+design, which is optimized for high speed throughput between the processor and
+the memory, disk drive and Ethernet port subsystems.
+
+MPC7448hpc2(Taiga) is designed to the micro-ATX chassis, allowing it to be
+used in 1U or 2U rack-mount chassis¡¯, as well as in standard ATX/Micro-ATX
+chassis.
+
+Building U-Boot
+------------------
+The mpc7448hpc2 code base is known to compile using:
+ Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
+
+ $ make mpc7448hpc2_config
+ Configuring for mpc7448hpc2 board...
+
+ $ make
+
+Memory Map
+----------
+
+The memory map is setup for Linux to operate properly.
+
+The mapping is:
+
+ Range Start Range End Definition Size
+
+ 0x0000_0000 0x7fff_ffff DDR 2G
+ 0xe000_0000 0xe7ff_ffff PCI Memory 128M
+ 0xfa00_0000 0xfaff_ffff PCI IO 16M
+ 0xfb00_0000 0xfbff_ffff PCI Config 16M
+ 0xfc00_0000 0xfc0f_ffff NVRAM/CADMUS 1M
+ 0xfe00_0000 0xfeff_ffff PromJet 16M
+ 0xff00_0000 0xff80_0000 FLASH (boot flash) 8M
+ 0xff80_0000 0xffff_ffff FLASH (second half flash) 8M
+
+Using Flash
+-----------
+
+The MPC7448hpc2 board has two "banks" of flash, each 8MB in size
+(2^23 = 0x00800000).
+
+Note: the "bank" here refers to half of the flash. In fact, there is only one
+bank of flash, which is divided into low and high half. Each is controlled by
+the most significant bit of the address bus. The so called "bank" is only for
+convenience.
+
+There is a switch which allows the "bank" to be selected. The switch
+settings for updating flash are given below.
+
+The u-boot commands for copying the boot-bank into the secondary bank are
+as follows:
+
+ erase ff800000 ff880000
+ cp.b ff000000 ff800000 80000
+
+U-boot commands for downloading an image via tftp and flashing
+it into the secondary bank:
+
+ tftp 10000 <u-boot.bin.image>
+ erase ff000000 ff080000
+ cp.b 10000 ff000000 80000
+
+After copying the image into the second bank of flash, be sure to toggle
+SW3[4] on board before resetting the board in order to set the
+secondary bank as the boot-bank.
+
+Board Switches
+----------------------
+
+Most switches on the board should not be changed. The most frequent
+user-settable switches on the board are used to configure
+the flash banks and determining the PCI frequency.
+
+SW1[1-5]: Processor core voltage
+
+ 12345 Core Voltage
+ -----
+ SW1=01111 1.000V.
+ SW1=01101 1.100V.
+ SW1=01011 1.200V.
+ SW1=01001 1.300V only for MPC7447A.
+
+
+SW2[1-6]: CPU core frequency
+
+ CPU Core Frequency (MHz)
+ Bus Frequency
+ 123456 100 133 167 200 Ratio
+
+ ------
+ SW2=101100 500 667 833 1000 5x
+ SW2=100100 550 733 917 1100 5.5x
+ SW2=110100 600 800 1000 1200 6x
+ SW2=010100 650 866 1083 1300 6.5x
+ SW2=001000 700 930 1167 1400 7x
+ SW2=000100 750 1000 1250 1500 7.5x
+ SW2=110000 800 1066 1333 1600 8x
+ SW2=011000 850 1333 1417 1700 8.5x only for MPC7447A
+ SW2=011110 900 1200 1500 1800 9x
+
+This table shows only a subset of available frequency options; see the CPU
+hardware specifications for more information.
+
+SW2[7-8]: Bus Protocol and CPU Reset Option
+
+ 7
+ -
+ SW2=0 System bus uses MPX bus protocol
+ SW2=1 System bus uses 60x bus protocol
+
+ 8
+ -
+ SW2=0 TSI108 can cause CPU reset
+ SW2=1 TSI108 can not cause CPU reset
+
+SW3[1-8] system options
+
+ 123
+ ---
+ SW3=xxx Connected to GPIO[0:2] on TSI108
+
+ 4
+ -
+ SW3=0 CPU boots from low half of flash
+ SW3=1 CPU boots from high half of flash
+
+ 5
+ -
+ SW3=0 SATA and slot2 connected to PCI bus
+ SW3=1 Only slot1 connected to PCI bus
+
+ 6
+ -
+ SW3=0 USB connected to PCI bus
+ SW3=1 USB disconnected from PCI bus
+
+ 7
+ -
+ SW3=0 Flash is write protected
+ SW3=1 Flash is NOT write protected
+
+ 8
+ -
+ SW3=0 CPU will boot from flash
+ SW3=1 CPU will boot from PromJet
+
+SW4[1-3]: System bus frequency
+
+ Bus Frequency (MHz)
+ ---
+ SW4=010 183
+ SW4=011 100
+ SW4=100 133
+ SW4=101 166 only for MPC7447A
+ SW4=110 200 only for MPC7448
+ others reserved
+
+SW4[4-6]: DDR2 SDRAM frequency
+
+ Bus Frequency (MHz)
+ ---
+ SW4=000 external clock
+ SW4=011 system clock
+ SW4=100 133
+ SW4=101 166
+ SW4=110 200
+ others reserved
+
+SW4[7-8]: PCI/PCI-X frequency control
+ 7
+ -
+ SW4=0 PCI/PCI-X bus operates normally
+ SW4=1 PCI bus forced to PCI-33 mode
+
+ 8
+ -
+ SW4=0 PCI-X mode at 133 MHz allowed
+ SW4=1 PCI-X mode limited to 100 MHz
diff --git a/board/freescale/mpc8313erdb/README b/board/freescale/mpc8313erdb/README
new file mode 100644
index 0000000..be7ef32
--- /dev/null
+++ b/board/freescale/mpc8313erdb/README
@@ -0,0 +1,111 @@
+Freescale MPC8313ERDB Board
+-----------------------------------------
+
+1. Board Switches and Jumpers
+
+ S3 is used to set CONFIG_SYS_RESET_SOURCE.
+
+ To boot the image at 0xFE000000 in NOR flash, use these DIP
+ switch settings for S3 S4:
+
+ +------+ +------+
+ | | | **** |
+ | **** | | |
+ +------+ ON +------+ ON
+ 4321 4321
+ (where the '*' indicates the position of the tab of the switch.)
+
+ To boot the image at the beginning of NAND flash, use these
+ DIP switch settings for S3 S4:
+
+ +------+ +------+
+ | * | | *** |
+ | *** | | * |
+ +------+ ON +------+ ON
+ 4321 4321
+ (where the '*' indicates the position of the tab of the switch.)
+
+ When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
+
+2. Memory Map
+ The memory map looks like this:
+
+ 0x0000_0000 0x07ff_ffff DDR 128M
+ 0x8000_0000 0x8fff_ffff PCI MEM 256M
+ 0x9000_0000 0x9fff_ffff PCI_MMIO 256M
+ 0xe000_0000 0xe00f_ffff IMMR 1M
+ 0xe200_0000 0xe20f_ffff PCI IO 16M
+ 0xe280_0000 0xe280_7fff NAND FLASH (CS1) 32K
+ 0xf000_0000 0xf001_ffff VSC7385 (CS2) 128K
+ 0xfa00_0000 0xfa00_7fff Board Status/ 32K
+ LED Control (CS3)
+ 0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M
+
+ When booting from NAND, NAND flash is CS0 and NOR flash
+ is CS1.
+
+3. Definitions
+
+3.1 Explanation of NEW definitions in:
+
+ include/configs/MPC8313ERDB.h
+
+ CONFIG_MPC83xx MPC83xx family
+ CONFIG_MPC831x MPC831x specific
+ CONFIG_MPC8313ERDB MPC8313ERDB board specific
+
+4. Compilation
+
+ Assuming you're using BASH (or similar) as your shell:
+
+ export CROSS_COMPILE=your-cross-compiler-prefix-
+ make distclean
+ make MPC8313ERDB_XXX_config
+ (where XXX is:
+ 33 - 33 MHz oscillator, boot from NOR flash
+ 66 - 66 MHz oscillator, boot from NOR flash
+ NAND_33 - 33 MHz oscillator, boot from NAND flash
+ NAND_66 - 66 MHz oscillator, boot from NAND flash)
+ make
+
+5. Downloading and Flashing Images
+
+5.1 Reflash U-boot Image using U-boot
+
+ NOR flash:
+
+ =>run tftpflash
+
+ You may want to try
+ =>tftpboot $loadaddr $uboot
+ first, to make sure that the TFTP load will succeed before it
+ goes ahead and wipes out your current firmware. And of course,
+ have an alternate means of programming the flash available
+ if the new u-boot doesn't boot.
+
+ NAND flash:
+
+ =>tftpboot $loadaddr <filename>
+ =>nand erase 0 0x80000
+ =>nand write $loadaddr 0 0x80000
+
+ ...where 0x80000 is the filesize rounded up to
+ the next 0x20000 increment.
+
+5.2 Downloading and Booting Linux Kernel
+
+ Ensure that all networking-related environment variables are set
+ properly (including ipaddr, serverip, gatewayip (if needed),
+ netmask, ethaddr, eth1addr, rootpath (if using NFS root),
+ fdtfile, and bootfile).
+
+ Then, do one of the following, depending on whether you
+ want an NFS root or a ramdisk root:
+
+ =>run nfsboot
+ or
+ =>run ramboot
+
+6 Notes
+
+ The console baudrate for MPC8313ERDB is 115200bps.
diff --git a/board/freescale/mpc8315erdb/README b/board/freescale/mpc8315erdb/README
new file mode 100644
index 0000000..b32132d
--- /dev/null
+++ b/board/freescale/mpc8315erdb/README
@@ -0,0 +1,105 @@
+Freescale MPC8315ERDB Board
+-----------------------------------------
+
+1. Board Switches and Jumpers
+
+ S3 is used to set CONFIG_SYS_RESET_SOURCE.
+
+ To boot the image at 0xFE000000 in NOR flash, use these DIP
+ switch settings for S3 S4:
+
+ +------+ +------+
+ | | | **** |
+ | **** | | |
+ +------+ ON +------+ ON
+ 4321 4321
+ (where the '*' indicates the position of the tab of the switch.)
+
+ To boot the image at the beginning of NAND flash, use these
+ DIP switch settings for S3 S4:
+
+ +------+ +------+
+ | * | | *** |
+ | *** | | * |
+ +------+ ON +------+ ON
+ 4321 4321
+ (where the '*' indicates the position of the tab of the switch.)
+
+ When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
+
+2. Memory Map
+ The memory map looks like this:
+
+ 0x0000_0000 0x07ff_ffff DDR 128M
+ 0x8000_0000 0x8fff_ffff PCI MEM 256M
+ 0x9000_0000 0x9fff_ffff PCI_MMIO 256M
+ 0xe000_0000 0xe00f_ffff IMMR 1M
+ 0xe030_0000 0xe03f_ffff PCI IO 1M
+ 0xe060_0000 0xe060_7fff NAND FLASH (CS1) 32K
+ 0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M
+
+ When booting from NAND, NAND flash is CS0 and NOR flash
+ is CS1.
+
+3. Definitions
+
+3.1 Explanation of NEW definitions in:
+
+ include/configs/MPC8315ERDB.h
+
+ CONFIG_MPC83xx MPC83xx family
+ CONFIG_MPC831x MPC831x specific
+ CONFIG_MPC8315 MPC8315 specific
+ CONFIG_MPC8315ERDB MPC8315ERDB board specific
+
+4. Compilation
+
+ Assuming you're using BASH (or similar) as your shell:
+
+ export CROSS_COMPILE=your-cross-compiler-prefix-
+ make distclean
+ make MPC8315ERDB_config (or MPC8315ERDB_NAND_config for u-boot-nand.bin)
+ make all
+
+5. Downloading and Flashing Images
+
+5.1 Reflash U-boot Image using U-boot
+
+ NOR flash:
+
+ tftp 40000 u-boot.bin
+ protect off all
+ erase fe000000 fe1fffff
+
+ cp.b 40000 fe000000 xxxx
+ protect on all
+
+ You have to supply the correct byte count with 'xxxx'
+ from the TFTP result log.
+
+ NAND flash:
+
+ =>tftpboot $loadaddr <filename>
+ =>nand erase 0 0x80000
+ =>nand write $loadaddr 0 0x80000
+
+ ...where 0x80000 is the filesize rounded up to
+ the next 0x20000 increment.
+
+5.2 Downloading and Booting Linux Kernel
+
+ Ensure that all networking-related environment variables are set
+ properly (including ipaddr, serverip, gatewayip (if needed),
+ netmask, ethaddr, eth1addr, rootpath (if using NFS root),
+ fdtfile, and bootfile).
+
+ Then, do one of the following, depending on whether you
+ want an NFS root or a ramdisk root:
+
+ =>run nfsboot
+ or
+ =>run ramboot
+
+6 Notes
+
+ The console baudrate for MPC8315ERDB is 115200bps.
diff --git a/board/freescale/mpc8323erdb/README b/board/freescale/mpc8323erdb/README
new file mode 100644
index 0000000..6f89829
--- /dev/null
+++ b/board/freescale/mpc8323erdb/README
@@ -0,0 +1,71 @@
+Freescale MPC8323ERDB Board
+-----------------------------------------
+
+1. Memory Map
+ The memory map looks like this:
+
+ 0x0000_0000 0x03ff_ffff DDR 64M
+ 0x8000_0000 0x8fff_ffff PCI MEM 256M
+ 0x9000_0000 0x9fff_ffff PCI_MMIO 256M
+ 0xe000_0000 0xe00f_ffff IMMR 1M
+ 0xd000_0000 0xd3ff_ffff PCI IO 64M
+ 0xfe00_0000 0xfeff_ffff NOR FLASH (CS0) 16M
+
+2. Compilation
+
+ Assuming you're using BASH (or similar) as your shell:
+
+ export CROSS_COMPILE=your-cross-compiler-prefix-
+ make distclean
+ make MPC8323ERDB_config
+ make
+
+3. Downloading and Flashing Images
+
+3.1 Reflash U-boot Image using U-boot
+
+ N.b, have an alternate means of programming
+ the flash available if the new u-boot doesn't boot.
+
+ First try a:
+
+ tftpboot $loadaddr $uboot
+
+ to make sure that the TFTP load will succeed before
+ an erase goes ahead and wipes out your current firmware.
+ Then do a:
+
+ run tftpflash
+
+ which is a shorter version of the manual sequence:
+
+ tftp $loadaddr u-boot.bin
+ protect off fe000000 +$filesize
+ erase fe000000 +$filesize
+ cp.b $loadaddr fe000000 $filesize
+
+ To keep your old u-boot's environment variables, do a:
+
+ saveenv
+
+ prior to resetting the board.
+
+3.2 Downloading and Booting Linux Kernel
+
+ Ensure that all networking-related environment variables are set
+ properly (including ipaddr, serverip, gatewayip (if needed),
+ netmask, ethaddr, eth1addr, rootpath (if using NFS root),
+ fdtfile, and bootfile).
+
+ Then, do one of the following, depending on whether you
+ want an NFS root or a ramdisk root:
+
+ run nfsboot
+
+ or
+
+ run ramboot
+
+4 Notes
+
+ The console baudrate for MPC8323ERDB is 115200bps.
diff --git a/board/freescale/mpc832xemds/README b/board/freescale/mpc832xemds/README
new file mode 100644
index 0000000..4142aa9
--- /dev/null
+++ b/board/freescale/mpc832xemds/README
@@ -0,0 +1,128 @@
+Freescale MPC832XEMDS Board
+-----------------------------------------
+1. Board Switches and Jumpers
+1.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board
+ For some reason, the HW designers describe the switch settings
+ in terms of 0 and 1, and then map that to physical switches where
+ the label "On" refers to logic 0 and "Off" is logic 1.
+
+ Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
+ bits may contribute to signals that are numbered based at 0,
+ and some of those signals may be high-bit-number-0 too. Heed
+ well the names and labels and do not get confused.
+
+ "Off" == 1
+ "On" == 0
+
+ SW3 is switch 18 as silk-screened onto the board.
+ SW4[8] is the bit labeled 8 on Switch 4.
+ SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5.
+ SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6.
+ SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
+ and bits labeled 8 is set as "Off".
+
+1.1 For the MPC832XEMDS PROTO Board
+
+ First, make sure the board default setting is consistent with the document
+ shipped with your board. Then apply the following setting:
+ SW3[1-8]= 0000_1000 (core PLL setting, core enable)
+ SW4[1-8]= 0001_0010 (Flash boot on local bus, system PLL setting)
+ SW5[1-8]= 0010_0110 (Boot from high end)
+ SW6[1-8]= 0011_0100 (Flash boot on 16 bit local bus)
+ SW7[1-8]= 1000_0011 (QE PLL setting)
+
+ ENET3/4 MII mode settings:
+ J1 1-2 (ETH3_TXER)
+ J2 2-3 (MII mode)
+ J3 2-3 (MII mode)
+ J4 2-3 (ADSL clockOscillator)
+ J5 1-2 (ETH4_TXER)
+ J6 2-3 (ClockOscillator)
+ JP1 removed (don't force PORESET)
+ JP2 mounted (ETH4/2 MII)
+ JP3 mounted (ETH3 MII)
+ JP4 mounted (HRCW from BCSR)
+
+ ENET3/4 RMII mode settings:
+ J1 1-2 (ETH3_TXER)
+ J2 1-2 (RMII mode)
+ J3 1-2 (RMII mode)
+ J4 2-3 (ADSL clockOscillator)
+ J5 1-2 (ETH4_TXER)
+ J6 2-3 (ClockOscillator)
+ JP1 removed (don't force PORESET)
+ JP2 removed (ETH4/2 RMII)
+ JP3 removed (ETH3 RMII)
+ JP4 removed (HRCW from FLASH)
+
+ on board Oscillator: 66M
+
+
+2. Memory Map
+
+2.1 The memory map should look pretty much like this:
+
+ 0x0000_0000 0x7fff_ffff DDR 2G
+ 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
+ 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
+ 0xc000_0000 0xdfff_ffff Empty 512M
+ 0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M
+ 0xe020_0000 0xe02f_ffff Empty 1M
+ 0xe030_0000 0xe03f_ffff PCI IO 1M
+ 0xe040_0000 0xefff_ffff Empty 252M
+ 0xf400_0000 0xf7ff_ffff Empty 64M
+ 0xf800_0000 0xf800_7fff BCSR on CS1 32K
+ 0xf800_8000 0xf800_ffff PIB CS2 32K
+ 0xf801_0000 0xf801_7fff PIB CS3 32K
+ 0xfe00_0000 0xfeff_ffff FLASH on CS0 16M
+
+
+3. Definitions
+
+3.1 Explanation of NEW definitions in:
+
+ include/configs/MPC832XEPB.h
+
+ CONFIG_MPC83xx MPC83xx family for MPC8349, MPC8360 and MPC832x
+ CONFIG_MPC832x MPC832x specific
+ CONFIG_MPC832XEMDS MPC832XEMDS board specific
+
+4. Compilation
+
+ Assuming you're using BASH shell:
+
+ export CROSS_COMPILE=your-cross-compile-prefix
+ cd u-boot
+ make distclean
+ make MPC832XEMDS_config
+ make
+
+ MPC832x support PCI 33MHz and PCI 66MHz, to make u-boot support PCI:
+
+ 1)Make sure the DIP SW support PCI mode as described in Section 1.1.
+
+ 2)To Make U-Boot image support PCI 33MHz, use
+ Make MPC832XEMDS_HOST_33_config
+
+ 3)To Make U-Boot image support PCI 66MHz, use
+ Make MPC832XEMDS_HOST_66M_config
+
+5. Downloading and Flashing Images
+
+5.0 Download over network:
+
+ tftp 10000 u-boot.bin
+
+5.1 Reflash U-boot Image using U-boot
+
+ tftp 20000 u-boot.bin
+ protect off fe000000 fe0fffff
+ erase fe000000 fe0fffff
+ cp.b 20000 fe000000 xxxx
+
+You have to supply the correct byte count with 'xxxx' from the TFTP result log.
+Maybe 3ffff will work too, that corresponds to the erased sectors.
+
+
+6. Notes
+ 1) The console baudrate for MPC832XEMDS is 115200bps.
diff --git a/board/freescale/mpc8349itx/README b/board/freescale/mpc8349itx/README
new file mode 100644
index 0000000..48bbd50
--- /dev/null
+++ b/board/freescale/mpc8349itx/README
@@ -0,0 +1,187 @@
+Freescale MPC8349E-mITX and MPC8349E-mITX-GP Boards
+---------------------------------------------------
+
+1. Board Description
+
+ The MPC8349E-mITX and MPC8349E-mITX-GP are reference boards featuring
+ the Freescale MPC8349E processor in a Mini-ITX form factor.
+
+ The MPC8349E-mITX-GP is an MPC8349E-mITX with the following differences:
+
+ A) One 8MB on-board flash EEPROM chip, instead of two.
+ B) No SATA controller
+ C) No Compact Flash slot
+ D) No Mini-PCI slot
+ E) No Vitesse 7385 5-port Ethernet switch
+ F) No 4-port USB Type-A interface
+
+2. Board Switches and Jumpers
+
+2.0 Descriptions for all of the board jumpers can be found in the User
+ Guide. Of particular interest to U-Boot developers is jumper J22:
+
+ Pos. Name Default Description
+ -----------------------------------------------------------------------
+ A LGPL0 ON (0) HRCW source, bit 0
+ B LGPL1 ON (0) HRCW source, bit 1
+ C LGPL3 ON (0) HRCW source, bit 2
+ D LGPL5 OFF (1) PCI_SYNC_OUT frequency
+ E BOOT1 ON (0) Flash EEPROM boot device
+ F PCI_M66EN ON (0) PCI 66MHz enable
+ G I2C-WP ON (0) I2C EEPROM write protection
+ H F_WP OFF (1) Flash EEPROM write protection
+
+ Jumper J22.E is only for the ITX, and it decides the configuration
+ of the flash chips. If J22.E is ON (i.e. jumpered), then flash chip
+ U4 is located at address FE000000 and flash chip U7 is at FE800000.
+ If J22.E is OFF, then U7 is at FE000000 and U4 is at FE800000.
+
+ For U-Boot development, J22.E can be used to switch back-and-forth
+ between two U-Boot images.
+
+3. Memory Map
+
+3.1. The memory map should look pretty much like this:
+
+ 0x0000_0000 - 0x0FFF_FFFF DDR SDRAM (256 MB)
+ 0x8000_0000 - 0x9FFF_FFFF PCI1 memory space (512 MB)
+ 0xA000_0000 - 0xBFFF_FFFF PCI2 memory space (512 MB)
+ 0xE000_0000 - 0xEFFF_FFFF IMMR (1 MB)
+ 0xE200_0000 - 0xE2FF_FFFF PCI1 I/O space (16 MB)
+ 0xE300_0000 - 0xE3FF_FFFF PCI2 I/O space (16 MB)
+ 0xF000_0000 - 0xF000_FFFF Compact Flash (ITX only)
+ 0xF001_0000 - 0xF001_FFFF Local bus expansion slot
+ 0xF800_0000 - 0xF801_FFFF Vitesse 7385 Parallel Interface (ITX only)
+ 0xFE00_0000 - 0xFE7F_FFFF First 8MB bank of Flash memory
+ 0xFE80_0000 - 0xFEFF_FFFF Second 8MB bank of Flash memory (ITX only)
+
+3.2 Flash EEPROM layout.
+
+ On the ITX, jumper J22.E is used to determine which flash chips are
+ at which address. When J22.E is switched, addresses from FE000000
+ to FE7FFFFF are swapped with addresses from FE800000 to FEFFFFFF.
+
+ On the ITX, at the normal boot address (aka HIGHBOOT):
+
+ FE00_0000 HRCW
+ FE70_0000 Alternative U-Boot image
+ FE80_0000 Alternative HRCW
+ FEF0_0000 U-Boot image
+ FEFF_FFFF End of flash
+
+ On the ITX, at the low boot address (LOWBOOT)
+
+ FE00_0000 HRCW and U-Boot image
+ FE04_0000 U-Boot environment variables
+ FE80_0000 Alternative HRCW and U-Boot image
+ FEFF_FFFF End of flash
+
+ On the ITX-GP, the only option is LOWBOOT and there is only one chip
+
+ FE00_0000 HRCW and U-Boot image
+ FE04_0000 U-Boot environment variables
+ F7FF_FFFF End of flash
+
+4. Definitions
+
+4.1 Explanation of NEW definitions in:
+
+ include/configs/MPC8349ITX.h
+
+ CONFIG_MPC83xx MPC83xx family
+ CONFIG_MPC8349 MPC8349 specific
+ CONFIG_MPC8349ITX MPC8349E-mITX
+ CONFIG_MPC8349ITXGP MPC8349E-mITX-GP
+
+5. Compilation
+
+ Assuming you're using BASH shell:
+
+ export CROSS_COMPILE=your-cross-compile-prefix
+ cd u-boot
+ make distclean
+
+ make MPC8349ITX_config
+ or:
+ make MPC8349ITXGP_config
+ or:
+ make MPC8349ITX_LOWBOOT_config
+
+ make
+
+6. Downloading and Flashing Images
+
+6.1 Download via tftp:
+
+ tftp $loadaddr <uboot>
+
+ where "<uboot>" is the path and filename, on the TFTP server, of
+ the U-Boot image.
+
+6.1 Reflash U-Boot Image using U-Boot
+
+ setenv uboot <uboot>
+ run tftpflash
+
+ where "<uboot>" is the path and filename, on the TFTP server, of
+ the U-Boot image.
+
+6.2 Using the HRCW to switch between two different U-Boot images on the ITX
+
+ Because the ITX has 16MB of flash, it is possible to keep two U-Boot
+ images in flash, and use the HRCW to specify which one is to be used
+ when the board boots. This trick is especially effective with a
+ hardware debugger that can override the HRCW, such as the BDI-2000.
+
+ When the BMS bit in the HRCW is 0, the ITX will boot the U-Boot image
+ at address FE000000. When the BMS bit is 1, the ITX will boot the
+ image at address FEF00000.
+
+ Therefore, just put a U-Boot image at both FE000000 and FEF00000 and
+ change the BMS bit whenever you want to boot the other image.
+
+ Step-by-step instructions:
+
+ 1) Build an ITX image to be loaded at FEF00000
+
+ make distclean
+ make MPC8349ITX_config
+ make
+
+ 2) Take the u-boot.bin image and flash it at FEF00000.
+
+ tftp $loadaddr u-boot.bin
+ protect off all
+ erase FEF00000 +$filesize
+ cp.b $loadaddr FEF00000 $filesize
+
+ 3) Build an ITX image to be loaded at FE000000
+
+ make distclean
+ make MPC8349ITX_LOWBOOT_config
+ make
+
+ 4) Take the u-boot.bin image and flash it at FE000000.
+
+ tftp $loadaddr u-boot.bin
+ protect off FE000000 +$filesize
+ erase FE000000 +$filesize
+ cp.b $loadaddr FE000000 $filesize
+
+ The HRCW in flash is currently set to boot the image at FE000000.
+
+ If you have a hardware debugger, configure it to set the HRCW to
+ B460A000 04040000 if you want to boot the image at FEF00000, or set
+ it to B060A000 04040000 if you want to boot the image at FE000000.
+
+ To change the HRCW in flash to boot the image at FEF00000, use these
+ U-Boot commands:
+
+ cp.b FE000000 1000 10000 ; copy 1st flash sector to 1000
+ mw.b 1020 b4 8 ; modify BMS bit
+ protect off FE000000 +10000
+ erase FE000000 +10000
+ cp.b 1000 FE000000 10000
+
+7. Notes
+ 1) The console baudrate for MPC8349EITX is 115200bps.
diff --git a/board/freescale/mpc8360emds/README b/board/freescale/mpc8360emds/README
new file mode 100644
index 0000000..6afa753
--- /dev/null
+++ b/board/freescale/mpc8360emds/README
@@ -0,0 +1,155 @@
+Freescale MPC8360EMDS Board
+-----------------------------------------
+1. Board Switches and Jumpers
+1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC8360EMDS board
+ For some reason, the HW designers describe the switch settings
+ in terms of 0 and 1, and then map that to physical switches where
+ the label "On" refers to logic 0 and "Off" is logic 1.
+
+ Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
+ bits may contribute to signals that are numbered based at 0,
+ and some of those signals may be high-bit-number-0 too. Heed
+ well the names and labels and do not get confused.
+
+ "Off" == 1
+ "On" == 0
+
+ SW18 is switch 18 as silk-screened onto the board.
+ SW4[8] is the bit labeled 8 on Switch 4.
+ SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
+ SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3.
+ SW3[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
+ and bits labeled 8 is set as "Off".
+
+1.1 There are three type boards for MPC8360E silicon up to now, They are
+
+ * MPC8360E-MDS-PB PROTO (a.k.a 8360SYS PROTOTYPE)
+ * MPC8360E-MDS-PB PILOT (a.k.a 8360SYS PILOT)
+ * MPC8360EA-MDS-PB PROTO (a.k.a 8360SYS2 PROTOTYPE)
+
+1.2 For all the MPC8360EMDS Board
+
+ First, make sure the board default setting is consistent with the
+ document shipped with your board. Then apply the following setting:
+ SW3[1-8]= 0000_0100 (HRCW setting value is performed on local bus)
+ SW4[1-8]= 0011_0000 (Flash boot on local bus)
+ SW9[1-8]= 0110_0110 (PCI Mode enabled. HRCW is read from FLASH)
+ SW10[1-8]= 0000_1000 (core PLL setting)
+ SW11[1-8]= 0000_0100 (SW11 is on the another side of the board)
+ JP6 1-2
+ on board Oscillator: 66M
+
+1.3 Since different board/chip rev. combinations have AC timing issues,
+ u-boot forces RGMII-ID (RGMII with Internal Delay) mode on by default
+ by the patch (mpc83xx: Disable G1TXCLK, G2TXCLK h/w buffers).
+
+ When the rev2.x silicon mount on these boards, and if you are using
+ u-boot version after this patch, to make the ethernet interfaces usable,
+ and to enable RGMII-ID on your board, you have to setup the jumpers
+ correctly.
+
+ * MPC8360E-MDS-PB PROTO
+ nothing to do
+ * MPC8360E-MDS-PB PILOT
+ JP9 and JP8 should be ON
+ * MPC8360EA-MDS-PB PROTO
+ JP2 and JP3 should be ON
+
+2. Memory Map
+
+2.1. The memory map should look pretty much like this:
+
+ 0x0000_0000 0x7fff_ffff DDR 2G
+ 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
+ 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
+ 0xc000_0000 0xdfff_ffff Empty 512M
+ 0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M
+ 0xe020_0000 0xe02f_ffff Empty 1M
+ 0xe030_0000 0xe03f_ffff PCI IO 1M
+ 0xe040_0000 0xefff_ffff Empty 252M
+ 0xf000_0000 0xf3ff_ffff Local Bus SDRAM 64M
+ 0xf400_0000 0xf7ff_ffff Empty 64M
+ 0xf800_0000 0xf800_7fff BCSR on CS1 32K
+ 0xf800_8000 0xf800_ffff PIB CS4 32K
+ 0xf801_0000 0xf801_7fff PIB CS5 32K
+ 0xfe00_0000 0xfeff_ffff FLASH on CS0 16M
+
+
+3. Definitions
+
+3.1 Explanation of NEW definitions in:
+
+ include/configs/MPC8360EMDS.h
+
+ CONFIG_MPC83xx MPC83xx family for both MPC8349 and MPC8360
+ CONFIG_MPC8360 MPC8360 specific
+ CONFIG_MPC8360EMDS MPC8360EMDS board specific
+
+4. Compilation
+
+ MPC8360EMDS shipped with 33.33MHz or 66MHz oscillator(check U41 chip).
+
+ Assuming you're using BASH shell:
+
+ export CROSS_COMPILE=your-cross-compile-prefix
+ cd u-boot
+ make distclean
+ make MPC8360EMDS_XX_config
+ make
+
+ MPC8360EMDS support ATM, PCI in host and slave mode.
+
+ To make u-boot support ATM :
+ 1) Make MPC8360EMDS_XX_ATM_config
+
+ To make u-boot support PCI host 66M :
+ 1) DIP SW support PCI mode as described in Section 1.1.
+ 2) Make MPC8360EMDS_XX_HOST_66_config
+
+ To make u-boot support PCI host 33M :
+ 1) DIP SW setting is similar as Section 1.1, except for SW3[4] is 1
+ 2) Make MPC8360EMDS_XX_HOST_33_config
+
+ To make u-boot support PCI slave 66M :
+ 1) DIP SW setting is similar as Section 1.1, except for SW9[3] is 1
+ 2) Make MPC8360EMDS_XX_SLAVE_config
+
+ (where XX is:
+ 33 - 33.33MHz oscillator
+ 66 - 66MHz oscillator)
+
+5. Downloading and Flashing Images
+
+5.0 Download over serial line using Kermit:
+
+ loadb
+ [Drop to kermit:
+ ^\c
+ send <u-boot-bin-image>
+ c
+ ]
+
+
+ Or via tftp:
+
+ tftp 10000 u-boot.bin
+
+5.1 Reflash U-boot Image using U-boot
+
+ tftp 20000 u-boot.bin
+ protect off fef00000 fef3ffff
+ erase fef00000 fef3ffff
+
+ cp.b 20000 fef00000 xxxx
+
+ or
+
+ cp.b 20000 fef00000 3ffff
+
+
+You have to supply the correct byte count with 'xxxx' from the TFTP result log.
+Maybe 3ffff will work too, that corresponds to the erased sectors.
+
+
+6. Notes
+ 1) The console baudrate for MPC8360EMDS is 115200bps.
diff --git a/board/freescale/mpc837xemds/README b/board/freescale/mpc837xemds/README
new file mode 100644
index 0000000..faf21c9
--- /dev/null
+++ b/board/freescale/mpc837xemds/README
@@ -0,0 +1,104 @@
+Freescale MPC837xEMDS Board
+-----------------------------------------
+1. Board Switches and Jumpers
+1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC837xEMDS board
+ For some reason, the HW designers describe the switch settings
+ in terms of 0 and 1, and then map that to physical switches where
+ the label "On" refers to logic 0 and "Off" is logic 1.
+
+ Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
+ bits may contribute to signals that are numbered based at 0,
+ and some of those signals may be high-bit-number-0 too. Heed
+ well the names and labels and do not get confused.
+
+ "Off" == 1
+ "On" == 0
+
+ SW4[8] is the bit labeled 8 on Switch 4.
+ SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
+ SW2[1:8]= 0000_0001 refers to bits labeled 1 through 7 is set as "On"
+ and bits labeled 8 is set as "Off".
+
+1.1 For the MPC837xEMDS Processor Board
+
+ First, make sure the board default setting is consistent with the
+ document shipped with your board. Then apply the following setting:
+ SW3[1-8]= 0011_0000 (BOOTSEQ, ROMLOC setting)
+ SW4[1-8]= 0000_0110 (core PLL setting)
+ SW5[1-8]= 1001_1000 (system PLL, boot up from low end of flash)
+ SW6[1-8]= 0000_1000 (HRCW is read from NOR FLASH)
+ SW7[1-8]= 0110_1101 (TSEC1/2 interface setting - RGMII)
+ J3 2-3, TSEC1 LVDD1 with 2.5V
+ J6 2-3, TSEC2 LVDD2 with 2.5V
+ J9 2-3, CLKIN from osc on board
+ J10 removed, CS0 connect to NOR flash; when mounted, CS0 connect to NAND
+ J11 removed, Hardware Reset Configuration Word load from FLASH(NOR or NAND)
+ mounted, HRCW load from BCSR.
+
+ on board Oscillator: 66M
+
+2. Memory Map
+
+2.1. The memory map should look pretty much like this:
+
+ 0x0000_0000 0x7fff_ffff DDR 2G
+ 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
+ 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
+ 0xc000_0000 0xdfff_ffff Empty 512M
+ 0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M
+ 0xe010_0000 0xe02f_ffff Empty 2M
+ 0xe030_0000 0xe03f_ffff PCI IO 1M
+ 0xe040_0000 0xe05f_ffff Empty 2M
+ 0xe060_0000 0xe060_7fff NAND Flash 32K
+ 0xf400_0000 0xf7ff_ffff Empty 64M
+ 0xf800_0000 0xf800_7fff BCSR on CS1 32K
+ 0xfe00_0000 0xffff_ffff NOR Flash on CS0 32M
+
+3. Definitions
+
+3.1 Explanation of NEW definitions in:
+
+ include/configs/MPC837XEMDS.h
+
+ CONFIG_MPC83xx MPC83xx family for both MPC837x and MPC8360
+ CONFIG_MPC837x MPC837x specific
+ CONFIG_MPC837XEMDS MPC837XEMDS board specific
+
+4. Compilation
+
+ Assuming you're using BASH shell:
+
+ export CROSS_COMPILE=your-cross-compile-prefix
+ cd u-boot
+ make distclean
+ make MPC837XEMDS_config
+ make
+
+5. Downloading and Flashing Images
+
+5.0 Download over serial line using Kermit:
+
+ loadb
+ [Drop to kermit:
+ ^\c
+ send <u-boot-bin-image>
+ c
+ ]
+
+
+ Or via tftp:
+
+ tftp 40000 u-boot.bin
+
+5.1 Reflash U-boot Image using U-boot
+
+ tftp 40000 u-boot.bin
+ protect off fe000000 fe1fffff
+ erase fe000000 fe1fffff
+
+ cp.b 40000 fe000000 xxxx
+
+You have to supply the correct byte count with 'xxxx' from the TFTP result log.
+
+6. Notes
+ 1) The console baudrate for MPC837XEMDS is 115200bps.
diff --git a/board/freescale/mpc837xerdb/README b/board/freescale/mpc837xerdb/README
new file mode 100644
index 0000000..cfb6efa
--- /dev/null
+++ b/board/freescale/mpc837xerdb/README
@@ -0,0 +1,97 @@
+Freescale MPC837xE-RDB Board
+-----------------------------------------
+
+1. Board Description
+
+ The MPC837xE-RDB are reference boards featuring the Freescale MPC8377E,
+ MPC8378E, and the MPC8379E processors in a Mini-ITX form factor.
+
+ The MPC837xE-RDB's have the following common features:
+
+ A) 256-MBytes on-board DDR2 unbuffered SDRAM
+ B) 8-Mbytes NOR Flash
+ C) 32-MBytes NAND Flash
+ D) 1 Secure Digital High Speed Card (SDHC) Interface
+ E) 1 Gigabit Ethernet
+ F) 5-port Ethernet switch (Vitesse 7385)
+ G) 1 32-bit, 3.3 V, PCI slot
+ H) 1 32-bit, 3.3 V, Mini-PCI slot
+ I) 4-port USB 2.0 Hub
+ J) 1-port OTG USB
+ K) 2 serial ports (top main console)
+ L) on board Oscillator: 66M
+
+ The MPC837xE-RDB's have the following differences:
+
+ MPC8377E-RDB MPC8378E-RDB MPC8379E-RDB
+ SATA controllers 2 0 4
+ PCI-Express (mini) 2 2 0
+ SGMII Ports 0 2 0
+
+
+2. Memory Map
+
+2.1. The memory map should look pretty much like this:
+
+ Address Range Device Size Port Size
+ (Bytes) (Bits)
+ =========================== ================= ======= =========
+ 0x0000_0000 0x0fff_ffff DDR 256M 64
+ 0x1000_0000 0x7fff_ffff Empty 1.75G -
+ 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M 32
+ 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M 32
+ 0xe030_0000 0xe03f_ffff PCI I/O space 1M 32
+ 0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M -
+ 0xe060_0000 0xe060_7fff NAND Flash 32K 8
+ 0xfe00_0000 0xfe7f_ffff NOR Flash on CS0 8M 16
+
+
+3. Definitions
+
+3.1 Explanation of NEW definitions in:
+
+ include/configs/MPC837XERDB.h
+
+ CONFIG_MPC83xx MPC83xx family for both MPC8349 and MPC8360
+ CONFIG_MPC837x MPC837x specific
+ CONFIG_MPC837XERDB MPC837xE-RDB board specific
+
+
+4. Compilation
+
+ Assuming you're using BASH shell:
+
+ export CROSS_COMPILE=your-cross-compile-prefix
+ cd u-boot
+ make distclean
+ make MPC837XERDB_config
+ make
+
+
+5. Downloading and Flashing Images
+
+5.0 Download over serial line using Kermit:
+
+ loadb $loadaddr
+ [Drop to kermit:
+ ^\c
+ send <u-boot-bin-image>
+ c
+ ]
+
+
+ Or via tftp:
+
+ tftp $loadaddr u-boot.bin
+
+5.1 Reflash U-boot Image using U-boot
+
+ tftp $loadaddr u-boot.bin
+ protect off fe000000 fe0fffff
+ erase fe000000 fe0fffff
+ cp.b $loadaddr fe000000 $filesize
+
+
+6. Additional Notes:
+ 1) The console is connected to the top RS-232 connector and the
+ baudrate for MPC837XE-RDB is 115200bps.
diff --git a/board/freescale/mpc8536ds/README b/board/freescale/mpc8536ds/README
new file mode 100644
index 0000000..2a38bd6
--- /dev/null
+++ b/board/freescale/mpc8536ds/README
@@ -0,0 +1,127 @@
+Overview:
+=========
+
+The MPC8536E integrates a PowerPC processor core with system logic
+required for imaging, networking, and communications applications.
+
+Boot from NAND:
+===============
+
+The MPC8536E is capable of booting from NAND flash which uses the image
+u-boot-nand.bin. This image contains two parts: a first stage image(also
+call 4K NAND loader and a second stage image. The former is appended to
+the latter to produce u-boot-nand.bin.
+
+The bootup process can be divided into two stages: the first stage will
+configure the L2SRAM, then copy the second stage image to L2SRAM and jump
+to it. The second stage image is to configure all the hardware and boot up
+to U-Boot command line.
+
+The 4K NAND loader's code comes from the corresponding nand_spl directory,
+along with the code twisted by CONFIG_NAND_SPL. The macro CONFIG_NAND_SPL
+is mainly used to shrink the code size to the 4K size limitation.
+
+The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
+second stage image. It's set in the board config file when boot from NAND
+is selected.
+
+Build and boot steps
+--------------------
+
+1. Building image
+ make MPC8536DS_NAND_config
+ make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
+
+2. Change dip-switch
+ SW2[5-8] = 1011
+ SW9[1-3] = 101
+ Note: 1 stands for 'on', 0 stands for 'off'
+
+3. Flash image
+ tftp 1000000 u-boot-nand.bin
+ nand erase 0 a0000
+ nand write 1000000 0 a0000
+
+Boot from On-chip ROM:
+======================
+
+The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC
+and boot from eSPI. When power on, the porcessor excutes the ROM code to
+initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from
+the memory device that interfaced to the controller, such as the SDCard or
+SPI EEPROM, to the target memory, e.g. SDRAM or L2SRAM, then boot from it.
+
+The memory device should contain a specific data structure with control word
+and config word at the fixed address. The config word direct the process how
+to config the memory device, and the control word direct the processor where
+to find the image on the memory device, or where copy the main image to. The
+user can use any method to store the data structure to the memory device, only
+if store it on the assigned address.
+
+Build and boot steps
+--------------------
+
+For boot from eSDHC:
+1. Build image
+ make MPC8536DS_SDCARD_config
+ make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
+
+2. Change dip-switch
+ SW2[5-8] = 0111
+ SW3[1] = 0
+ SW8[7] = 0 - The on-board SD/MMC slot is active
+ SW8[7] = 1 - The externel SD/MMC slot is active
+
+3. Put image to SDCard
+ Put the follwing info at the assigned address on the SDCard:
+
+ Offset | Data | Description
+ --------------------------------------------------------
+ | 0x40-0x43 | 0x424F4F54 | BOOT signature |
+ --------------------------------------------------------
+ | 0x48-0x4B | 0x00080000 | u-boot.bin's size |
+ --------------------------------------------------------
+ | 0x50-0x53 | 0x???????? | u-boot.bin's Addr on SDCard |
+ --------------------------------------------------------
+ | 0x58-0x5B | 0xF8F80000 | Target Address |
+ -------------------------------------------------------
+ | 0x60-0x63 | 0xF8FFF000 | Execution Starting Address |
+ --------------------------------------------------------
+ | 0x68-0x6B | 0x6 | Number of Config Addr/Data |
+ --------------------------------------------------------
+ | 0x80-0x83 | 0xFF720100 | Config Addr 1 |
+ | 0x84-0x87 | 0xF8F80000 | Config Data 1 |
+ --------------------------------------------------------
+ | 0x88-0x8b | 0xFF720e44 | Config Addr 2 |
+ | 0x8c-0x8f | 0x0000000C | Config Data 2 |
+ --------------------------------------------------------
+ | 0x90-0x93 | 0xFF720000 | Config Addr 3 |
+ | 0x94-0x97 | 0x80010000 | Config Data 3 |
+ --------------------------------------------------------
+ | 0x98-0x9b | 0xFF72e40c | Config Addr 4 |
+ | 0x9c-0x9f | 0x00000040 | Config Data 4 |
+ --------------------------------------------------------
+ | 0xa0-0xa3 | 0x40000001 | Config Addr 5 |
+ | 0xa4-0xa7 | 0x00000100 | Config Data 5 |
+ --------------------------------------------------------
+ | 0xa8-0xab | 0x80000001 | Config Addr 6 |
+ | 0xac-0xaf | 0x80000001 | Config Data 6 |
+ --------------------------------------------------------
+ | ...... |
+ --------------------------------------------------------
+ | 0x???????? | u-boot.bin |
+ --------------------------------------------------------
+
+ then insert the SDCard to the active slot to boot up.
+
+For boot from eSPI:
+1. Build image
+ make MPC8536DS_SPIFLASH_config
+ make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
+
+2. Change dip-switch
+ SW2[5-8] = 0110
+
+3. Put image to SPI flash
+ Put the info in the above table onto the SPI flash, then
+ boot up.
diff --git a/board/freescale/mpc8544ds/README b/board/freescale/mpc8544ds/README
new file mode 100644
index 0000000..b49c3c0
--- /dev/null
+++ b/board/freescale/mpc8544ds/README
@@ -0,0 +1,122 @@
+Overview
+--------
+The MPC8544DS system is similar to the 85xx CDS systems such
+as the MPC8548CDS due to the similar E500 core. However, it
+is placed on the same board as the 8641 HPCN system.
+
+
+Flash Banks
+-----------
+Like the 85xx CDS systems, the 8544 DS board has two flash banks.
+They are both present on boot, but there locations can be swapped
+using the dip-switch SW10, bit 2.
+
+However, unlike the CDS systems, but similar to the 8641 HPCN
+board, a runtime reset through the FPGA can also affect a swap
+on the flash bank mappings for the next reset cycle.
+
+Irrespective of the switch SW10[2], booting is always from the
+boot bank at 0xfff8_0000.
+
+
+Memory Map
+----------
+
+0xff80_0000 - 0xffbf_ffff Alternate bank 4MB
+0xffc0_0000 - 0xffff_ffff Boot bank 4MB
+
+0xffb8_0000 Alternate image start 512KB
+0xfff8_0000 Boot image start 512KB
+
+
+Flashing Images
+---------------
+
+For example, to place a new image in the alternate flash bank
+and then reset with that new image temporarily, use this:
+
+ tftp 1000000 u-boot.bin.8544ds
+ erase ffb80000 ffbfffff
+ cp.b 1000000 ffb80000 80000
+ pixis_reset altbank
+
+
+To overwrite the image in the boot flash bank:
+
+ tftp 1000000 u-boot.bin.8544ds
+ protect off all
+ erase fff80000 ffffffff
+ cp.b 1000000 fff80000 80000
+
+Other example U-Boot image and flash manipulations examples
+can be found in the README.mpc85xxcds file as well.
+
+
+The pixis_reset command
+-----------------------
+A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
+using the FPGA sequencer. When the board restarts, it has the option
+of using either the current or alternate flash bank as the boot
+image, with or without the watchdog timer enabled, and finally with
+or without frequency changes.
+
+Usage is;
+
+ pixis_reset
+ pixis_reset altbank
+ pixis_reset altbank wd
+ pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+ pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+
+Examples;
+
+ /* reset to current bank, like "reset" command */
+ pixis_reset
+
+ /* reset board but use the to alternate flash bank */
+ pixis_reset altbank
+
+ /* reset board, use alternate flash bank with watchdog timer enabled*/
+ pixis_reset altbank wd
+
+ /* reset board to alternate bank with frequency changed.
+ * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
+ */
+ pixis-reset altbank cf 40 2.5 10
+
+Valid clock choices are in the 8641 Reference Manuals.
+
+
+Using the Device Tree Source File
+---------------------------------
+To create the DTB (Device Tree Binary) image file,
+use a command similar to this:
+
+ dtc -b 0 -f -I dts -O dtb mpc8544ds.dts > mpc8544ds.dtb
+
+Likely, that .dts file will come from here;
+
+ linux-2.6/arch/powerpc/boot/dts/mpc8544ds.dts
+
+After placing the DTB file in your TFTP disk area,
+you can download that dtb file using a command like:
+
+ tftp 900000 mpc8544ds.dtb
+
+Burn it to flash if you want.
+
+
+Booting Linux
+-------------
+
+Place a linux uImage in the TFTP disk area too.
+
+ tftp 1000000 uImage.8544
+ tftp 900000 mpc8544ds.dtb
+ bootm 1000000 - 900000
+
+Watch your ethact, netdev and bootargs U-Boot environment variables.
+You may want to do something like this too:
+
+ setenv ethact eTSEC3
+ setenv netdev eth1
diff --git a/board/freescale/mpc8569mds/README b/board/freescale/mpc8569mds/README
new file mode 100644
index 0000000..3d12a96
--- /dev/null
+++ b/board/freescale/mpc8569mds/README
@@ -0,0 +1,77 @@
+Overview
+--------
+MPC8569MDS is composed of two boards - PB (Processor Board) and PIB (Platform
+I/O Board). The mpc8569 PowerTM processor is mounted on PB board.
+
+Building U-boot
+-----------
+ make MPC8569MDS_config
+ make
+
+Memory Map
+----------
+0x0000_0000 0x7fff_ffff DDR 2G
+0xa000_0000 0xbfff_ffff PCIe MEM 512MB
+0xe000_0000 0xe00f_ffff CCSRBAR 1M
+0xe280_0000 0xe2ff_ffff PCIe I/O 8M
+0xc000_0000 0xdfff_ffff SRIO 512MB
+0xf000_0000 0xf3ff_ffff SDRAM 64MB
+0xf800_0000 0xf800_7fff BCSR 32KB
+0xf800_8000 0xf800_ffff PIB (CS4) 32KB
+0xf801_0000 0xf801_7fff PIB (CS5) 32KB
+0xfe00_0000 0xffff_ffff Flash 32MB
+
+
+Flashing u-boot Images
+---------------
+
+Use the following commands to program u-boot image into flash:
+
+ => tftp 1000000 u-boot.bin
+ => protect off all
+ => erase fff80000 ffffffff
+ => cp.b 1000000 fff80000 80000
+
+
+Setting the correct MAC addresses
+-----------------------
+The command - "mac", is introduced to set on-board system EEPROM in the format
+defined in board/freescale/common/sys_eeprom.c. we must set all 8 MAC
+addresses for the MPC8569MDS's 8 Ethernet ports and save it by "mac save" when
+we first get the board. The commands are as follows:
+ => mac i NXID /* Set NXID to this EEPROM */
+ => mac e 01 /* Set Errata, this value is not defined by hardware
+ designer, we can set whatever we want */
+ => mac n a0 /* Set Serial Number. This is not defined by hardware
+ designer, we can set whatever we want */
+ => mac date 090512080000 /* Set the date in YYMMDDhhmmss format */
+
+ => mac p 8 /* Set the number of mac ports, it should be 8 */
+ => mac 0 xx:xx:xx:xx:xx:xx /* xx:xx:xx:xx:xx:xx should be the real mac
+ address, you can refer to the value on
+ the sticker of the rear side of the board
+ */
+ .....
+ => mac 7 xx:xx:xx:xx:xx:xx
+ => mac read
+ => mac save
+
+After resetting the board, the ethxaddrs will be filled with the mac addresses
+if such environment variables are blank(never been set before). If the ethxaddr
+has been set but we want to update it, we can use the following commands:
+ => setenv ethxaddr /* x = "none",1,2,3,4,5,6,7 */
+ => save
+ => reset
+
+
+Programming the ucode to flash
+---------------------------------
+MPC8569 doesn't have ROM in QE, so we must upload the microcode(ucode) to QE's
+IRAM so that the QE can work. The ucode binary can be downloaded from
+http://opensource.freescale.com/firmware/, and it must be programmed to
+the address 0xfff0000 in the flash. Otherwise, the QE can't work and uboot
+hangs at "Net:"
+
+
+Please note the above two steps(setting mac addresses and programming ucode) are
+very important to get the board booting up and working properly.
diff --git a/board/freescale/mpc8572ds/README b/board/freescale/mpc8572ds/README
new file mode 100644
index 0000000..57fd2ad
--- /dev/null
+++ b/board/freescale/mpc8572ds/README
@@ -0,0 +1,166 @@
+Overview
+--------
+MPC8572DS is a high-performance computing, evaluation and development platform
+supporting the mpc8572 PowerTM processor.
+
+Building U-boot
+-----------
+ make MPC8572DS_config
+ make
+
+Flash Banks
+-----------
+MPC8572DS board has two flash banks. They are both present on boot, but their
+locations can be swapped using the dip-switch SW9[1:2].
+
+Booting is always from the boot bank at 0xec00_0000.
+
+
+Memory Map
+----------
+
+0xe800_0000 - 0xebff_ffff Alternate bank 64MB
+0xec00_0000 - 0xefff_ffff Boot bank 64MB
+
+0xebf8_0000 - 0xebff_ffff Alternate u-boot address 512KB
+0xeff8_0000 - 0xefff_ffff Boot u-boot address 512KB
+
+
+Flashing Images
+---------------
+
+To place a new u-boot image in the alternate flash bank and then reset with that
+ new image temporarily, use this:
+
+ tftp 1000000 u-boot.bin
+ erase ebf80000 ebffffff
+ cp.b 1000000 ebf80000 80000
+ pixis_reset altbank
+
+
+To program the image in the boot flash bank:
+
+ tftp 1000000 u-boot.bin
+ protect off all
+ erase eff80000 ffffffff
+ cp.b 1000000 eff80000 80000
+
+
+The pixis_reset command
+-----------------------
+The command - "pixis_reset", is introduced to reset mpc8572ds board
+using the FPGA sequencer. When the board restarts, it has the option
+of using either the current or alternate flash bank as the boot
+image, with or without the watchdog timer enabled, and finally with
+or without frequency changes.
+
+Usage is;
+
+ pixis_reset
+ pixis_reset altbank
+ pixis_reset altbank wd
+ pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+ pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+
+Examples:
+
+ /* reset to current bank, like "reset" command */
+ pixis_reset
+
+ /* reset board but use the to alternate flash bank */
+ pixis_reset altbank
+
+
+Using the Device Tree Source File
+---------------------------------
+To create the DTB (Device Tree Binary) image file,
+use a command similar to this:
+
+ dtc -b 0 -f -I dts -O dtb mpc8572ds.dts > mpc8572ds.dtb
+
+Likely, that .dts file will come from here;
+
+ linux-2.6/arch/powerpc/boot/dts/mpc8572ds.dts
+
+
+Booting Linux
+-------------
+
+Place a linux uImage in the TFTP disk area.
+
+ tftp 1000000 uImage.8572
+ tftp c00000 mpc8572ds.dtb
+ bootm 1000000 - c00000
+
+
+Implementing AMP(Asymmetric MultiProcessing)
+-------------
+1. Build kernel image for core0:
+
+ a. $ make 85xx/mpc8572_ds_defconfig
+
+ b. $ make menuconfig
+ - un-select "Processor support"->"Symetric multi-processing support"
+
+ c. $ make uImage
+
+ d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0
+
+2. Build kernel image for core1:
+
+ a. $ make 85xx/mpc8572_ds_defconfig
+
+ b. $ make menuconfig
+ - Un-select "Processor support"->"Symetric multi-processing support"
+ - Select "Advanced setup" -> " Prompt for advanced kernel
+ configuration options"
+ - Select "Set physical address where the kernel is loaded" and
+ set it to 0x20000000, assuming core1 will start from 512MB.
+ - Select "Set custom page offset address"
+ - Select "Set custom kernel base address"
+ - Select "Set maximum low memory"
+ - "Exit" and save the selection.
+
+ c. $ make uImage
+
+ d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1
+
+3. Create dtb for core0:
+
+ $ dtc -I dts -O dtb -f -b 0 arch/powerpc/boot/dts/mpc8572ds_core0.dts > /tftpboot/mpc8572ds_core0.dtb
+
+4. Create dtb for core1:
+
+ $ dtc -I dts -O dtb -f -b 1 arch/powerpc/boot/dts/mpc8572ds_core1.dts > /tftpboot/mpc8572ds_core1.dtb
+
+5. Bring up two cores separately:
+
+ a. Power on the board, under u-boot prompt:
+ => setenv <serverip>
+ => setenv <ipaddr>
+ => setenv bootargs root=/dev/ram rw console=ttyS0,115200
+ b. Bring up core1's kernel first:
+ => setenv bootm_low 0x20000000
+ => setenv bootm_size 0x10000000
+ => tftp 21000000 8572/uImage.core1
+ => tftp 22000000 8572/ramdiskfile
+ => tftp 20c00000 8572/mpc8572ds_core1.dtb
+ => interrupts off
+ => bootm start 21000000 22000000 20c00000
+ => bootm loados
+ => bootm ramdisk
+ => bootm fdt
+ => fdt boardsetup
+ => fdt chosen $initrd_start $initrd_end
+ => bootm prep
+ => cpu 1 release $bootm_low - $fdtaddr -
+ c. Bring up core0's kernel(on the same u-boot console):
+ => setenv bootm_low 0
+ => setenv bootm_size 0x20000000
+ => tftp 1000000 8572/uImage.core0
+ => tftp 2000000 8572/ramdiskfile
+ => tftp c00000 8572/mpc8572ds_core0.dtb
+ => bootm 1000000 2000000 c00000
+
+Please note only core0 will run u-boot, core1 starts kernel directly after
+"cpu release" command is issued.
diff --git a/board/freescale/mpc8610hpcd/README b/board/freescale/mpc8610hpcd/README
new file mode 100644
index 0000000..31a9af3
--- /dev/null
+++ b/board/freescale/mpc8610hpcd/README
@@ -0,0 +1,73 @@
+Freescale MPC8610HPCD board
+===========================
+
+
+Building U-Boot
+---------------
+
+ $ make MPC8610HPCD_config
+ Configuring for MPC8610HPCD board...
+
+ $ make
+
+
+Flashing U-Boot
+---------------
+The flash is 128M starting at 0xF800_0000.
+
+The alternate image is at 0xFBF0_0000
+The boot image is at 0xFFF0_0000.
+
+
+To Flash U-Boot into the booting bank:
+
+ tftp 1000000 u-boot.bin
+ protect off all
+ erase fff00000 +$filesize
+ cp.b 1000000 fff00000 $filesize
+
+
+To Flash U-boot into the alternate bank
+
+ tftp 1000000 u-boot.bin
+ erase fbf00000 +$filesize
+ cp.b 1000000 fbf00000 $filesize
+
+
+pixis_reset command
+-------------------
+A new command, "pixis_reset", is introduced to reset mpc8610hpcd board
+using the FPGA sequencer. When the board restarts, it has the option
+of using either the current or alternate flash bank as the boot
+image, with or without the watchdog timer enabled, and finally with
+or without frequency changes.
+
+Usage is;
+
+ pixis_reset
+ pixis_reset altbank
+ pixis_reset altbank wd
+ pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+ pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+
+Examples;
+
+ /* reset to current bank, like "reset" command */
+ pixis_reset
+
+ /* reset board but use the to alternate flash bank */
+ pixis_reset altbank
+
+ /* reset board, use alternate flash bank with watchdog timer enabled*/
+ pixis_reset altbank wd
+
+ /* reset board to alternate bank with frequency changed.
+ * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
+ */
+ pixis-reset altbank cf 40 2.5 10
+
+
+DIP Switch Settings
+-------------------
+To manually switch the flash banks using the DIP switch
+settings, toggle both SW6:1 and SW6:2.
diff --git a/board/freescale/mpc8641hpcn/README b/board/freescale/mpc8641hpcn/README
new file mode 100644
index 0000000..d8fe0a4
--- /dev/null
+++ b/board/freescale/mpc8641hpcn/README
@@ -0,0 +1,186 @@
+Freescale MPC8641HPCN board
+===========================
+
+Created 05/24/2006 Haiying Wang
+-------------------------------
+
+1. Building U-Boot
+------------------
+The 86xx HPCN code base is known to compile using:
+ Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
+
+ $ make MPC8641HPCN_config
+ Configuring for MPC8641HPCN board...
+
+ $ make
+
+
+2. Switch and Jumper Setting
+----------------------------
+Jumpers:
+ J14 Pins 1-2 (near plcc32 socket)
+
+Switches:
+ SW1(1-5) = 01100 CONFIG_SYS_COREPLL = 01000 :: CORE = 2:1
+ 01100 :: CORE = 2.5:1
+ 10000 :: CORE = 3:1
+ 11100 :: CORE = 3.5:1
+ 10100 :: CORE = 4:1
+ 01110 :: CORE = 4.5:1
+ SW1(6-8) = 001 CONFIG_SYS_SYSCLK = 000 :: SYSCLK = 33MHz
+ 001 :: SYSCLK = 40MHz
+
+ SW2(1-4) = 1100 CONFIG_SYS_CCBPLL = 0010 :: 2X
+ 0100 :: 4X
+ 0110 :: 6X
+ 1000 :: 8X
+ 1010 :: 10X
+ 1100 :: 12X
+ 1110 :: 14X
+ 0000 :: 16X
+ SW2(5-8) = 1110 CONFIG_SYS_BOOTLOC = 1110 :: boot 16-bit localbus
+
+ SW3(1-7) = 0011000 CONFIG_SYS_VID = 0011000 :: VCORE = 1.2V
+ 0100000 :: VCORE = 1.11V
+ SW3(8) = 0 VCC_PLAT = 0 :: VCC_PLAT = 1.2V
+ 1 :: VCC_PLAT = 1.0V
+
+ SW4(1-2) = 11 CONFIG_SYS_HOSTMODE = 11 :: both prots host/root
+ SW4(3-4) = 11 CONFIG_SYS_BOOTSEQ = 11 :: no boot seq
+ SW4(5-8) = 0011 CONFIG_SYS_IOPORT = 0011 :: both PEX
+
+ SW5(1) = 1 CONFIG_SYS_FLASHMAP = 1 :: boot from flash
+ 0 :: boot from PromJet
+ SW5(2) = 1 CONFIG_SYS_FLASHBANK = 1 :: swap upper/lower
+ halves (virtual banks)
+ 0 :: normal
+ SW5(3) = 0 CONFIG_SYS_FLASHWP = 0 :: not protected
+ SW5(4) = 0 CONFIG_SYS_PORTDIV = 1 :: 2:1 for PD4
+ 1:1 for PD6
+ SW5(5-6) = 11 CONFIG_SYS_PIXISOPT = 11 :: s/w determined
+ SW5(7-8) = 11 CONFIG_SYS_LADOPT = 11 :: s/w determined
+
+ SW6(1) = 1 CONFIG_SYS_CPUBOOT = 1 :: no boot holdoff
+ SW6(2) = 1 CONFIG_SYS_BOOTADDR = 1 :: no traslation
+ SW6(3-5) = 000 CONFIG_SYS_REFCLKSEL = 000 :: 100MHZ
+ SW6(6) = 1 CONFIG_SYS_SERROM_ADDR= 1 ::
+ SW6(7) = 1 CONFIG_SYS_MEMDEBUG = 1 ::
+ SW6(8) = 1 CONFIG_SYS_DDRDEBUG = 1 ::
+
+ SW8(1) = 1 ACZ_SYNC = 1 :: 48MHz on TP49
+ SW8(2) = 1 ACB_SYNC = 1 :: THRMTRIP disabled
+ SW8(3) = 1 ACZ_SDOUT = 1 :: p4 mode
+ SW8(4) = 1 ACB_SDOUT = 1 :: PATA freq. = 133MHz
+ SW8(5) = 0 SUSLED = 0 :: SouthBridge Mode
+ SW8(6) = 0 SPREAD = 0 :: REFCLK SSCG Disabled
+ SW8(7) = 1 ACPWR = 1 :: non-battery
+ SW8(8) = 0 CONFIG_SYS_IDWP = 0 :: write enable
+
+
+3. Flash U-Boot
+---------------
+The flash range 0xEF800000 to 0xEFFFFFFF can be divided into 2 halves.
+It is possible to use either half to boot using u-boot. Switch 5 bit 2
+is used for this purpose.
+
+0xEF800000 to 0xEFBFFFFF - 4MB
+0xEFC00000 to 0xEFFFFFFF - 4MB
+When this bit is 0, U-Boot is at 0xEFF00000.
+When this bit is 1, U-Boot is at 0xEFB00000.
+
+Use the above mentioned flash commands to program the other half, and
+use switch 5, bit 2 to alternate between the halves. Note: The booting
+version of U-Boot will always be at 0xEFF00000.
+
+To Flash U-Boot into the booting bank (0xEFC00000 - 0xEFFFFFFF):
+
+ tftp 1000000 u-boot.bin
+ protect off all
+ erase eff00000 +$filesize
+ cp.b 1000000 eff00000 $filesize
+
+or use tftpflash command:
+ run tftpflash
+
+To Flash U-boot into the alternative bank (0xEF800000 - 0xEFBFFFFF):
+
+ tftp 1000000 u-boot.bin
+ erase efb00000 +$filesize
+ cp.b 1000000 efb00000 $filesize
+
+
+4. Memory Map
+-------------
+NOTE: RIO and PCI are mutually exclusive, so they share an address
+
+For 32-bit u-boot, devices are mapped so that the virtual address ==
+the physical address, and the map looks liks this:
+
+ Memory Range Device Size
+ ------------ ------ ----
+ 0x0000_0000 0x7fff_ffff DDR 2G
+ 0x8000_0000 0x9fff_ffff RIO MEM 512M
+ 0x8000_0000 0x9fff_ffff PCI1/PEX1 MEM 512M
+ 0xa000_0000 0xbfff_ffff PCI2/PEX2 MEM 512M
+ 0xffe0_0000 0xffef_ffff CCSR 1M
+ 0xffdf_0000 0xffdf_7fff PIXIS 8K
+ 0xffdf_8000 0xffdf_ffff CF 8K
+ 0xf840_0000 0xf840_3fff Stack space 32K
+ 0xffc0_0000 0xffc0_ffff PCI1/PEX1 IO 64K
+ 0xffc1_0000 0xffc1_ffff PCI2/PEX2 IO 64K
+ 0xef80_0000 0xefff_ffff Flash 8M
+
+For 36-bit-enabled u-boot, the virtual map is the same as for 32-bit.
+However, the physical map is altered to reside in 36-bit space, as follows.
+Addresses are no longer mapped with VA == PA. All accesses from
+software use the VA; the PA is only used for setting up windows
+and mappings. Note that with the exception of PCI MEM and RIO, the low
+ 32 bits are the same as the VA above; only the top 4 bits vary:
+
+ Memory Range Device Size
+ ------------ ------ ----
+ 0x0_0000_0000 0x0_7fff_ffff DDR 2G
+ 0xc_0000_0000 0xc_1fff_ffff RIO MEM 512M
+ 0xc_0000_0000 0xc_1fff_ffff PCI1/PEX1 MEM 512M
+ 0xc_2000_0000 0xc_3fff_ffff PCI2/PEX2 MEM 512M
+ 0xf_ffe0_0000 0xf_ffef_ffff CCSR 1M
+ 0xf_ffdf_0000 0xf_ffdf_7fff PIXIS 8K
+ 0xf_ffdf_8000 0xf_ffdf_ffff CF 8K
+ 0x0_f840_0000 0xf_f840_3fff Stack space 32K
+ 0xf_ffc0_0000 0xf_ffc0_ffff PCI1/PEX1 IO 64K
+ 0xf_ffc1_0000 0xf_ffc1_ffff PCI2/PEX2 IO 64K
+ 0xf_ef80_0000 0xf_efff_ffff Flash 8M
+
+5. pixis_reset command
+--------------------
+A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
+using the FPGA sequencer. When the board restarts, it has the option
+of using either the current or alternate flash bank as the boot
+image, with or without the watchdog timer enabled, and finally with
+or without frequency changes.
+
+Usage is;
+
+ pixis_reset
+ pixis_reset altbank
+ pixis_reset altbank wd
+ pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+ pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+
+Examples;
+
+ /* reset to current bank, like "reset" command */
+ pixis_reset
+
+ /* reset board but use the to alternate flash bank */
+ pixis_reset altbank
+
+ /* reset board, use alternate flash bank with watchdog timer enabled*/
+ pixis_reset altbank wd
+
+ /* reset board to alternate bank with frequency changed.
+ * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
+ */
+ pixis-reset altbank cf 40 2.5 10
+
+Valid clock choices are in the 8641 Reference Manuals.
diff --git a/board/freescale/mx35pdk/README b/board/freescale/mx35pdk/README
new file mode 100644
index 0000000..3d69ed5
--- /dev/null
+++ b/board/freescale/mx35pdk/README
@@ -0,0 +1,188 @@
+Overview
+--------------
+
+mx35pdk (known als as mx35_3stack) is a development board by Freescale.
+It consists of three pluggable board:
+ - CPU module, with CPU, RAM, flash
+ - Personality board, with most interfaces (USB, Network,..)
+ - Debug board with JTAG header.
+
+The board is usually delivered with redboot. This howto explains how to boot
+a linux kernel and how to replace the original bootloader with U-Boot.
+
+The board is delivered with Redboot on the NAND flash. It is possible to
+switch the boot device with the switches SW1-SW2 on the Personality board,
+and with SW5-SW10 on the Debug board.
+
+Delivered Redboot script to start the kernel
+---------------------------------------------------
+
+In redboot the following script is stored:
+
+fis load kernel
+exec -c "noinitrd console=ttymxc0,115200 root=/dev/mtdblock8 rw rootfstype=jffs2 ip=dhcp fec_mac=00:04:9F:00:E7:76"
+
+Kernel is taken from flash. The image is in zImage format.
+
+Booting from NET, rootfs on NFS:
+-----------------------------------
+
+To change the script in redboot:
+
+load -r -b 0x100000 <path_to_zImage>
+exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/armVFP rw ip=dhcp"
+
+If the ip address is not set, you can set it with :
+
+ip_address -l <board_ip/netmask> -h <server_ip>
+
+Linux partitions:
+---------------------------
+
+As default, the board is shipped with these partition tables for NAND
+and for NOR:
+
+Creating 5 MTD partitions on "NAND 2GiB 3,3V 8-bit":
+0x00000000-0x00100000 : "nand.bootloader"
+0x00100000-0x00600000 : "nand.kernel"
+0x00600000-0x06600000 : "nand.rootfs"
+0x06600000-0x06e00000 : "nand.configure"
+0x06e00000-0x80000000 : "nand.userfs"
+
+Creating 6 MTD partitions on "mxc_nor_flash.0":
+0x00000000-0x00080000 : "Bootloader"
+0x00080000-0x00480000 : "nor.Kernel"
+0x00480000-0x02280000 : "nor.userfs"
+0x02280000-0x03e80000 : "nor.rootfs"
+0x01fe0000-0x01fe3000 : "FIS directory"
+0x01fff000-0x04000000 : "Redboot config"
+
+NAND partitions can be recognized enabling in kernel CONFIG_MTD_REDBOOT_PARTS.
+For this board, CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK should be set to 2.
+
+However, the setup in redboot is not correct and does not use the whole flash.
+
+Better solution is to use the kernel parameter mtdparts.
+Here the resulting script to be defined in RedBoot with fconfig:
+
+load -r -b 0x100000 sbabic/mx35pdk/zImage.2.6.37
+exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/arm rw ip=dhcp mtdparts=mxc_nand:1m(boot),5m(linux),96m(root),8m(cfg),1938m(user);physmap-flash.0:512k(b),4m(k),30m(u),28m(r)"
+
+Flashing U-Boot
+--------------------------------
+
+There are two options: the original bootloader in NAND can be replaced with
+u-boot, or u-boot can be stored on the NOR flash without erasing
+the delivered bootloader.
+The boot storage can be select using the switches on the personality board
+(SW1-SW2) and on the DEBUG board (SW4-SW10).
+
+The second option is to be preferred if you have not a JTAG debugger.
+If something goes wrong flashing the bootloader, it is always possible to
+recover the board booting from the other device.
+
+Replacing the bootloader on the NAND
+--------------------------------------
+To replace RedBoot with U-Boot, the easy way is to do this in linux.
+Start the kernel with the suggested options. Make sure to have set the
+mtdparts exactly as described, because this matches the layout on the
+mx35pdk.
+
+You should see in your boot log the following entries for the NAND
+flash:
+
+5 cmdlinepart partitions found on MTD device mxc_nand
+Creating 5 MTD partitions on "mxc_nand":
+0x000000000000-0x000000100000 : "boot"
+0x000000100000-0x000000600000 : "linux"
+0x000000600000-0x000006600000 : "root"
+0x000006600000-0x000006e00000 : "cfg"
+0x000006e00000-0x000080000000 : "user"
+
+You can use the utilities flash_eraseall and nandwrite to put
+u-boot on the NAND. The bootloader is marked as "boot", and 1MB is
+reserved. If everything is correct, this partition is accessed as
+/dev/mtd4. However, check if it is correct with "cat /proc/mtd" and
+get the device node from the partition name:
+
+$ cat /proc/mtd | grep boot
+
+I suggest you try the utilities on a different partition to be sure
+if everything works correctly. If not, and you remove RedBoot, you have to
+reinstall it using the ATK tool as suggested by Freescale, or using a
+JTAG debugger.
+
+I report the versions of the utilities I used (they are provided with ELDK):
+
+-bash-3.2# nandwrite --version
+nandwrite $Revision: 1.32 $
+
+flash_eraseall --version
+flash_eraseall $Revision: 1.22 $
+
+nandwrite reports a warning if the file to be saved is not sector aligned.
+This should have no consequences, but I preferred to pad u-boot.bin
+to get no problem at all.
+$ dd if=/dev/zero of=zeros bs=1 count=74800
+$ cat u-boot.bin zeros > u-boot-padded.bin
+
+To erase the partition:
+$ flash_eraseall /dev/mtd4
+
+Writing u-boot:
+
+$ nandwrite /dev/mtd4 u-boot-padded.bin
+
+Now U-Boot is stored on the booting partition.
+
+To boot from NAND, you have to select the switches as follows:
+
+Personality board
+ SW2 1, 4, 5 on
+ 2, 3, 6, 7, 8 off
+ SW1 all off
+
+Debug Board:
+ SW5 0
+ SW6 0
+ SW7 0
+ SW8 1
+ SW9 1
+ SW10 0
+
+
+Saving U-Boot in the NOR flash
+---------------------------------
+
+The procedure to save in the NOR flash is quite the same as to write into the NAND.
+
+Check the partition for boot in the NOR flash. Setting the mtdparts as reported,
+the boot partition should be /dev/mtd0.
+
+Creating 6 MTD partitions on "mxc_nor_flash.0":
+0x00000000-0x00080000 : "Bootloader"
+0x00080000-0x00480000 : "nor.Kernel"
+0x00480000-0x02280000 : "nor.userfs"
+0x02280000-0x03e80000 : "nor.rootfs"
+0x01fe0000-0x01fe3000 : "FIS directory"
+0x01fff000-0x04000000 : "Redboot config"
+
+To erase the whole partition:
+$ flash_eraseall /dev/mtd0
+
+Writing u-boot:
+dd if=u-boot.bin of=/dev/mtd0
+
+To boot from NOR, you have to select the switches as follows:
+
+Personality board
+ SW2 all off
+ SW1 all off
+
+Debug Board:
+ SW5 0
+ SW6 0
+ SW7 0
+ SW8 1
+ SW9 1
+ SW10 0
diff --git a/board/freescale/mx6qsabrelite/README b/board/freescale/mx6qsabrelite/README
new file mode 100644
index 0000000..6f2f534
--- /dev/null
+++ b/board/freescale/mx6qsabrelite/README
@@ -0,0 +1,72 @@
+U-Boot for the Freescale i.MX6q SabreLite board
+
+This file contains information for the port of U-Boot to the Freescale
+i.MX6q SabreLite board.
+
+1. Boot source, boot from SD card
+---------------------------------
+
+The recent mainline U-Boot for the Freescale i.MX6q SabreLite board supports
+boot from SD card only. However, by default, the SabreLite
+boards boot from the SPI NOR flash. These boards need to be reflashed with
+a small SD card loader to support boot from SD card. This small SD card loader
+will be flashed into the SPI NOR. The board will still boot from SPI NOR, but
+the loader will in turn request the BootROM to load the U-Boot from SD card.
+
+The SD card loader is available from
+
+https://wiki.linaro.org/Boards/MX6QSabreLite
+
+under a open-source 3-clause BSD license.
+
+To update the SPI-NOR on the SabreLite board without the Freescale
+manufacturing tool use the following procedure:
+
+1. Write this SD card loader onto a large SD card using:
+
+ sudo dd if=iMX6DQ_SPI_to_uSDHC3.bin of=/dev/sXx
+
+Note: Replace sXx with the device representing the SD card in your system.
+
+Note: This writes SD card loader at address 0
+
+2. Put this SD card into the slot for the large SD card (SD3 on the bottom of
+the board). Make sure SW1 switch is at position "00", so that it can boot
+from the fuses.
+
+3. Power-up the SabreLite, press 'space' to enter command mode in the U-Boot
+(the default one the board is shipped with, starting from the SPI NOR) and
+enter the following commands:
+
+ MX6Q SABRELITE U-Boot > mmc dev 0
+ MX6Q SABRELITE U-Boot > mmc read 0x10800000 0 200
+ MX6Q SABRELITE U-Boot > sf probe 1
+ MX6Q SABRELITE U-Boot > sf erase 0 0x40000
+ MX6Q SABRELITE U-Boot > sf write 0x10800000 0 0x40000
+
+4. done.
+
+In case you somehow do not succeed with this procedure you will have to use
+the Freescale manufacturing tool in order to reflash the SPI-NOR.
+
+Note: The board now boots from full size SD3 on the bottom of the board. NOT
+ the micro SD4/BOOT slot on the top of the board. I.e. you have to use
+ full size SD cards.
+
+This information is taken from
+
+https://wiki.linaro.org/Boards/MX6QSabreLite
+
+2. Build
+--------
+
+To build U-Boot for the SabreLite board:
+
+ make mx6qsabrelite_config
+ make u-boot.imx
+
+To copy the resulting u-boot.imx to the SD card:
+
+ sudo dd if=u-boot.imx of=/dev/sXx bs=512 seek=2&&sudo sync
+
+Note: Replace sXx with the device representing the SD card in your system.
diff --git a/board/freescale/p1022ds/README b/board/freescale/p1022ds/README
new file mode 100644
index 0000000..04d9197
--- /dev/null
+++ b/board/freescale/p1022ds/README
@@ -0,0 +1,23 @@
+Overview
+--------
+P1022ds is a Low End Dual core platform supporting the P1022 processor
+of QorIQ series. P1022 is an e500 based dual core SOC.
+
+
+Pin Multiplex(hwconfig setting)
+-------------------------------
+Add the environment 'usb2', 'audclk' and 'tdm' to support pin multiplex
+via hwconfig, i.e:
+'setenv hwconfig usb2' to enable USB2 and disable eTsec2
+'setenv hwconfig tdm' to enable TDM and disable Audio
+'setenv hwconfig audclk:12' to enable Audio(codec clock sources is 12MHz)
+ and disable TDM
+'setenv hwconfig 'usb2;tdm' to enable USB2 and TDM, disable eTsec2 and Audio
+'setenv hwconfig 'usb2;audclk:11' to enable USB2 and Audio(codec clock sources
+ is 11MHz), disable eTsec2 and TDM
+
+Warning: TDM and AUDIO can not enable simultaneous !
+and AUDIO codec clock sources only setting as 11MHz or 12MHz !
+'setenv hwconfig 'audclk:12;tdm' --- error !
+'setenv hwconfig 'audclk:11;tdm' --- error !
+'setenv hwconfig 'audclk:10' --- error !
diff --git a/board/freescale/p1023rds/README b/board/freescale/p1023rds/README
new file mode 100644
index 0000000..685f5da
--- /dev/null
+++ b/board/freescale/p1023rds/README
@@ -0,0 +1,101 @@
+Overview
+--------
+The P1023 process includes a performance optimized implementation of the
+QorIQ data Path Acceleration Architecture (DPAA). This architecture
+provides the infrastructure to support simplified sharing of networking
+interfaces and accelerators by multiple CPU cores. P1023 is an e500 based
+dual core SOC.
+
+P1023RDS board is a Low End Dual core platform supporting the P1023
+processor of QorIQ series.
+
+Building U-boot
+---------------
+To build the u-boot for P1023RDS:
+Configure to NOR boot:
+ make P1023RDS_config
+Configure to NAND boot:
+ make P1023RDS_NAND_config
+Build:
+ make
+
+Board Switches
+--------------
+Most switches on the board should not be changed. The most frequent
+user-settable switches on the board are used to configure
+the flash banks.
+
+J4: all open
+
+Default NOR flash boot switch setting:
+ Sw3[1:8]: off on on off on on off off
+ Sw4[1:8]: off off off on off off off off
+ Sw6[1:8]: off on off on off on on off
+ Sw7[1:8]: off on off off on off off off
+ Sw8[1:8]: on off off off off off off off
+
+For NAND flash boot,set
+Sw4[1:4]: off on on on
+
+The default native ethernet setting is for RGMII mode.
+To use SGMII mode, set
+SW8[1:2]: OFF OFF
+SW7[6:7]: ON ON
+
+Memory Map
+----------
+0x0000_0000 0x7fff_ffff DDR 2G Cacheable
+0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
+0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
+0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
+
+0xe000_0000 0xe003_ffff BCSR 256K BCSR
+0xee00_0000 0xefff_ffff NOR flash 32M NOR flash
+0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M
+0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable
+0xffa0_0000 0xffaf_ffff NAND FLASH 1M non-cacheable
+0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
+
+Flashing u-boot Images
+---------------
+To program the image in the boot flash bank:
+NOR flash boot:
+ => tftp 1000000 u-boot.bin
+ => protect off all
+ => erase eff80000 efffffff
+ => cp.b 1000000 eff80000 80000
+
+NAND flash boot:
+ => tftp 1000000 u-boot-nand.bin
+ => nand erase 0 80000
+ => nand write 1000000 0 80000
+
+Firmware ucode location
+---------------------------------
+Microcode(ucode) to FMAN's IRAM is needed to make FMAN Ethernet work.
+u-boot loads ucode FLASH. The location for ucode:
+NOR Flash: 0xfe000000
+NAND Flash: 0x1f00000
+
+Using the Device Tree Source File
+---------------------------------
+To create the DTB (Device Tree Binary) image file,
+use a command similar to this:
+
+ dtc -b 0 -f -I dts -O dtb p1023rds.dts > p1023rds.dtb
+
+Likely, that .dts file will come from here;
+
+ linux-2.6/arch/powerpc/boot/dts/p1023rds.dts
+or
+ make p1023rds.dtb ARCH=powerpc
+in linux-2.6 directory.
+
+Booting Linux
+-------------
+Place a linux uImage in the TFTP disk area.
+
+ tftp 1000000 uImage
+ tftp 2000000 rootfs.ext2.gz.uboot
+ tftp c00000 p1023rds.dtb
+ bootm 1000000 2000000 c00000
diff --git a/board/freescale/p1_p2_rdb/README b/board/freescale/p1_p2_rdb/README
new file mode 100644
index 0000000..cb664a5
--- /dev/null
+++ b/board/freescale/p1_p2_rdb/README
@@ -0,0 +1,145 @@
+Overview
+--------
+P2020RDB is a Low End Dual core platform supporting the P2020 processor
+of QorIQ series. P2020 is an e500 based dual core SOC.
+
+Building U-boot
+-----------
+To build the u-boot for P2020RDB:
+ make P2020RDB_config
+ make
+
+NOR Flash Banks
+-----------
+RDB board for P2020 has two flash banks. They are both present on boot.
+
+Booting by default is always from the boot bank at 0xef00_0000.
+
+Memory Map
+----------
+0xef00_0000 - 0xef7f_ffff Alternate bank 8MB
+0xe800_0000 - 0xefff_ffff Boot bank 8MB
+
+0xef78_0000 - 0xef7f_ffff Alternate u-boot address 512KB
+0xeff8_0000 - 0xefff_ffff Boot u-boot address 512KB
+
+Switch settings to boot from the NOR flash banks
+------------------------------------------------
+SW4[8]=0 default NOR Flash bank
+SW4[8]=1 Alternate NOR Flash bank
+
+Flashing Images
+---------------
+To place a new u-boot image in the alternate flash bank and then boot
+with that new image temporarily, use this:
+ tftp 1000000 u-boot.bin
+ erase ef780000 ef7fffff
+ cp.b 1000000 ef780000 80000
+
+Now to boot from the alternate bank change the SW4[8] from 0 to 1.
+
+To program the image in the boot flash bank:
+ tftp 1000000 u-boot.bin
+ protect off all
+ erase eff80000 ffffffff
+ cp.b 1000000 eff80000 80000
+
+Using the Device Tree Source File
+---------------------------------
+To create the DTB (Device Tree Binary) image file,
+use a command similar to this:
+
+ dtc -b 0 -f -I dts -O dtb p2020rdb.dts > p2020rdb.dtb
+
+Likely, that .dts file will come from here;
+
+ linux-2.6/arch/powerpc/boot/dts/p2020rdb.dts
+
+Booting Linux
+-------------
+Place a linux uImage in the TFTP disk area.
+
+ tftp 1000000 uImage.p2020rdb
+ tftp 2000000 rootfs.ext2.gz.uboot
+ tftp c00000 p2020rdb.dtb
+ bootm 1000000 2000000 c00000
+
+Implementing AMP(Asymmetric MultiProcessing)
+---------------------------------------------
+1. Build kernel image for core0:
+
+ a. $ make 85xx/p1_p2_rdb_defconfig
+
+ b. $ make menuconfig
+ - un-select "Processor support"->
+ "Symetric multi-processing support"
+
+ c. $ make uImage
+
+ d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0
+
+2. Build kernel image for core1:
+
+ a. $ make 85xx/p1_p2_rdb_defconfig
+
+ b. $ make menuconfig
+ - Un-select "Processor support"->
+ "Symetric multi-processing support"
+ - Select "Advanced setup" ->
+ "Prompt for advanced kernel configuration options"
+ - Select
+ "Set physical address where the kernel is loaded"
+ and set it to 0x20000000, assuming core1 will
+ start from 512MB.
+ - Select "Set custom page offset address"
+ - Select "Set custom kernel base address"
+ - Select "Set maximum low memory"
+ - "Exit" and save the selection.
+
+ c. $ make uImage
+
+ d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1
+
+3. Create dtb for core0:
+
+ $ dtc -I dts -O dtb -f -b 0
+ arch/powerpc/boot/dts/p2020rdb_camp_core0.dts >
+ /tftpboot/p2020rdb_camp_core0.dtb
+
+4. Create dtb for core1:
+
+ $ dtc -I dts -O dtb -f -b 1
+ arch/powerpc/boot/dts/p2020rdb_camp_core1.dts >
+ /tftpboot/p2020rdb_camp_core1.dtb
+
+5. Bring up two cores separately:
+
+ a. Power on the board, under u-boot prompt:
+ => setenv <serverip>
+ => setenv <ipaddr>
+ => setenv bootargs root=/dev/ram rw console=ttyS0,115200
+ b. Bring up core1's kernel first:
+ => setenv bootm_low 0x20000000
+ => setenv bootm_size 0x10000000
+ => tftp 21000000 uImage.core1
+ => tftp 22000000 ramdiskfile
+ => tftp 20c00000 p2020rdb_camp_core1.dtb
+ => interrupts off
+ => bootm start 21000000 22000000 20c00000
+ => bootm loados
+ => bootm ramdisk
+ => bootm fdt
+ => fdt boardsetup
+ => fdt chosen $initrd_start $initrd_end
+ => bootm prep
+ => cpu 1 release $bootm_low - $fdtaddr -
+ c. Bring up core0's kernel(on the same u-boot console):
+ => setenv bootm_low 0
+ => setenv bootm_size 0x20000000
+ => tftp 1000000 uImage.core0
+ => tftp 2000000 ramdiskfile
+ => tftp c00000 p2020rdb_camp_core0.dtb
+ => bootm 1000000 2000000 c00000
+
+Please note only core0 will run u-boot, core1 starts kernel directly
+after "cpu release" command is issued.
diff --git a/board/freescale/p1_p2_rdb_pc/README b/board/freescale/p1_p2_rdb_pc/README
new file mode 100644
index 0000000..4437731
--- /dev/null
+++ b/board/freescale/p1_p2_rdb_pc/README
@@ -0,0 +1,46 @@
+Overview
+--------
+P1_P2_RDB_PC represents a set of boards including
+ P1020MSBG-PC
+ P1020RDB-PC
+ P1020UTM-PC
+ P1021RDB-PC
+ P1024RDB
+ P1025RDB
+ P2020RDB-PC
+
+They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC
+has 64-bit DDR. All others have 32-bit DDR.
+
+Key features on these boards include:
+ * DDR3
+ * NOR flash
+ * NAND flash (on RDB's only)
+ * SPI flash (on RDB's only)
+ * SDHC/MMC card slot
+ * VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB)
+ * PCIE slot and mini-PCIE slots
+
+As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM
+is used to store SPD data. In case of absent or corrupted SPD, falling back
+to timing data embedded in the source code will be used. Raw timing data is
+extracted from DDR chip datasheet. Different speeds of DDR are supported with
+this approach. ODT option is forced to fit this set of boards, again because
+they don't have regular DIMMs.
+
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet specification
+for writing timing.
+
+VSC firmware Address is defined by default in config file for eTSEC1.
+
+SD width is based off DIP switch. DIP switch is detected on the
+board by reading i2c bus and setting the appropriate mux values.
+
+Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC have
+pins multiplexing. QE function needs to be disabled to access Nor Flash and
+CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe"
+in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to
+enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below
+
+'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD.
+'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD.
diff --git a/board/freescale/p2041rdb/README b/board/freescale/p2041rdb/README
new file mode 100644
index 0000000..292d0d3
--- /dev/null
+++ b/board/freescale/p2041rdb/README
@@ -0,0 +1,123 @@
+Overview
+=========
+The P2041 Processor combines four Power Architecture processor cores
+with high-performance datapath acceleration architecture(DPAA), CoreNet
+fabric infrastructure, as well as network and peripheral bus interfaces
+required for networking, telecom/datacom, wireless infrastructure, and
+military/aerospace applications.
+
+P2041RDB board is a quad core platform supporting the P2041 processor
+of QorIQ DPAA series.
+
+Boot from NOR flash
+===================
+1. Build image
+ make P2041RDB_config
+ make all
+
+2. Program image
+ => tftp 1000000 u-boot.bin
+ => protect off all
+ => erase eff80000 efffffff
+ => cp.b 1000000 eff80000 80000
+
+3. Program RCW
+ => tftp 1000000 rcw.bin
+ => protect off all
+ => erase e8000000 e801ffff
+ => cp.b 1000000 e8000000 50
+
+4. Program FMAN Firmware ucode
+ => tftp 1000000 ucode.bin
+ => protect off all
+ => erase ef000000 ef0fffff
+ => cp.b 1000000 ef000000 2000
+
+5. Change DIP-switch
+ SW1[1-5] = 10110
+ Note: 1 stands for 'on', 0 stands for 'off'
+
+Boot from SDCard
+===================
+1. Build image
+ make P2041RDB_SDCARD_config
+ make all
+
+2. Generate PBL imge
+ Use PE tool to produce a image used to be programed to
+ SDCard which contains RCW and U-Boot image.
+
+3. Program the PBL image to SDCard
+ => tftp 1000000 pbl_sd.bin
+ => mmcinfo
+ => mmc write 1000000 8 441
+
+4. Program FMAN Firmware ucode
+ => tftp 1000000 ucode.bin
+ => mmc write 1000000 46a 10
+
+5. Change DIP-switch
+ SW1[1-5] = 01100
+ Note: 1 stands for 'on', 0 stands for 'off'
+
+Boot from SPI flash
+===================
+1. Build image
+ make P2041RDB_SPIFLASH_config
+ make all
+
+2. Generate PBL imge
+ Use PE tool to produce a image used to be programed to
+ SPI flash which contains RCW and U-Boot image.
+
+3. Program the PBL image to SPI flash
+ => tftp 1000000 pbl_spi.bin
+ => spi probe 0
+ => sf erase 0 100000
+ => sf write 1000000 0 $filesize
+
+4. Program FMAN Firmware ucode
+ => tftp 1000000 ucode.bin
+ => sf erase 110000 10000
+ => sf write 1000000 110000 $filesize
+
+5. Change DIP-switch
+ SW1[1-5] = 10100
+ Note: 1 stands for 'on', 0 stands for 'off'
+
+CPLD command
+============
+The CPLD is used to control the power sequence and some serdes lane
+mux function.
+
+cpld reset - hard reset to default bank
+cpld reset altbank - reset to alternate bank
+cpld lane_mux <lane> <mux_value> - set multiplexed lane pin
+ lane 6: 0 -> slot1 (Default)
+ 1 -> SGMII
+ lane a: 0 -> slot2 (Default)
+ 1 -> AURORA
+ lane c: 0 -> slot2 (Default)
+ 1 -> SATA0
+ lane d: 0 -> slot2 (Default)
+ 1 -> SATA1
+
+Using the Device Tree Source File
+=================================
+To create the DTB (Device Tree Binary) image file, use a command
+similar to this:
+ dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb
+
+Or use the following command:
+ {linux-2.6}/make p2041rdb.dtb ARCH=powerpc
+
+then the dtb file will be generated under the following directory:
+ {linux-2.6}/arch/powerpc/boot/p2041rdb.dtb
+
+Booting Linux
+=============
+Place a linux uImage in the TFTP disk area.
+ tftp 1000000 uImage
+ tftp 2000000 rootfs.ext2.gz.uboot
+ tftp 3000000 p2041rdb.dtb
+ bootm 1000000 2000000 3000000
diff --git a/board/freescale/p3060qds/README b/board/freescale/p3060qds/README
new file mode 100644
index 0000000..ec62798
--- /dev/null
+++ b/board/freescale/p3060qds/README
@@ -0,0 +1,110 @@
+Overview
+=========
+The P3060QDS is a Freescale reference board that hosts the six-core P3060 SOC.
+
+The P3060 Processor combines six e500mc Power Architecture processor
+cores(1.2GHz) with high-performance datapath acceleration
+architecture(DPAA), CoreNet fabric infrastructure, as well as network
+and peripheral bus interfaces required for networking, telecom/datacom,
+wireless infrastructure, and military/aerospace applications.
+
+
+P3060QDS Board Specifications:
+==============================
+Memory subsystem:
+ * 2G Bytes UDIMM DDR3(64bit bus) with ECC on
+ * 128M Bytes NOR flash single-chip memory
+ * 16M Bytes SPI flash
+ * 8K Bytes AT24C64 I2C EEPROM for RCW
+
+Ethernet(Default SERDES 0x19):
+ * FM1-dTSEC1: connected to RGMII PHY1 (Vitesse VSC8641 on board,Bottom of dual RJ45)
+ * FM1-dTSEC2: connected to RGMII PHY2 (Vitesse VSC8641 on board,Top of dual RJ45)
+ * FM1-dTSEC3: connected to SGMII PHY (Vitesse VSC8234 port1 in slot1)
+ * FM1-dTSEC4: connected to SGMII PHY (Vitesse VSC8234 port3 in slot1)
+ * FM2-dTSEC1: connected to SGMII PHY (Vitesse VSC8234 port0 in slot2)
+ * FM2-dTSEC2: connected to SGMII PHY (Vitesse VSC8234 port2 in slot2)
+ * FM2-dTSEC3: connected to SGMII PHY (Vitesse VSC8234 port0 in slot1)
+ * FM2-dTSEC4: connected to SGMII PHY (Vitesse VSC8234 port2 in slot1)
+
+PCIe:
+ * PCIe1: Lanes A, B, C and D of Bank1 are connected to one x4 PCIe SLOT4
+ * PCIe2: Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT3
+
+RapidIO:
+ * sRIO1: Lanes E, F, G and H of Bank1 are connected to sRIO1 (SLOT3)
+ * sRIO2: Lanes A, B, C and D of Bank1 are connected to sRIO2 (SLOT4)
+
+USB:
+ * USB1: connected via an external ULPI PHY SMC3315 to a TYPE-A interface
+ * USB2: connected via an external ULPI PHY SMC3315 to a TYPE-AB interface
+
+I2C:
+ * I2C1_CH0: EEPROM AT24C64(0x50) RCW, AT24C02(0x51) DDR SPD,
+ AT24C02(0x53) DDR SPD, AT24C02(0x57) SystemID, RTC DS3232(0x68)
+ * I2C1_CH1: 1588 RiserCard(0x55), HSLB Testport, TempMon
+ ADT7461(0x4C), SerDesMux DS64MB201(0x51/59/5C/5D)
+ * I2C1_CH2: VDD/GVDD/GIDD ZL6100 (0x21/0x22/0x23/0x24/0x40)
+ * I2C1_CH3: OCM CFG AT24C02(0x55), OCM IPL AT24C64(0x56)
+ * I2C1_CH4: PCIe SLOT1
+ * I2C1_CH5: PCIe SLOT2
+ * I2C1_CH6: PCIe SLOT3
+ * I2C1_CH7: PCIe SLOT4
+ * I2C2: NULL
+ * I2C3: NULL
+
+UART:
+ * Supports two UARTs up to 115200 bps for console
+
+
+Boot from NOR flash
+===================
+1. Build image
+ export ARCH=powerpc
+ export CROSS_COMPILE=/your_path/gcc-4.5.xx-eglibc-2.11.xx/powerpc-linux-gnu/bin/powerpc-linux-gnu-
+ make P3060QDS_config
+ make
+
+2. Program image
+ => tftp 1000000 u-boot.bin
+ => protect off all
+ => erase eff80000 efffffff
+ => cp.b 1000000 eff80000 80000
+
+3. Program RCW
+ => tftp 1000000 rcw.bin
+ => protect off all
+ => erase e8000000 e801ffff
+ => cp.b 1000000 e8000000 50
+
+4. Program FMAN Firmware ucode
+ => tftp 1000000 ucode.bin
+ => protect off all
+ => erase ef000000 ef0fffff
+ => cp.b 1000000 ef000000 2000
+
+5. Change DIP-switch
+ RCW Location: SW1[1-5] = 01101 (eLBC 16bit NOR flash)
+ Note: 1 stands for 'on', 0 stands for 'off'
+
+
+Using the Device Tree Source File
+=================================
+To create the DTB (Device Tree Binary) image file, use a command
+similar to this:
+ dtc -O dtb -b 0 -p 1024 p3060qds.dts > p3060qds.dtb
+
+Or use the following command:
+ {linux-2.6}/make p3060qds.dtb ARCH=powerpc
+
+then the dtb file will be generated under the following directory:
+ {linux-2.6}/arch/powerpc/boot/p3060qds.dtb
+
+
+Booting Linux
+=============
+Place a linux uImage in the TFTP disk area.
+ tftp 1000000 uImage
+ tftp 2000000 rootfs.ext2.gz.uboot
+ tftp 3000000 p3060rdb.dtb
+ bootm 1000000 2000000 3000000