diff options
Diffstat (limited to 'board/karo')
| -rw-r--r-- | board/karo/tk71/Kconfig | 12 | ||||
| -rw-r--r-- | board/karo/tk71/MAINTAINERS | 6 | ||||
| -rw-r--r-- | board/karo/tk71/Makefile | 9 | ||||
| -rw-r--r-- | board/karo/tk71/kwbimage.cfg | 158 | ||||
| -rw-r--r-- | board/karo/tk71/tk71.c | 150 | ||||
| -rw-r--r-- | board/karo/tx25/Kconfig | 15 | ||||
| -rw-r--r-- | board/karo/tx25/MAINTAINERS | 6 | ||||
| -rw-r--r-- | board/karo/tx25/Makefile | 11 | ||||
| -rw-r--r-- | board/karo/tx25/lowlevel_init.S | 98 | ||||
| -rw-r--r-- | board/karo/tx25/tx25.c | 210 |
10 files changed, 0 insertions, 675 deletions
diff --git a/board/karo/tk71/Kconfig b/board/karo/tk71/Kconfig deleted file mode 100644 index 7b3d548..0000000 --- a/board/karo/tk71/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_TK71 - -config SYS_BOARD - default "tk71" - -config SYS_VENDOR - default "karo" - -config SYS_CONFIG_NAME - default "tk71" - -endif diff --git a/board/karo/tk71/MAINTAINERS b/board/karo/tk71/MAINTAINERS deleted file mode 100644 index ac85d6b..0000000 --- a/board/karo/tk71/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -TK71 BOARD -#M: - -S: Maintained -F: board/karo/tk71/ -F: include/configs/tk71.h -F: configs/tk71_defconfig diff --git a/board/karo/tk71/Makefile b/board/karo/tk71/Makefile deleted file mode 100644 index 0e0df77..0000000 --- a/board/karo/tk71/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright (C) 2012 Marek Vasut <marex@denx.de> -# on behalf of DENX Software Engineering GmbH -# -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := tk71.o diff --git a/board/karo/tk71/kwbimage.cfg b/board/karo/tk71/kwbimage.cfg deleted file mode 100644 index a32e27c..0000000 --- a/board/karo/tk71/kwbimage.cfg +++ /dev/null @@ -1,158 +0,0 @@ -# -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com> -# -# adopted to TK71 by -# Nils Faerber <nils.faerber@kernelconcepts.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM nand -NAND_ECC_MODE default -NAND_PAGE_SIZE 0x0800 - -# SOC registers configuration using bootrom header extension -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed - -# Configure RGMII-0 interface pad voltage to 1.8V -DATA 0xFFD100e0 0x1b1b1b9b - -#Dram initalization for SINGLE x16 CL=5 @ 400MHz -DATA 0xFFD01400 0x43000c30 # DDR Configuration register -# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) -# bit23-14: zero -# bit24: 1= enable exit self refresh mode on DDR access -# bit25: 1 required -# bit29-26: zero -# bit31-30: 01 - -DATA 0xFFD01404 0x36543000 # DDR Controller Control Low -# bit 4: 0=addr/cmd in smame cycle -# bit 5: 0=clk is driven during self refresh, we don't care for APX -# bit 6: 0=use recommended falling edge of clk for addr/cmd -# bit14: 0=input buffer always powered up -# bit18: 1=cpu lock transaction enabled -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 -# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM -# bit30-28: 3 required -# bit31: 0=no additional STARTBURST delay - -DATA 0xFFD01408 0x1101355b # DDR Timing (Low) (active cycles value +1) -# bit3-0: TRAS lsbs -# bit7-4: TRCD -# bit11- 8: TRP -# bit15-12: TWR -# bit19-16: TWTR -# bit20: TRAS msb -# bit23-21: 0x0 -# bit27-24: TRRD -# bit31-28: TRTP - -DATA 0xFFD0140C 0x00000034 # DDR Timing (High) -# bit6-0: TRFC -# bit8-7: TR2R -# bit10-9: TR2W -# bit12-11: TW2W -# bit31-13: zero required - -DATA 0xFFD01410 0x00000000 # DDR Address Control -# bit1-0: 01, Cs0width=x16 -# bit3-2: 10, Cs0size=512Mb -# bit5-4: 01, Cs1width=x16 -# bit7-6: 10, Cs1size=512Mb -# bit9-8: 00, Cs2width=nonexistent -# bit11-10: 00, Cs2size =nonexistent -# bit13-12: 00, Cs3width=nonexistent -# bit15-14: 00, Cs3size =nonexistent -# bit16: 0, Cs0AddrSel -# bit17: 0, Cs1AddrSel -# bit18: 0, Cs2AddrSel -# bit19: 0, Cs3AddrSel -# bit31-20: 0 required - -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit0: 0, OpenPage enabled -# bit31-1: 0 required - -DATA 0xFFD01418 0x00000000 # DDR Operation -# bit3-0: 0x0, DDR cmd -# bit31-4: 0 required - -DATA 0xFFD0141C 0x00000652 # DDR Mode -# bit2-0: 2, BurstLen=2 required -# bit3: 0, BurstType=0 required -# bit6-4: 4, CL=5 -# bit7: 0, TestMode=0 normal -# bit8: 0, DLL reset=0 normal -# bit11-9: 6, auto-precharge write recovery ???????????? -# bit12: 0, PD must be zero -# bit31-13: 0 required - -DATA 0xFFD01420 0x00000042 # DDR Extended Mode -# bit0: 0, DDR DLL enabled -# bit1: 0, DDR drive strenght normal -# bit2: 0, DDR ODT control lsd (disabled) -# bit5-3: 000, required -# bit6: 1, DDR ODT control msb, (disabled) -# bit9-7: 000, required -# bit10: 0, differential DQS enabled -# bit11: 0, required -# bit12: 0, DDR output buffer enabled -# bit31-13: 0 required - -DATA 0xFFD01424 0x0000F17F # DDR Controller Control High -# bit2-0: 111, required -# bit3 : 1 , MBUS Burst Chop disabled -# bit6-4: 111, required -# bit7 : 0 -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz -# bit9 : 0 , no half clock cycle addition to dataout -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh -# bit15-12: 1111 required -# bit31-16: 0 required - -DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) -DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) - -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size -# bit0: 1, Window enabled -# bit1: 0, Write Protect disabled -# bit3-2: 00, CS0 hit selected -# bit23-4: ones, required -# bit31-24: 0x0F, Size (i.e. 256MB) - -DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 256Mb -DATA 0xFFD0150C 0x00000000 # CS[1]n Size 256Mb Window enabled for CS1 - -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled - -DATA 0xFFD01494 0x00110000 # DDR ODT Control (Low) -# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1 -# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0 -# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1. -# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0. -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above -# bit3-2: 01, ODT1 active NEVER! -# bit31-4: zero, required - -DATA 0xFFD0149C 0x0000F80F # CPU ODT Control -# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3 -# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm -# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm -# bit14: 1, M_STARTBURST_IN ODT: Enabled -# bit15: 1, DDR IO ODT Unit: Use ODT block -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -#bit0=1, enable DDR init upon this register write - -# End of Header extension -DATA 0x0 0x0 diff --git a/board/karo/tk71/tk71.c b/board/karo/tk71/tk71.c deleted file mode 100644 index 35546d2..0000000 --- a/board/karo/tk71/tk71.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (C) 2012 Marek Vasut <marex@denx.de> - * on behalf of DENX Software Engineering GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <miiphy.h> -#include <asm/arch/cpu.h> -#include <asm/arch/soc.h> -#include <asm/arch/mpp.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define TK71_OE_LOW (~0) -#define TK71_OE_HIGH (~0) -#define TK71_OE_VAL_LOW (0) -#define TK71_OE_VAL_HIGH (0) - -int board_early_init_f(void) -{ - /* - * default gpio configuration - * There are maximum 64 gpios controlled through 2 sets of registers - * the below configuration configures mainly initial LED status - */ - mvebu_config_gpio(TK71_OE_VAL_LOW, - TK71_OE_VAL_HIGH, - TK71_OE_LOW, TK71_OE_HIGH); - - /* Multi-Purpose Pins Functionality configuration */ - static const u32 kwmpp_config[] = { - MPP0_NF_IO2, - MPP1_NF_IO3, - MPP2_NF_IO4, - MPP3_NF_IO5, - MPP4_NF_IO6, - MPP5_NF_IO7, - MPP6_SYSRST_OUTn, - MPP7_GPO, - MPP8_TW_SDA, - MPP9_TW_SCK, - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP12_SD_CLK, - MPP13_SD_CMD, - MPP14_SD_D0, - MPP15_SD_D1, - MPP16_SD_D2, - MPP17_SD_D3, - MPP18_NF_IO0, - MPP19_NF_IO1, - MPP20_GE1_0, - MPP21_GE1_1, - MPP22_GE1_2, - MPP23_GE1_3, - MPP24_GE1_4, - MPP25_GE1_5, - MPP26_GE1_6, - MPP27_GE1_7, - MPP28_GPIO, - MPP29_GPIO, - MPP30_GE1_10, - MPP31_GE1_11, - MPP32_GE1_12, - MPP33_GE1_13, - MPP34_GPIO, - MPP35_GPIO, - MPP36_GPIO, - MPP37_GPIO, - MPP38_GPIO, - MPP39_GPIO, - MPP40_GPIO, - MPP41_GPIO, - MPP42_GPIO, - MPP43_GPIO, - MPP44_GPIO, - MPP45_GPIO, - MPP46_GPIO, - MPP47_GPIO, - MPP48_GPIO, - MPP49_GPIO, - 0 - }; - kirkwood_mpp_conf(kwmpp_config, NULL); - - return 0; -} - -int board_init(void) -{ - /* - * arch number of board - */ - gd->bd->bi_arch_number = CONFIG_MACH_TYPE; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; - - return 0; -} - -#ifdef CONFIG_CMD_NET - -#define MV88E1116_MAC_CTRL2_REG 21 -#define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) - -static void mv_phy_88e1118_init(char *name) -{ - u16 reg; - u16 devadr; - - if (miiphy_set_current_dev(name)) - return; - - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { - printf("Err..%s could not read PHY dev address\n", - __func__); - return; - } - - /* - * Enable RGMII delay on Tx and Rx for CPU port - * Ref: sec 4.7.2 of chip datasheet - */ - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); - miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, ®); - reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg); - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); - - /* reset the phy */ - miiphy_reset(name, devadr); - - printf("88E1118 Initialized on %s\n", name); -} - -/* Configure and enable Switch and PHY */ -void reset_phy(void) -{ - /* configure and initialize PHY */ - mv_phy_88e1118_init("egiga0"); - -} -#endif diff --git a/board/karo/tx25/Kconfig b/board/karo/tx25/Kconfig deleted file mode 100644 index 42746c1..0000000 --- a/board/karo/tx25/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_TX25 - -config SYS_BOARD - default "tx25" - -config SYS_VENDOR - default "karo" - -config SYS_SOC - default "mx25" - -config SYS_CONFIG_NAME - default "tx25" - -endif diff --git a/board/karo/tx25/MAINTAINERS b/board/karo/tx25/MAINTAINERS deleted file mode 100644 index 2defe34..0000000 --- a/board/karo/tx25/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -TX25 BOARD -M: John Rigby <jcrigby@gmail.com> -S: Maintained -F: board/karo/tx25/ -F: include/configs/tx25.h -F: configs/tx25_defconfig diff --git a/board/karo/tx25/Makefile b/board/karo/tx25/Makefile deleted file mode 100644 index add5dd3..0000000 --- a/board/karo/tx25/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2009 DENX Software Engineering -# Author: John Rigby <jcrigby@gmail.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_SPL_BUILD -obj-y += lowlevel_init.o -endif -obj-y += tx25.o diff --git a/board/karo/tx25/lowlevel_init.S b/board/karo/tx25/lowlevel_init.S deleted file mode 100644 index 11b80b4..0000000 --- a/board/karo/tx25/lowlevel_init.S +++ /dev/null @@ -1,98 +0,0 @@ -/* - * (C) Copyright 2009 DENX Software Engineering - * Author: John Rigby <jrigby@gmail.com> - * - * Based on U-Boot and RedBoot sources for several different i.mx - * platforms. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm/macro.h> -#include <asm/arch/macro.h> - -.macro init_clocks - /* - * clocks - * - * first enable CLKO debug output - * 0x40000000 enables the debug CLKO signal - * 0x05000000 sets CLKO divider to 6 - * 0x00600000 makes CLKO parent clk the USB clk - */ - write32 0x53f80064, 0x45600000 - - /* CCTL: ARM = 399 MHz, AHB = 133 MHz */ - write32 0x53f80008, 0x20034000 - - /* - * PCDR2: NFC = 33.25 MHz - * This is required for the NAND Flash of this board, which is a Samsung - * K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with - * the NFC driver in symmetric (i.e. one-cycle) mode. - */ - write32 0x53f80020, 0x01010103 - - /* - * enable all implemented clocks in all three - * clock control registers - */ - write32 0x53f8000c, 0x1fffffff - write32 0x53f80010, 0xffffffff - write32 0x53f80014, 0xfdfff -.endm - -.macro init_ddrtype - /* - * ddr_type is 3.3v SDRAM - */ - write32 0x43fac454, 0x800 -.endm - -/* - * sdram controller init - */ -.macro init_sdram_bank bankaddr, ctl, cfg - ldr r0, =0xb8001000 - ldr r2, =\bankaddr - /* - * reset SDRAM controller - * then wait for initialization to complete - */ - ldr r1, =(1 << 1) - str r1, [r0, #0x10] -1: ldr r3, [r0, #0x10] - tst r3, #(1 << 31) - beq 1b - - ldr r1, =0x95728 - str r1, [r0, #\cfg] /* config */ - - ldr r1, =0x92116480 /* control | precharge */ - str r1, [r0, #\ctl] /* write command to controller */ - str r1, [r2, #0x400] /* command encoded in address */ - - ldr r1, =0xa2116480 /* auto refresh */ - str r1, [r0, #\ctl] - ldrb r3, [r2] /* read dram twice to auto refresh */ - ldrb r3, [r2] - - ldr r1, =0xb2116480 /* control | load mode */ - str r1, [r0, #\ctl] /* write command to controller */ - strb r1, [r2, #0x33] /* command encoded in address */ - - ldr r1, =0x82116480 /* control | normal (0)*/ - str r1, [r0, #\ctl] /* write command to controller */ -.endm - -.globl lowlevel_init -lowlevel_init: - init_aips - init_max - init_m3if - init_clocks - - init_sdram_bank 0x80000000, 0x0, 0x4 - - init_sdram_bank 0x90000000, 0x8, 0xc - mov pc, lr diff --git a/board/karo/tx25/tx25.c b/board/karo/tx25/tx25.c deleted file mode 100644 index 4d1a0ec..0000000 --- a/board/karo/tx25/tx25.c +++ /dev/null @@ -1,210 +0,0 @@ -/* - * (C) Copyright 2009 DENX Software Engineering - * Author: John Rigby <jrigby@gmail.com> - * - * Based on imx27lite.c: - * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net> - * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com> - * And: - * RedBoot tx25_misc.c Copyright (C) 2009 Red Hat - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux-mx25.h> -#include <asm/gpio.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_SPL_BUILD -void board_init_f(ulong bootflag) -{ - /* - * copy ourselves from where we are running to where we were - * linked at. Use ulong pointers as all addresses involved - * are 4-byte-aligned. - */ - ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst; - asm volatile ("ldr %0, =_start" : "=r"(start_ptr)); - asm volatile ("ldr %0, =_end" : "=r"(end_ptr)); - asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr)); - asm volatile ("adr %0, board_init_f" : "=r"(run_ptr)); - for (dst = start_ptr; dst < end_ptr; dst++) - *dst = *(dst+(run_ptr-link_ptr)); - /* - * branch to nand_boot's link-time address. - */ - asm volatile("ldr pc, =nand_boot"); -} -#endif - -#ifdef CONFIG_FEC_MXC -/* - * FIXME: need to revisit this - * The original code enabled PUE and 100-k pull-down without PKE, so the right - * value here is likely: - * 0 for no pull - * or: - * PAD_CTL_PUS_100K_DOWN for 100-k pull-down - */ -#define FEC_OUT_PAD_CTRL 0 - -#define GPIO_FEC_RESET_B IMX_GPIO_NR(4, 7) -#define GPIO_FEC_ENABLE_B IMX_GPIO_NR(4, 9) - -void tx25_fec_init(void) -{ - static const iomux_v3_cfg_t fec_pads[] = { - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX25_PAD_FEC_RX_DV__FEC_RX_DV, - MX25_PAD_FEC_RDATA0__FEC_RDATA0, - NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL), - MX25_PAD_FEC_MDIO__FEC_MDIO, - MX25_PAD_FEC_RDATA1__FEC_RDATA1, - NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL), - - NEW_PAD_CTRL(MX25_PAD_D13__GPIO_4_7, 0), /* FEC_RESET_B */ - NEW_PAD_CTRL(MX25_PAD_D11__GPIO_4_9, 0), /* FEC_ENABLE_B */ - }; - - static const iomux_v3_cfg_t fec_cfg_pads[] = { - MX25_PAD_FEC_RDATA0__GPIO_3_10, - MX25_PAD_FEC_RDATA1__GPIO_3_11, - MX25_PAD_FEC_RX_DV__GPIO_3_12, - }; - - debug("tx25_fec_init\n"); - imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); - - /* drop PHY power and assert reset (low) */ - gpio_direction_output(GPIO_FEC_RESET_B, 0); - gpio_direction_output(GPIO_FEC_ENABLE_B, 0); - - mdelay(5); - - debug("resetting phy\n"); - - /* turn on PHY power leaving reset asserted */ - gpio_set_value(GPIO_FEC_ENABLE_B, 1); - - mdelay(10); - - /* - * Setup some strapping pins that are latched by the PHY - * as reset goes high. - * - * Set PHY mode to 111 - * mode0 comes from FEC_RDATA0 which is GPIO 3_10 in mux mode 5 - * mode1 comes from FEC_RDATA1 which is GPIO 3_11 in mux mode 5 - * mode2 is tied high so nothing to do - * - * Turn on RMII mode - * RMII mode is selected by FEC_RX_DV which is GPIO 3_12 in mux mode - */ - /* - * set each mux mode to gpio mode - */ - imx_iomux_v3_setup_multiple_pads(fec_cfg_pads, - ARRAY_SIZE(fec_cfg_pads)); - - /* - * set each to 1 and make each an output - */ - gpio_direction_output(IMX_GPIO_NR(3, 10), 1); - gpio_direction_output(IMX_GPIO_NR(3, 11), 1); - gpio_direction_output(IMX_GPIO_NR(3, 12), 1); - - mdelay(22); /* this value came from RedBoot */ - - /* - * deassert PHY reset - */ - gpio_set_value(GPIO_FEC_RESET_B, 1); - - mdelay(5); - - /* - * set FEC pins back - */ - imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); -} -#else -#define tx25_fec_init() -#endif - -#ifdef CONFIG_MXC_UART -/* - * Set up input pins with hysteresis and 100-k pull-ups - */ -#define UART1_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP) -/* - * FIXME: need to revisit this - * The original code enabled PUE and 100-k pull-down without PKE, so the right - * value here is likely: - * 0 for no pull - * or: - * PAD_CTL_PUS_100K_DOWN for 100-k pull-down - */ -#define UART1_OUT_PAD_CTRL 0 - -static void tx25_uart1_init(void) -{ - static const iomux_v3_cfg_t uart1_pads[] = { - NEW_PAD_CTRL(MX25_PAD_UART1_RXD__UART1_RXD, UART1_IN_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_UART1_TXD__UART1_TXD, UART1_OUT_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_UART1_RTS__UART1_RTS, UART1_OUT_PAD_CTRL), - NEW_PAD_CTRL(MX25_PAD_UART1_CTS__UART1_CTS, UART1_IN_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} -#else -#define tx25_uart1_init() -#endif - -int board_init() -{ - tx25_uart1_init(); - - /* board id for linux */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - return 0; -} - -int board_late_init(void) -{ - tx25_fec_init(); - return 0; -} - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); -#if CONFIG_NR_DRAM_BANKS > 1 - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, - PHYS_SDRAM_2_SIZE); -#else - -#endif -} - -int checkboard(void) -{ - printf("KARO TX25\n"); - return 0; -} |