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-rw-r--r--board/matrix_vision/mergerbox/README59
-rw-r--r--board/matrix_vision/mvbc_p/README.mvbc_p73
-rw-r--r--board/matrix_vision/mvblm7/README.mvblm784
-rw-r--r--board/matrix_vision/mvsmr/README.mvsmr55
4 files changed, 271 insertions, 0 deletions
diff --git a/board/matrix_vision/mergerbox/README b/board/matrix_vision/mergerbox/README
new file mode 100644
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--- /dev/null
+++ b/board/matrix_vision/mergerbox/README
@@ -0,0 +1,59 @@
+Matrix Vision MergerBox
+-----------------------
+
+1. Board Description
+
+ The MergerBox is a 120x160mm single board computing platform
+ for 3D Full-HD digital video processing.
+
+ Power Supply is 10-32VDC.
+
+2 System Components
+
+2.1 CPU
+ Freescale MPC8377 CPU running at 800MHz core and 333MHz csb.
+ 256 MByte DDR-II memory @ 333MHz data rate.
+ 64 MByte Nor Flash on local bus.
+ 1 GByte Nand Flash on FCM.
+ 1 Vitesse VSC8601 RGMII ethernet Phys.
+ 1 USB host controller over ULPI I/F with 4-Port hub.
+ 2 serial ports. Console running on ttyS0 @ 115200 8N1.
+ 1 mPCIe expansion slot (PCIe x1 + USB) used for Wifi/Bt.
+ 2 PCIe x1 busses on local mPCIe and cutom expansion connector.
+ 2 SATA host ports.
+ System configuration (HRCW) is taken from I2C EEPROM.
+
+2.2 Graphics
+ SM107 emebedded video controller driving a 5" 800x480 TFT panel.
+ Connected over 32-Bit/66MHz PCI utilizing 4 MByte embedded memory.
+
+2.3 FPGA
+ Altera Cyclone-IV EP4C115 with several PCI DMA engines.
+ Connects to 7x Gennum 3G-SDI transceivers as video interconnect
+ as well as a HDMI v1.4 compliant output for 3D monitoring.
+ Utilizes two more DDR-II controllers providing 256MB memory.
+
+2.4 I2C
+ Bus1:
+ AD7418 @ 0x50 for voltage/temp. monitoring.
+ SX8650 @ 0x90 touch controller for HMI.
+ EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics.
+ Bus2:
+ mPCIe SMBus
+ SiI9022A @ 0x72/0xC0 HDMI transmitter.
+ TCA6416A @ 0x40 + 0x42 16-Bit I/O expander.
+ LMH1983 @ 0xCA video PLL.
+ DS1338C @ 0xD0 real-time clock with embedded crystal.
+ 9FG104 @ 0xDC 4x 100MHz LVDS SerDes reference clock.
+
+3 Flash layout.
+
+ reset vector is 0x00000100, i.e. low boot.
+
+ 00000000 u-boot binary.
+ 00100000 FPGA raw bit file.
+ 00300000 FIT image holding kernel, dtb and rescue squashfs.
+ 03d00000 u-boot environment.
+ 03e00000 splash image
+
+ mtd partitions are propagated to linux kernel via device tree blob.
diff --git a/board/matrix_vision/mvbc_p/README.mvbc_p b/board/matrix_vision/mvbc_p/README.mvbc_p
new file mode 100644
index 0000000..a691137
--- /dev/null
+++ b/board/matrix_vision/mvbc_p/README.mvbc_p
@@ -0,0 +1,73 @@
+Matrix Vision mvBlueCOUGAR-P (mvBC-P)
+-------------------------------------
+
+1. Board Description
+
+ The mvBC-P is a 70x40x40mm multi board gigabit ethernet network camera
+ with main focus on GigEVision protocol in combination with local image
+ preprocessing.
+
+ Power Supply is either VDC 48V or Pover over Ethernet (PoE).
+
+2 System Components
+
+2.1 CPU
+ Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB.
+ 64MB SDRAM @ 133MHz.
+ 8 MByte Nor Flash on local bus.
+ 1 serial ports. Console running on ttyS0 @ 115200 8N1.
+
+2.2 PCI
+ PCI clock fixed at 66MHz. Arbitration inside FPGA.
+ Intel GD82541ER network MAC/PHY and FPGA connected.
+
+2.3 FPGA
+ Altera Cyclone-II EP2C8 with PCI DMA engine.
+ Connects to Matrix Vision specific CCD/CMOS sensor interface.
+ Utilizes 64MB Nand Flash.
+
+2.3.1 I/O @ FPGA
+ 2 Outputs : photo coupler
+ 2 Inputs : photo coupler
+
+2.4 I2C
+ LM75 @ 0x90 for temperature monitoring.
+ EEPROM @ 0xA0 for vendor specifics.
+ image sensor interface (slave addresses depend on sensor)
+
+3 Flash layout.
+
+ reset vector is 0x00000100, i.e. "LOWBOOT".
+
+ FF800000 u-boot
+ FF840000 u-boot script image
+ FF850000 redundant u-boot script image
+ FF860000 FPGA raw bit file
+ FF8A0000 tbd.
+ FF900000 root FS
+ FFC00000 kernel
+ FFFC0000 device tree blob
+ FFFD0000 redundant device tree blob
+ FFFE0000 environment
+ FFFF0000 redundant environment
+
+ mtd partitions are propagated to linux kernel via device tree blob.
+
+4 Booting
+
+ On startup the bootscript @ FF840000 is executed. This script can be
+ exchanged easily. Default boot mode is "boot from flash", i.e. system
+ works stand-alone.
+
+ This behaviour depends on some environment variables :
+
+ "netboot" : yes ->try dhcp/bootp and boot from network.
+ A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
+ DHCP server configuration, e.g. to provide different images to
+ different devices.
+
+ During netboot the system tries to get 3 image files:
+ 1. Kernel - name + data is given during BOOTP.
+ 2. Initrd - name is stored in "initrd_name"
+ 3. device tree blob - name is stored in "dtb_name"
+ Fallback files are the flash versions.
diff --git a/board/matrix_vision/mvblm7/README.mvblm7 b/board/matrix_vision/mvblm7/README.mvblm7
new file mode 100644
index 0000000..a0686f7
--- /dev/null
+++ b/board/matrix_vision/mvblm7/README.mvblm7
@@ -0,0 +1,84 @@
+Matrix Vision mvBlueLYNX-M7 (mvBL-M7)
+-------------------------------------
+
+1. Board Description
+
+ The mvBL-M7 is a 120x120mm single board computing platform
+ with strong focus on stereo image processing applications.
+
+ Power Supply is either VDC 12-48V or Pover over Ethernet (PoE)
+ on any port (requires add-on board).
+
+2 System Components
+
+2.1 CPU
+ Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb.
+ 512MByte DDR-II memory @ 133MHz.
+ 8 MByte Nor Flash on local bus.
+ 2 Vitesse VSC8601 RGMII ethernet Phys.
+ 1 USB host controller over ULPI I/F.
+ 2 serial ports. Console running on ttyS0 @ 115200 8N1.
+ 1 SD-Card slot connected to SPI.
+ System configuration (HRCW) is taken from I2C EEPROM.
+
+2.2 PCI
+ A miniPCI Type-III socket is present. PCI clock fixed at 66MHz.
+
+2.3 FPGA
+ Altera Cyclone-II EP2C20/35 with PCI DMA engines.
+ Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces.
+ Utilizes another 256MB DDR-II memory and 32-128MB Nand Flash.
+
+2.3.1 I/O @ FPGA
+ 2x8 Outputs : Infineon High-Side Switches to Main Supply.
+ 2x8 Inputs : Programmable input threshold + trigger capabilities
+ 2 dedicated flash interfaces for illuminator boards.
+ Cross trigger for chaining several boards.
+
+2.4 I2C
+ Bus1:
+ MAX5381 DAC @ 0x60 for 1st digital input threshold.
+ LM75 @ 0x90 for temperature monitoring.
+ EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics.
+ 1st image sensor interface (slave addresses depend on sensor)
+ Bus2:
+ MAX5381 DAC @ 0x60 for 2nd digital input threshold.
+ 2nd image sensor interface (slave addresses depend on sensor)
+
+3 Flash layout.
+
+ reset vector is 0xFFF00100, i.e. "HIGHBOOT".
+
+ FF800000 environment
+ FF802000 redundant environment
+ FF804000 u-boot script image
+ FF806000 redundant u-boot script image
+ FF808000 device tree blob
+ FF80A000 redundant device tree blob
+ FF80C000 tbd.
+ FF80E000 tbd.
+ FF810000 kernel
+ FFC00000 root FS
+ FFF00000 u-boot
+ FFF80000 FPGA raw bit file
+
+ mtd partitions are propagated to linux kernel via device tree blob.
+
+4 Booting
+
+ On startup the bootscript @ FF804000 is executed. This script can be
+ exchanged easily. Default boot mode is "boot from flash", i.e. system
+ works stand-alone.
+
+ This behaviour depends on some environment variables :
+
+ "netboot" : yes ->try dhcp/bootp and boot from network.
+ A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
+ DHCP server configuration, e.g. to provide different images to
+ different devices.
+
+ During netboot the system tries to get 3 image files:
+ 1. Kernel - name + data is given during BOOTP.
+ 2. Initrd - name is stored in "initrd_name"
+ 3. device tree blob - name is stored in "dtb_name"
+ Fallback files are the flash versions.
diff --git a/board/matrix_vision/mvsmr/README.mvsmr b/board/matrix_vision/mvsmr/README.mvsmr
new file mode 100644
index 0000000..8e34cb7
--- /dev/null
+++ b/board/matrix_vision/mvsmr/README.mvsmr
@@ -0,0 +1,55 @@
+Matrix Vision mvSMR
+-------------------
+
+1. Board Description
+
+ The mvSMR is a 75x130mm single image processing board used
+ in automation. Power Supply is 24VDC.
+
+2 System Components
+
+2.1 CPU
+ Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB.
+ 64MB DDR-I @ 133MHz.
+ 8 MByte Nor Flash on local bus.
+ 2 serial ports. Console running on ttyS0 @ 115200 8N1.
+
+2.2 PCI
+ PCI clock fixed at 33MHz due to old'n'slow Xilinx PCI core.
+
+2.3 FPGA
+ Xilinx Spartan-3 XC3S200 with PCI DMA engine.
+ Connects to Matrix Vision specific CCD/CMOS sensor interface.
+
+2.4 I2C
+ EEPROM @ 0xA0 for vendor specifics.
+ image sensor interface (slave addresses depend on sensor)
+
+3 Flash layout.
+
+ reset vector is 0x00000100, i.e. "LOWBOOT".
+
+ FF800000 u-boot
+ FF806000 u-boot script image
+ FF808000 u-boot environment
+ FF840000 FPGA raw bit file
+ FF880000 root FS
+ FFF00000 kernel
+
+4 Booting
+
+ On startup the bootscript @ FF806000 is executed. This script can be
+ exchanged easily. Default boot mode is "boot from flash", i.e. system
+ works stand-alone.
+
+ This behaviour depends on some environment variables :
+
+ "netboot" : yes ->try dhcp/bootp and boot from network.
+ A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
+ DHCP server configuration, e.g. to provide different images to
+ different devices.
+
+ During netboot the system tries to get 3 image files:
+ 1. Kernel - name + data is given during BOOTP.
+ 2. Initrd - name is stored in "initrd_name"
+ Fallback files are the flash versions.