diff options
Diffstat (limited to 'board/mpl/mip405')
| -rw-r--r-- | board/mpl/mip405/Kconfig | 17 | ||||
| -rw-r--r-- | board/mpl/mip405/MAINTAINERS | 7 | ||||
| -rw-r--r-- | board/mpl/mip405/Makefile | 12 | ||||
| -rw-r--r-- | board/mpl/mip405/cmd_mip405.c | 49 | ||||
| -rw-r--r-- | board/mpl/mip405/init.S | 200 | ||||
| -rw-r--r-- | board/mpl/mip405/mip405.c | 805 | ||||
| -rw-r--r-- | board/mpl/mip405/mip405.h | 166 |
7 files changed, 0 insertions, 1256 deletions
diff --git a/board/mpl/mip405/Kconfig b/board/mpl/mip405/Kconfig deleted file mode 100644 index e003a43..0000000 --- a/board/mpl/mip405/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -if TARGET_MIP405 || TARGET_MIP405T - -config SYS_BOARD - default "mip405" - -config SYS_VENDOR - default "mpl" - -config SYS_CONFIG_NAME - default "MIP405" - -config ISO_STRING - string - default "MEV-10082-001" if TARGET_MIP405T - default "MEV-10072-001" if TARGET_MIP405 - -endif diff --git a/board/mpl/mip405/MAINTAINERS b/board/mpl/mip405/MAINTAINERS deleted file mode 100644 index b323e5a..0000000 --- a/board/mpl/mip405/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -MIP405 BOARD -M: Denis Peter <d.peter@mpl.ch> -S: Maintained -F: board/mpl/mip405/ -F: include/configs/MIP405.h -F: configs/MIP405_defconfig -F: configs/MIP405T_defconfig diff --git a/board/mpl/mip405/Makefile b/board/mpl/mip405/Makefile deleted file mode 100644 index 5bcf130..0000000 --- a/board/mpl/mip405/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = mip405.o cmd_mip405.o \ - ../common/pci.o \ - ../common/usb_uhci.o \ - ../common/common_util.o -obj-y += init.o diff --git a/board/mpl/mip405/cmd_mip405.c b/board/mpl/mip405/cmd_mip405.c deleted file mode 100644 index ca6f0af..0000000 --- a/board/mpl/mip405/cmd_mip405.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * SPDX-License-Identifier: GPL-2.0+ - * - * hacked for MIP405 - */ - -#include <common.h> -#include <command.h> -#include "mip405.h" -#include "../common/common_util.h" - - -extern void print_mip405_info(void); -extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); - - -/* ------------------------------------------------------------------------- */ - -int do_mip405(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - - ulong led_on; - - if (strcmp(argv[1], "info") == 0) - { - print_mip405_info(); - return 0; - } - if (strcmp(argv[1], "led") == 0) - { - led_on = (ulong)simple_strtoul(argv[2], NULL, 10); - user_led0(led_on); - return 0; - } - return (do_mplcommon(cmdtp, flag, argc, argv)); -} -U_BOOT_CMD( - mip405, 8, 1, do_mip405, - "MIP405 specific Cmds", - "flash mem [SrcAddr] - updates U-Boot with image in memory\n" - "mip405 flash mps - updates U-Boot with image from MPS\n" - "mip405 info - displays board information\n" - "mip405 led <on> - switches LED on (on=1) or off (on=0)" -); - -/* ------------------------------------------------------------------------- */ diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S deleted file mode 100644 index 2ea2e29..0000000 --- a/board/mpl/mip405/init.S +++ /dev/null @@ -1,200 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0 IBM-pibs - */ -/*----------------------------------------------------------------------------- - * Function: ext_bus_cntlr_init - * Description: Initializes the External Bus Controller for the external - * peripherals. IMPORTANT: For pass1 this code must run from - * cache since you can not reliably change a peripheral banks - * timing register (pbxap) while running code from that bank. - * For ex., since we are running from ROM on bank 0, we can NOT - * execute the code that modifies bank 0 timings from ROM, so - * we run it from cache. - * Bank 0 - Flash or Multi Purpose Socket - * Bank 1 - Multi Purpose Socket or Flash (set in C-Code) - * Bank 2 - UART 1 (set in C-Code) - * Bank 3 - UART 2 (set in C-Code) - * Bank 4 - not used - * Bank 5 - not used - * Bank 6 - not used - * Bank 7 - PLD Register - *-----------------------------------------------------------------------------*/ - -#include <configs/MIP405.h> -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> -#include <asm/ppc4xx.h> -#include "mip405.h" - - - .globl ext_bus_cntlr_init -ext_bus_cntlr_init: - mflr r4 /* save link register */ - mfdcr r3,CPC0_PSR /* get strapping reg */ - andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */ - bnelr /* jump back if PCI boot */ - - bl ..getAddr -..getAddr: - mflr r3 /* get address of ..getAddr */ - mtlr r4 /* restore link register */ - addi r4,0,14 /* set ctr to 14; used to prefetch */ - mtctr r4 /* 14 cache lines to fit this function */ - /* in cache (gives us 8x14=112 instrctns) */ -..ebcloop: - icbt r0,r3 /* prefetch cache line for addr in r3 */ - addi r3,r3,32 /* move to next cache line */ - bdnz ..ebcloop /* continue for 14 cache lines */ - - /*------------------------------------------------------------------- - * Delay to ensure all accesses to ROM are complete before changing - * bank 0 timings. - *------------------------------------------------------------------- */ - addis r3,0,0x0 - ori r3,r3,0xA000 - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - - /*----------------------------------------------------------------------- - * decide boot up mode - *----------------------------------------------------------------------- */ - addi r4,0,PB0CR - mtdcr EBC0_CFGADDR,r4 - mfdcr r4,EBC0_CFGDATA - - andi. r0, r4, 0x2000 /* mask out irrelevant bits */ - beq 0f /* jump if 8 bit bus width */ - - /* setup 16 bit things - *----------------------------------------------------------------------- - * Memory Bank 0 (16 Bit Flash) initialization - *---------------------------------------------------------------------- */ - - addi r4,0,PB1AP - mtdcr EBC0_CFGADDR,r4 - addis r4,0,(FLASH_AP_B)@h - ori r4,r4,(FLASH_AP_B)@l - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB0CR - mtdcr EBC0_CFGADDR,r4 - /* BS=0x010(4MB),BU=0x3(R/W), */ - addis r4,0,(FLASH_CR_B)@h - ori r4,r4,(FLASH_CR_B)@l - mtdcr EBC0_CFGDATA,r4 - b 1f - -0: - - /* 8Bit boot mode: */ - /*----------------------------------------------------------------------- - * Memory Bank 0 Multi Purpose Socket initialization - *----------------------------------------------------------------------- */ - /* 0x7F8FFE80 slowest boot */ - addi r4,0,PB1AP - mtdcr EBC0_CFGADDR,r4 - addis r4,0,(MPS_AP_B)@h - ori r4,r4,(MPS_AP_B)@l - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB0CR - mtdcr EBC0_CFGADDR,r4 - /* BS=0x010(4MB),BU=0x3(R/W), */ - addis r4,0,(MPS_CR_B)@h - ori r4,r4,(MPS_CR_B)@l - - mtdcr EBC0_CFGDATA,r4 - - -1: - /*----------------------------------------------------------------------- - * Memory Bank 2-3-4-5-6 (not used) initialization - *-----------------------------------------------------------------------*/ - addi r4,0,PB1CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB2CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB3CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB4CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB5CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB6CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB7CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr EBC0_CFGDATA,r4 - nop /* pass2 DCR errata #8 */ - blr - -#if defined(CONFIG_BOOT_PCI) - .section .bootpg,"ax" - .globl _start_pci -/******************************************* - */ - -_start_pci: - /* first handle errata #68 / PCI_18 */ - iccci r0, r0 /* invalidate I-cache */ - lis r31, 0 - mticcr r31 /* ICCR = 0 (all uncachable) */ - isync - - mfccr0 r28 /* set CCR0[24] = 1 */ - ori r28, r28, 0x0080 - mtccr0 r28 - - /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */ - lis r28, 0xEF40 - addi r28, r28, 0x0004 - stw r31, 0x0C(r28) /* clear PMM0PCIHA */ - lis r29, 0xFFF8 /* open 512 kByte */ - addi r29, r29, 0x0001/* and enable this region */ - stwbrx r29, r0, r28 /* write PMM0MA */ - - lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */ - addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */ - - lis r31, 0x8000 /* set en bit bus 0 */ - ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */ - stwbrx r31, r0, r28 /* write it */ - - lwbrx r31, r0, r29 /* load XBCS register */ - oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */ - stwbrx r31, r0, r29 /* write back XBCS register */ - - nop - nop - b _start /* normal start */ -#endif diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c deleted file mode 100644 index 4d8671f..0000000 --- a/board/mpl/mip405/mip405.c +++ /dev/null @@ -1,805 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * SPDX-License-Identifier: GPL-2.0+ - * - * TODO: clean-up - */ - -/* - * How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM? - * - * As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being - * used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum - * parameters from the datasheet are: - * Tclk = 7.5ns (CL = 2) - * Trp = 15ns - * Trc = 60ns - * Trcd = 15ns - * Trfc = 66ns - * - * If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock - * period is 10ns and the parameters needed for the Timing Register are: - * CASL = CL = 2 clock cycles - * PTA = Trp = 15ns / 10ns = 2 clock cycles - * CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles - * LDF = 2 clock cycles (but can be extended to meet board-level timing) - * RFTA = Trfc = 66ns / 10ns= 7 clock cycles - * RCD = Trcd = 15ns / 10ns= 2 clock cycles - * - * The actual bit settings in the register would be: - * - * CASL = 0b01 - * PTA = 0b01 - * CTP = 0b10 - * LDF = 0b01 - * RFTA = 0b011 - * RCD = 0b01 - * - * If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc - * instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay - * defined as Trc rather than Trfc. - * When using DIMM modules, most but not all of the required timing parameters can be read - * from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc - * are not available from the EEPROM - */ - -#include <common.h> -#include "mip405.h" -#include <asm/processor.h> -#include <asm/ppc4xx.h> -#include <asm/ppc4xx-i2c.h> -#include <miiphy.h> -#include "../common/common_util.h" -#include <stdio_dev.h> -#include <i2c.h> -#include <rtc.h> - -DECLARE_GLOBAL_DATA_PTR; - -#undef SDRAM_DEBUG -#define ENABLE_ECC /* for ecc boards */ - -/* stdlib.h causes some compatibility problems; should fixe these! -- wd */ -#ifndef __ldiv_t_defined -typedef struct { - long int quot; /* Quotient */ - long int rem; /* Remainder */ -} ldiv_t; -extern ldiv_t ldiv (long int __numer, long int __denom); -# define __ldiv_t_defined 1 -#endif - - -#define PLD_PART_REG PER_PLD_ADDR + 0 -#define PLD_VERS_REG PER_PLD_ADDR + 1 -#define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2 -#define PLD_IRQ_REG PER_PLD_ADDR + 3 -#define PLD_COM_MODE_REG PER_PLD_ADDR + 4 -#define PLD_EXT_CONF_REG PER_PLD_ADDR + 5 - -#define MEGA_BYTE (1024*1024) - -typedef struct { - unsigned char boardtype; /* Board revision and Population Options */ - unsigned char cal; /* cas Latency (will be programmend as cal-1) */ - unsigned char trp; /* datain27 in clocks */ - unsigned char trcd; /* datain29 in clocks */ - unsigned char tras; /* datain30 in clocks */ - unsigned char tctp; /* tras - trcd in clocks */ - unsigned char am; /* Address Mod (will be programmed as am-1) */ - unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */ - unsigned char ecc; /* if true, ecc is enabled */ -} sdram_t; -#if defined(CONFIG_TARGET_MIP405T) -const sdram_t sdram_table[] = { - { 0x0F, /* MIP405T Rev A, 64MByte -1 Board */ - 3, /* Case Latenty = 3 */ - 3, /* trp 20ns / 7.5 ns datain[27] */ - 3, /* trcd 20ns /7.5 ns (datain[29]) */ - 6, /* tras 44ns /7.5 ns (datain[30]) */ - 4, /* tcpt 44 - 20ns = 24ns */ - 2, /* Address Mode = 2 (12x9x4) */ - 3, /* size value (32MByte) */ - 0}, /* ECC disabled */ - { 0xff, /* terminator */ - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff } -}; -#else -const sdram_t sdram_table[] = { - { 0x0f, /* Rev A, 128MByte -1 Board */ - 3, /* Case Latenty = 3 */ - 3, /* trp 20ns / 7.5 ns datain[27] */ - 3, /* trcd 20ns /7.5 ns (datain[29]) */ - 6, /* tras 44ns /7.5 ns (datain[30]) */ - 4, /* tcpt 44 - 20ns = 24ns */ - 3, /* Address Mode = 3 */ - 5, /* size value */ - 1}, /* ECC enabled */ - { 0x07, /* Rev A, 64MByte -2 Board */ - 3, /* Case Latenty = 3 */ - 3, /* trp 20ns / 7.5 ns datain[27] */ - 3, /* trcd 20ns /7.5 ns (datain[29]) */ - 6, /* tras 44ns /7.5 ns (datain[30]) */ - 4, /* tcpt 44 - 20ns = 24ns */ - 2, /* Address Mode = 2 */ - 4, /* size value */ - 1}, /* ECC enabled */ - { 0x03, /* Rev A, 128MByte -4 Board */ - 3, /* Case Latenty = 3 */ - 3, /* trp 20ns / 7.5 ns datain[27] */ - 3, /* trcd 20ns /7.5 ns (datain[29]) */ - 6, /* tras 44ns /7.5 ns (datain[30]) */ - 4, /* tcpt 44 - 20ns = 24ns */ - 3, /* Address Mode = 3 */ - 5, /* size value */ - 1}, /* ECC enabled */ - { 0x1f, /* Rev B, 128MByte -3 Board */ - 3, /* Case Latenty = 3 */ - 3, /* trp 20ns / 7.5 ns datain[27] */ - 3, /* trcd 20ns /7.5 ns (datain[29]) */ - 6, /* tras 44ns /7.5 ns (datain[30]) */ - 4, /* tcpt 44 - 20ns = 24ns */ - 3, /* Address Mode = 3 */ - 5, /* size value */ - 1}, /* ECC enabled */ - { 0x2f, /* Rev C, 128MByte -3 Board */ - 3, /* Case Latenty = 3 */ - 3, /* trp 20ns / 7.5 ns datain[27] */ - 3, /* trcd 20ns /7.5 ns (datain[29]) */ - 6, /* tras 44ns /7.5 ns (datain[30]) */ - 4, /* tcpt 44 - 20ns = 24ns */ - 3, /* Address Mode = 3 */ - 5, /* size value */ - 1}, /* ECC enabled */ - { 0xff, /* terminator */ - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff } -}; -#endif /*CONFIG_TARGET_MIP405T */ -void SDRAM_err (const char *s) -{ -#ifndef SDRAM_DEBUG - (void) get_clocks (); - gd->baudrate = 9600; - serial_init (); -#endif - serial_puts ("\n"); - serial_puts (s); - serial_puts ("\n enable SDRAM_DEBUG for more info\n"); - for (;;); -} - - -unsigned char get_board_revcfg (void) -{ - out8 (PER_BOARD_ADDR, 0); - return (in8 (PER_BOARD_ADDR)); -} - - -#ifdef SDRAM_DEBUG - -void write_hex (unsigned char i) -{ - char cc; - - cc = i >> 4; - cc &= 0xf; - if (cc > 9) - serial_putc (cc + 55); - else - serial_putc (cc + 48); - cc = i & 0xf; - if (cc > 9) - serial_putc (cc + 55); - else - serial_putc (cc + 48); -} - -void write_4hex (unsigned long val) -{ - write_hex ((unsigned char) (val >> 24)); - write_hex ((unsigned char) (val >> 16)); - write_hex ((unsigned char) (val >> 8)); - write_hex ((unsigned char) val); -} - -#endif - - -int init_sdram (void) -{ - unsigned long tmp, baseaddr; - unsigned short i; - unsigned char trp_clocks, - trcd_clocks, - tras_clocks, - trc_clocks; - unsigned char cal_val; - unsigned char bc; - unsigned long sdram_tim, sdram_bank; - - /*i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);*/ - (void) get_clocks (); - gd->baudrate = 9600; - serial_init (); - /* set up the pld */ - mtdcr (EBC0_CFGADDR, PB7AP); - mtdcr (EBC0_CFGDATA, PLD_AP); - mtdcr (EBC0_CFGADDR, PB7CR); - mtdcr (EBC0_CFGDATA, PLD_CR); - /* THIS IS OBSOLETE */ - /* set up the board rev reg*/ - mtdcr (EBC0_CFGADDR, PB5AP); - mtdcr (EBC0_CFGDATA, BOARD_AP); - mtdcr (EBC0_CFGADDR, PB5CR); - mtdcr (EBC0_CFGDATA, BOARD_CR); -#ifdef SDRAM_DEBUG - /* get all informations from PLD */ - serial_puts ("\nPLD Part 0x"); - bc = in8 (PLD_PART_REG); - write_hex (bc); - serial_puts ("\nPLD Vers 0x"); - bc = in8 (PLD_VERS_REG); - write_hex (bc); - serial_puts ("\nBoard Rev 0x"); - bc = in8 (PLD_BOARD_CFG_REG); - write_hex (bc); - serial_puts ("\n"); -#endif - /* check board */ - bc = in8 (PLD_PART_REG); -#if defined(CONFIG_TARGET_MIP405T) - if((bc & 0x80)==0) - SDRAM_err ("U-Boot configured for a MIP405T not for a MIP405!!!\n"); -#else - if((bc & 0x80)==0x80) - SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n"); -#endif - /* set-up the chipselect machine */ - mtdcr (EBC0_CFGADDR, PB0CR); /* get cs0 config reg */ - tmp = mfdcr (EBC0_CFGDATA); - if ((tmp & 0x00002000) == 0) { - /* MPS Boot, set up the flash */ - mtdcr (EBC0_CFGADDR, PB1AP); - mtdcr (EBC0_CFGDATA, FLASH_AP); - mtdcr (EBC0_CFGADDR, PB1CR); - mtdcr (EBC0_CFGDATA, FLASH_CR); - } else { - /* Flash boot, set up the MPS */ - mtdcr (EBC0_CFGADDR, PB1AP); - mtdcr (EBC0_CFGDATA, MPS_AP); - mtdcr (EBC0_CFGADDR, PB1CR); - mtdcr (EBC0_CFGDATA, MPS_CR); - } - /* set up UART0 (CS2) and UART1 (CS3) */ - mtdcr (EBC0_CFGADDR, PB2AP); - mtdcr (EBC0_CFGDATA, UART0_AP); - mtdcr (EBC0_CFGADDR, PB2CR); - mtdcr (EBC0_CFGDATA, UART0_CR); - mtdcr (EBC0_CFGADDR, PB3AP); - mtdcr (EBC0_CFGDATA, UART1_AP); - mtdcr (EBC0_CFGADDR, PB3CR); - mtdcr (EBC0_CFGDATA, UART1_CR); - bc = in8 (PLD_BOARD_CFG_REG); -#ifdef SDRAM_DEBUG - serial_puts ("\nstart SDRAM Setup\n"); - serial_puts ("\nBoard Rev: "); - write_hex (bc); - serial_puts ("\n"); -#endif - i = 0; - baseaddr = CONFIG_SYS_SDRAM_BASE; - while (sdram_table[i].sz != 0xff) { - if (sdram_table[i].boardtype == bc) - break; - i++; - } - if (sdram_table[i].boardtype != bc) - SDRAM_err ("No SDRAM table found for this board!!!\n"); -#ifdef SDRAM_DEBUG - serial_puts (" found table "); - write_hex (i); - serial_puts (" \n"); -#endif - /* since the ECC initialisation needs some time, - * we show that we're alive - */ - if (sdram_table[i].ecc) - serial_puts ("\nInitializing SDRAM, Please stand by"); - cal_val = sdram_table[i].cal - 1; /* Cas Latency */ - trp_clocks = sdram_table[i].trp; /* 20ns / 7.5 ns datain[27] */ - trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */ - tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */ - /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */ - /* trc_clocks is sum of trp_clocks + tras_clocks */ - trc_clocks = trp_clocks + tras_clocks; - /* get SDRAM timing register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); - sdram_tim = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F; - /* insert CASL value */ - sdram_tim |= ((unsigned long) (cal_val)) << 23; - /* insert PTA value */ - sdram_tim |= ((unsigned long) (trp_clocks - 1)) << 18; - /* insert CTP value */ - sdram_tim |= - ((unsigned long) (trc_clocks - trp_clocks - - trcd_clocks)) << 16; - /* insert LDF (always 01) */ - sdram_tim |= ((unsigned long) 0x01) << 14; - /* insert RFTA value */ - sdram_tim |= ((unsigned long) (trc_clocks - 4)) << 2; - /* insert RCD value */ - sdram_tim |= ((unsigned long) (trcd_clocks - 1)) << 0; - - tmp = ((unsigned long) (sdram_table[i].am - 1) << 13); /* AM = 3 */ - /* insert SZ value; */ - tmp |= ((unsigned long) sdram_table[i].sz << 17); - /* get SDRAM bank 0 register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); - sdram_bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; - sdram_bank |= (baseaddr | tmp | 0x01); - -#ifdef SDRAM_DEBUG - serial_puts ("sdtr: "); - write_4hex (sdram_tim); - serial_puts ("\n"); -#endif - - /* write SDRAM timing register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); - mtdcr (SDRAM0_CFGDATA, sdram_tim); - -#ifdef SDRAM_DEBUG - serial_puts ("mb0cf: "); - write_4hex (sdram_bank); - serial_puts ("\n"); -#endif - - /* write SDRAM bank 0 register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); - mtdcr (SDRAM0_CFGDATA, sdram_bank); - - if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */ - /* get SDRAM refresh interval register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); - tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; - tmp |= 0x07F00000; - } else { - /* get SDRAM refresh interval register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); - tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; - tmp |= 0x05F00000; - } - /* write SDRAM refresh interval register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); - mtdcr (SDRAM0_CFGDATA, tmp); - /* enable ECC if used */ -#if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI) - if (sdram_table[i].ecc) { - /* disable checking for all banks */ - unsigned long *p; -#ifdef SDRAM_DEBUG - serial_puts ("disable ECC.. "); -#endif - mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); - tmp = mfdcr (SDRAM0_CFGDATA); - tmp &= 0xff0fffff; /* disable all banks */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); - /* set up SDRAM Controller with ECC enabled */ -#ifdef SDRAM_DEBUG - serial_puts ("setup SDRAM Controller.. "); -#endif - mtdcr (SDRAM0_CFGDATA, tmp); - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); - tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000; - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); - mtdcr (SDRAM0_CFGDATA, tmp); - udelay (600); -#ifdef SDRAM_DEBUG - serial_puts ("fill the memory..\n"); -#endif - serial_puts ("."); - /* now, fill all the memory */ - tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz); - p = (unsigned long) 0; - while ((unsigned long) p < tmp) { - *p++ = 0L; - if (!((unsigned long) p % 0x00800000)) /* every 8MByte */ - serial_puts ("."); - } - /* enable bank 0 */ - serial_puts ("."); -#ifdef SDRAM_DEBUG - serial_puts ("enable ECC\n"); -#endif - udelay (400); - mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); - tmp = mfdcr (SDRAM0_CFGDATA); - tmp |= 0x00800000; /* enable bank 0 */ - mtdcr (SDRAM0_CFGDATA, tmp); - udelay (400); - } else -#endif - { - /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); - tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80C00000; - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); - mtdcr (SDRAM0_CFGDATA, tmp); - udelay (400); - } - serial_puts ("\n"); - return (0); -} - -int board_early_init_f (void) -{ - init_sdram (); - - /*-------------------------------------------------------------------------+ - | Interrupt controller setup for the PIP405 board. - | Note: IRQ 0-15 405GP internally generated; active high; level sensitive - | IRQ 16 405GP internally generated; active low; level sensitive - | IRQ 17-24 RESERVED - | IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive - | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive - | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive - | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive - | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive - | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive - | Note for MIP405 board: - | An interrupt taken for the SouthBridge (IRQ 25) indicates that - | the Interrupt Controller in the South Bridge has caused the - | interrupt. The IC must be read to determine which device - | caused the interrupt. - | - +-------------------------------------------------------------------------*/ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */ - mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ - mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - return 0; -} - -int board_early_init_r(void) -{ - int mode; - - /* - * since we are relocated, we can finally enable i-cache - * and set up the flash CS correctly - */ - icache_enable(); - setup_cs_reloc(); - /* get and display boot mode */ - mode = get_boot_mode(); - if (mode & BOOT_PCI) - printf("PCI Boot %s Map\n", (mode & BOOT_MPS) ? - "MPS" : "Flash"); - else - printf("%s Boot\n", (mode & BOOT_MPS) ? - "MPS" : "Flash"); - - return 0; -} - -/* - * Get some PLD Registers - */ - -unsigned short get_pld_parvers (void) -{ - unsigned short result; - unsigned char rc; - - rc = in8 (PLD_PART_REG); - result = (unsigned short) rc << 8; - rc = in8 (PLD_VERS_REG); - result |= rc; - return result; -} - - -void user_led0 (unsigned char on) -{ - if (on) - out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4)); - else - out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb)); -} - - -void ide_set_reset (int idereset) -{ - /* if reset = 1 IDE reset will be asserted */ - if (idereset) - out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1)); - else { - udelay (10000); - out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe)); - } -} - - -/* ------------------------------------------------------------------------- */ - -void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var) -{ -#if !defined(CONFIG_TARGET_MIP405T) - unsigned char bc,rc,tmp; - int i; - - bc = in8 (PLD_BOARD_CFG_REG); - tmp = ~bc; - tmp &= 0xf; - rc = 0; - for (i = 0; i < 4; i++) { - rc <<= 1; - rc += (tmp & 0x1); - tmp >>= 1; - } - rc++; - if(( (((bc>>4) & 0xf)==0x2) /* Rev C PCB or */ - || (((bc>>4) & 0xf)==0x1)) /* Rev B PCB with */ - && (rc==0x1)) /* Population Option 1 is a -3 */ - rc=3; - *pcbrev=(bc >> 4) & 0xf; - *var=rc; -#else - unsigned char bc; - bc = in8 (PLD_BOARD_CFG_REG); - *pcbrev=(bc >> 4) & 0xf; - *var=16-(bc & 0xf); -#endif -} - -/* - * Check Board Identity: - */ -/* serial String: "MIP405_1000" OR "MIP405T_1000" */ -#if !defined(CONFIG_TARGET_MIP405T) -#define BOARD_NAME "MIP405" -#else -#define BOARD_NAME "MIP405T" -#endif - -int checkboard (void) -{ - char s[50]; - unsigned char bc, var; - int i; - backup_t *b = (backup_t *) s; - - puts ("Board: "); - get_pcbrev_var(&bc,&var); - i = getenv_f("serial#", (char *)s, 32); - if ((i == 0) || strncmp ((char *)s, BOARD_NAME,sizeof(BOARD_NAME))) { - get_backup_values (b); - if (strncmp (b->signature, "MPL\0", 4) != 0) { - puts ("### No HW ID - assuming " BOARD_NAME); - printf ("-%d Rev %c", var, 'A' + bc); - } else { - b->serial_name[sizeof(BOARD_NAME)-1] = 0; - printf ("%s-%d Rev %c SN: %s", b->serial_name, var, - 'A' + bc, &b->serial_name[sizeof(BOARD_NAME)]); - } - } else { - s[sizeof(BOARD_NAME)-1] = 0; - printf ("%s-%d Rev %c SN: %s", s, var,'A' + bc, - &s[sizeof(BOARD_NAME)]); - } - bc = in8 (PLD_EXT_CONF_REG); - printf (" Boot Config: 0x%x\n", bc); - return (0); -} - - -/* ------------------------------------------------------------------------- */ -/* ------------------------------------------------------------------------- */ -/* - dram_init() reads EEPROM via I2c. EEPROM contains all of - the necessary info for SDRAM controller configuration -*/ -/* ------------------------------------------------------------------------- */ -/* ------------------------------------------------------------------------- */ -static int test_dram (unsigned long ramsize); - -int dram_init(void) -{ - - unsigned long bank_reg[4], tmp, bank_size; - int i; - unsigned long TotalSize; - - /* since the DRAM controller is allready set up, calculate the size with the - bank registers */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); - bank_reg[0] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); - bank_reg[1] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); - bank_reg[2] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); - bank_reg[3] = mfdcr (SDRAM0_CFGDATA); - TotalSize = 0; - for (i = 0; i < 4; i++) { - if ((bank_reg[i] & 0x1) == 0x1) { - tmp = (bank_reg[i] >> 17) & 0x7; - bank_size = 4 << tmp; - TotalSize += bank_size; - } - } - mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); - tmp = mfdcr (SDRAM0_CFGDATA); - - if (!tmp) - printf ("No "); - printf ("ECC "); - - test_dram (TotalSize * MEGA_BYTE); - gd->ram_size = TotalSize * MEGA_BYTE; - - return 0; -} - -/* ------------------------------------------------------------------------- */ - - -static int test_dram (unsigned long ramsize) -{ -#ifdef SDRAM_DEBUG - mem_test (0L, ramsize, 1); -#endif - /* not yet implemented */ - return (1); -} - -/* used to check if the time in RTC is valid */ -static unsigned long start; -static struct rtc_time tm; - -int misc_init_r (void) -{ - /* adjust flash start and size as well as the offset */ - gd->bd->bi_flashstart=0-flash_info[0].size; - gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN; - gd->bd->bi_flashoffset=0; - - /* check, if RTC is running */ - rtc_get (&tm); - start=get_timer(0); - /* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */ - if (mfdcr(CPC0_PSR) & PSR_ROM_LOC) - mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80)); - - return (0); -} - - -void print_mip405_rev (void) -{ - unsigned char part, vers, pcbrev, var; - - get_pcbrev_var(&pcbrev,&var); - part = in8 (PLD_PART_REG); - vers = in8 (PLD_VERS_REG); - printf ("Rev: " BOARD_NAME "-%d Rev %c PLD %d Vers %d\n", - var, pcbrev + 'A', part & 0x7F, vers); -} - - -extern int mk_date (char *, struct rtc_time *); - -int last_stage_init (void) -{ - unsigned long stop; - struct rtc_time newtm; - char *s; - - /* write correct LED configuration */ - if (miiphy_write("ppc_4xx_eth0", 0x1, 0x14, 0x2402) != 0) { - printf ("Error writing to the PHY\n"); - } - /* since LED/CFG2 is not connected on the -2, - * write to correct capability information */ - if (miiphy_write("ppc_4xx_eth0", 0x1, 0x4, 0x01E1) != 0) { - printf ("Error writing to the PHY\n"); - } - print_mip405_rev (); - stdio_print_current_devices (); - check_env (); - /* check if RTC time is valid */ - stop=get_timer(start); - while(stop<1200) { /* we wait 1.2 sec to check if the RTC is running */ - udelay(1000); - stop=get_timer(start); - } - rtc_get (&newtm); - if(tm.tm_sec==newtm.tm_sec) { - s=getenv("defaultdate"); - if(!s) - mk_date ("010112001970", &newtm); - else - if(mk_date (s, &newtm)!=0) { - printf("RTC: Bad date format in defaultdate\n"); - return 0; - } - rtc_reset (); - rtc_set(&newtm); - } - return 0; -} - -/*************************************************************************** - * some helping routines - */ - -int overwrite_console (void) -{ - /* return true if console should be overwritten */ - return ((in8(PLD_EXT_CONF_REG) & 0x1) == 0); -} - - -/************************************************************************ -* Print MIP405 Info -************************************************************************/ -void print_mip405_info (void) -{ - unsigned char part, vers, cfg, irq_reg, com_mode, ext; - - part = in8 (PLD_PART_REG); - vers = in8 (PLD_VERS_REG); - cfg = in8 (PLD_BOARD_CFG_REG); - irq_reg = in8 (PLD_IRQ_REG); - com_mode = in8 (PLD_COM_MODE_REG); - ext = in8 (PLD_EXT_CONF_REG); - - printf ("PLD Part %d version %d\n", part & 0x7F, vers); - printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A'); - printf ("Population Options %d %d %d %d\n", (cfg) & 0x1, - (cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1); - printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off"); - printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3); -#if !defined(CONFIG_TARGET_MIP405T) - printf ("User Config Switch %d %d %d %d %d %d %d %d\n", - (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1, - (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1, - (ext >> 6) & 0x1, (ext >> 7) & 0x1); - printf ("SER1 uses handshakes %s\n", - (ext & 0x80) ? "DTR/DSR" : "RTS/CTS"); -#else - printf ("User Config Switch %d %d %d %d %d %d %d %d\n", - (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1, - (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1, - (ext >> 6) & 0x1,(ext >> 7) & 0x1); -#endif - printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted"); - printf ("IRQs:\n"); - printf (" PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active"); -#if !defined(CONFIG_TARGET_MIP405T) - printf (" UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active"); - printf (" UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active"); -#endif - printf (" PIIX SMI: %s\n", (irq_reg & 0x10) ? "inactive" : "active"); - printf (" PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active"); - printf (" PIIX NMI: %s\n", (irq_reg & 0x4) ? "inactive" : "active"); -} diff --git a/board/mpl/mip405/mip405.h b/board/mpl/mip405/mip405.h deleted file mode 100644 index b1f69aa..0000000 --- a/board/mpl/mip405/mip405.h +++ /dev/null @@ -1,166 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - /**************************************************************************** - * Global routines used for MIP405 - *****************************************************************************/ -#ifndef __ASSEMBLY__ -/*int switch_cs(unsigned char boot);*/ - -extern int mem_test(unsigned long start, unsigned long ramsize,int mode); - -void user_led0(unsigned char on); - - -#endif -/* timings */ -/* PLD (CS7) */ -#define PLD_BME 0 /* Burst disable */ -#define PLD_TWE 5 /* 5 * 30ns 120ns Waitstates (access=TWT+1+TH) */ -#define PLD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ -#define PLD_OEN 1 /* Cycles from CS low to OE low */ -#define PLD_WBN 1 /* Cycles from CS low to WE low */ -#define PLD_WBF 1 /* Cycles from WE high to CS high */ -#define PLD_TH 2 /* Number of hold cycles after transfer */ -#define PLD_RE 0 /* Ready disabled */ -#define PLD_SOR 1 /* Sample on Ready disabled */ -#define PLD_BEM 0 /* Byte Write only active on Write cycles */ -#define PLD_PEN 0 /* Parity disable */ -#define PLD_AP ((PLD_BME << 31) + (PLD_TWE << 23) + (PLD_CSN << 18) + (PLD_OEN << 16) + (PLD_WBN << 14) + \ - (PLD_WBF << 12) + (PLD_TH << 9) + (PLD_RE << 8) + (PLD_SOR << 7) + (PLD_BEM << 6) + (PLD_PEN << 5)) - -/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ -#define PLD_BS 0 /* 1 MByte */ -/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ -#define PLD_BU 3 /* R/W */ -/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ -#define PLD_BW 0 /* 16Bit */ -#define PLD_CR ((PER_PLD_ADDR & 0xfff00000) + (PLD_BS << 17) + (PLD_BU << 15) + (PLD_BW << 13)) - - -/* timings */ - -#define PER_BOARD_ADDR (PER_UART1_ADDR+(1024*1024)) -/* Dummy CS to get the board revision */ -#define BOARD_BME 0 /* Burst disable */ -#define BOARD_TWE 255 /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */ -#define BOARD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ -#define BOARD_OEN 1 /* Cycles from CS low to OE low */ -#define BOARD_WBN 1 /* Cycles from CS low to WE low */ -#define BOARD_WBF 1 /* Cycles from WE high to CS high */ -#define BOARD_TH 2 /* Number of hold cycles after transfer */ -#define BOARD_RE 0 /* Ready disabled */ -#define BOARD_SOR 1 /* Sample on Ready disabled */ -#define BOARD_BEM 0 /* Byte Write only active on Write cycles */ -#define BOARD_PEN 0 /* Parity disable */ -#define BOARD_AP ((BOARD_BME << 31) + (BOARD_TWE << 23) + (BOARD_CSN << 18) + (BOARD_OEN << 16) + (BOARD_WBN << 14) + \ - (BOARD_WBF << 12) + (BOARD_TH << 9) + (BOARD_RE << 8) + (BOARD_SOR << 7) + (BOARD_BEM << 6) + (BOARD_PEN << 5)) - -/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ -#define BOARD_BS 0 /* 1 MByte */ -/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ -#define BOARD_BU 3 /* R/W */ -/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ -#define BOARD_BW 0 /* 16Bit */ -#define BOARD_CR ((PER_BOARD_ADDR & 0xfff00000) + (BOARD_BS << 17) + (BOARD_BU << 15) + (BOARD_BW << 13)) - - -/* UART0 CS2 */ -#define UART0_BME 0 /* Burst disable */ -#define UART0_TWE 7 /* 7 * 30ns 210ns Waitstates (access=TWT+1+TH) */ -#define UART0_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ -#define UART0_OEN 1 /* Cycles from CS low to OE low */ -#define UART0_WBN 1 /* Cycles from CS low to WE low */ -#define UART0_WBF 1 /* Cycles from WE high to CS high */ -#define UART0_TH 2 /* Number of hold cycles after transfer */ -#define UART0_RE 0 /* Ready disabled */ -#define UART0_SOR 1 /* Sample on Ready disabled */ -#define UART0_BEM 0 /* Byte Write only active on Write cycles */ -#define UART0_PEN 0 /* Parity disable */ -#define UART0_AP ((UART0_BME << 31) + (UART0_TWE << 23) + (UART0_CSN << 18) + (UART0_OEN << 16) + (UART0_WBN << 14) + \ - (UART0_WBF << 12) + (UART0_TH << 9) + (UART0_RE << 8) + (UART0_SOR << 7) + (UART0_BEM << 6) + (UART0_PEN << 5)) - -/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ -#define UART0_BS 0 /* 1 MByte */ -/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ -#define UART0_BU 3 /* R/W */ -/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ -#define UART0_BW 0 /* 8Bit */ -#define UART0_CR ((PER_UART0_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13)) - -/* UART1 CS3 */ -#define UART1_AP UART0_AP /* same timing as UART0 */ -#define UART1_CR ((PER_UART1_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13)) - - -/* Flash CS0 or CS 1 */ -/* 0x7F8FFE80 slowest timing at all... */ -#define FLASH_BME_B 1 /* Burst enable */ -#define FLASH_FWT_B 0x6 /* 6 * 30ns 210ns First Wait Access */ -#define FLASH_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */ -#define FLASH_BME 0 /* Burst disable */ -#define FLASH_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */ -#define FLASH_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ -#define FLASH_OEN 1 /* Cycles from CS low to OE low */ -#define FLASH_WBN 1 /* Cycles from CS low to WE low */ -#define FLASH_WBF 1 /* Cycles from WE high to CS high */ -#define FLASH_TH 2 /* Number of hold cycles after transfer */ -#define FLASH_RE 0 /* Ready disabled */ -#define FLASH_SOR 1 /* Sample on Ready disabled */ -#define FLASH_BEM 0 /* Byte Write only active on Write cycles */ -#define FLASH_PEN 0 /* Parity disable */ -/* Access Parameter Register for non Boot */ -#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ - (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5)) -/* Access Parameter Register for Boot */ -#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ - (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5)) - -/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ -#define FLASH_BS FLASH_SIZE_PRELIM /* 4 MByte */ -/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ -#define FLASH_BU 3 /* R/W */ -/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ -#define FLASH_BW 1 /* 16Bit */ -/* CR register for Boot */ -#define FLASH_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13)) -/* CR register for non Boot */ -#define FLASH_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13)) - -/* MPS CS1 or CS0 */ -/* Boot CS: */ -#define MPS_BME_B 1 /* Burst enable */ -#define MPS_FWT_B 0x6/* 6 * 30ns 210ns First Wait Access */ -#define MPS_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */ -#define MPS_BME 0 /* Burst disable */ -#define MPS_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */ -#define MPS_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ -#define MPS_OEN 1 /* Cycles from CS low to OE low */ -#define MPS_WBN 1 /* Cycles from CS low to WE low */ -#define MPS_WBF 1 /* Cycles from WE high to CS high */ -#define MPS_TH 2 /* Number of hold cycles after transfer */ -#define MPS_RE 0 /* Ready disabled */ -#define MPS_SOR 1 /* Sample on Ready disabled */ -#define MPS_BEM 0 /* Byte Write only active on Write cycles */ -#define MPS_PEN 0 /* Parity disable */ -/* Access Parameter Register for non Boot */ -#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ - (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5)) -/* Access Parameter Register for Boot */ -#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ - (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5)) - -/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ -#define MPS_BS 2 /* 4 MByte */ -#define MPS_BS_B FLASH_SIZE_PRELIM /* 1 MByte */ -/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ -#define MPS_BU 3 /* R/W */ -/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ -#define MPS_BW 0 /* 8Bit */ -/* CR register for Boot */ -#define MPS_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS_B << 17) + (MPS_BU << 15) + (MPS_BW << 13)) -/* CR register for non Boot */ -#define MPS_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13)) |