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-rw-r--r--board/mpl/common/common_util.c677
-rw-r--r--board/mpl/common/common_util.h27
-rw-r--r--board/mpl/common/isa.c470
-rw-r--r--board/mpl/common/isa.h41
-rw-r--r--board/mpl/common/kbd.c625
-rw-r--r--board/mpl/common/kbd.h20
-rw-r--r--board/mpl/common/pci.c98
-rw-r--r--board/mpl/common/pci_parts.h176
-rw-r--r--board/mpl/common/piix4_pci.h149
-rw-r--r--board/mpl/common/usb_uhci.c1042
-rw-r--r--board/mpl/common/usb_uhci.h171
-rw-r--r--board/mpl/mip405/Kconfig17
-rw-r--r--board/mpl/mip405/MAINTAINERS7
-rw-r--r--board/mpl/mip405/Makefile12
-rw-r--r--board/mpl/mip405/cmd_mip405.c49
-rw-r--r--board/mpl/mip405/init.S200
-rw-r--r--board/mpl/mip405/mip405.c805
-rw-r--r--board/mpl/mip405/mip405.h166
-rw-r--r--board/mpl/pip405/Kconfig15
-rw-r--r--board/mpl/pip405/MAINTAINERS6
-rw-r--r--board/mpl/pip405/Makefile14
-rw-r--r--board/mpl/pip405/README371
-rw-r--r--board/mpl/pip405/cmd_pip405.c53
-rw-r--r--board/mpl/pip405/init.S197
-rw-r--r--board/mpl/pip405/pip405.c958
-rw-r--r--board/mpl/pip405/pip405.h131
-rw-r--r--board/mpl/pip405/u-boot.lds.debug121
27 files changed, 0 insertions, 6618 deletions
diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c
deleted file mode 100644
index 31636b3..0000000
--- a/board/mpl/common/common_util.c
+++ /dev/null
@@ -1,677 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <video_fb.h>
-#include "common_util.h"
-#include <asm/processor.h>
-#include <asm/byteorder.h>
-#include <i2c.h>
-#include <pci.h>
-#include <malloc.h>
-#include <bzlib.h>
-#include <video.h>
-
-#ifdef CONFIG_PIP405
-#include "../pip405/pip405.h"
-#include <asm/4xx_pci.h>
-#endif
-#if defined(CONFIG_TARGET_MIP405) || defined(CONFIG_TARGET_MIP405T)
-#include "../mip405/mip405.h"
-#include <asm/4xx_pci.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern int mem_test(ulong start, ulong ramsize, int quiet);
-
-#define I2C_BACKUP_ADDR 0x7C00 /* 0x200 bytes for backup */
-#define IMAGE_SIZE CONFIG_SYS_MONITOR_LEN /* ugly, but it works for now */
-
-#if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \
- || defined(CONFIG_TARGET_MIP405T)
-/*-----------------------------------------------------------------------
- * On PIP/MIP405 we have 3 (4) possible boot mode
- *
- * - Boot from Flash (Flash CS = CS0, MPS CS = CS1)
- * - Boot from MPS (Flash CS = CS1, MPS CS = CS0)
- * - Boot from PCI with Flash map (Flash CS = CS0, MPS CS = CS1)
- * - Boot from PCI with MPS map (Flash CS = CS1, MPS CS = CS0)
- * The flash init is the first board specific routine which is called
- * after code relocation (running from SDRAM)
- * The first thing we do is to map the Flash CS to the Flash area and
- * the MPS CS to the MPS area. Since the flash size is unknown at this
- * point, we use the max flash size and the lowest flash address as base.
- *
- * After flash detection we adjust the size of the CS area accordingly.
- * update_flash_size() will fix in wrong values in the flash_info structure,
- * misc_init_r() will fix the values in the board info structure
- */
-int get_boot_mode(void)
-{
- unsigned long pbcr;
- int res = 0;
- pbcr = mfdcr(CPC0_PSR);
- if ((pbcr & PSR_ROM_WIDTH_MASK) == 0)
- /* boot via MPS or MPS mapping */
- res = BOOT_MPS;
- if (pbcr & PSR_ROM_LOC)
- /* boot via PCI.. */
- res |= BOOT_PCI;
- return res;
-}
-
-/* Map the flash high (in boot area)
- This code can only be executed from SDRAM (after relocation).
-*/
-void setup_cs_reloc(void)
-{
- int mode;
- /*
- * since we are relocated, we can set-up the CS finaly
- * but first of all, switch off PCI mapping (in case it
- * was a PCI boot)
- */
- out32r(PMM0MA, 0L);
- /* get boot mode */
- mode = get_boot_mode();
- /*
- * we map the flash high in every case
- * first find out to which CS the flash is attached to
- */
- if (mode & BOOT_MPS) {
- /* map flash high on CS1 and MPS on CS0 */
- mtdcr(EBC0_CFGADDR, PB0AP);
- mtdcr(EBC0_CFGDATA, MPS_AP);
- mtdcr(EBC0_CFGADDR, PB0CR);
- mtdcr(EBC0_CFGDATA, MPS_CR);
- /*
- * we use the default values (max values) for the flash
- * because its real size is not yet known
- */
- mtdcr(EBC0_CFGADDR, PB1AP);
- mtdcr(EBC0_CFGDATA, FLASH_AP);
- mtdcr(EBC0_CFGADDR, PB1CR);
- mtdcr(EBC0_CFGDATA, FLASH_CR_B);
- } else {
- /* map flash high on CS0 and MPS on CS1 */
- mtdcr(EBC0_CFGADDR, PB1AP);
- mtdcr(EBC0_CFGDATA, MPS_AP);
- mtdcr(EBC0_CFGADDR, PB1CR);
- mtdcr(EBC0_CFGDATA, MPS_CR);
- /*
- * we use the default values (max values) for the flash
- * because its real size is not yet known
- */
- mtdcr(EBC0_CFGADDR, PB0AP);
- mtdcr(EBC0_CFGDATA, FLASH_AP);
- mtdcr(EBC0_CFGADDR, PB0CR);
- mtdcr(EBC0_CFGDATA, FLASH_CR_B);
- }
-}
-#endif /* #if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) */
-
-#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE
-/* adjust flash start and protection info */
-int update_flash_size(int flash_size)
-{
- int i = 0, mode;
- flash_info_t *info = &flash_info[0];
- unsigned long flashcr;
- unsigned long flash_base = (0 - flash_size) & 0xFFF00000;
-
- if (flash_size > 128*1024*1024) {
- printf("\n ### ERROR, wrong flash size: %X, reset board ###\n",
- flash_size);
- hang();
- }
-
- if ((flash_size >> 20) != 0)
- i = __ilog2(flash_size >> 20);
-
- /* set up flash CS according to the size */
- mode = get_boot_mode();
- if (mode & BOOT_MPS) {
- /* flash is on CS1 */
- mtdcr(EBC0_CFGADDR, PB1CR);
- flashcr = mfdcr(EBC0_CFGDATA);
- /* we map the flash high in every case */
- flashcr &= 0x0001FFFF; /* mask out address bits */
- flashcr |= flash_base; /* start addr */
- flashcr |= (i << 17); /* size addr */
- mtdcr(EBC0_CFGADDR, PB1CR);
- mtdcr(EBC0_CFGDATA, flashcr);
- } else {
- /* flash is on CS0 */
- mtdcr(EBC0_CFGADDR, PB0CR);
- flashcr = mfdcr(EBC0_CFGDATA);
- /* we map the flash high in every case */
- flashcr &= 0x0001FFFF; /* mask out address bits */
- flashcr |= flash_base; /* start addr */
- flashcr |= (i << 17); /* size addr */
- mtdcr(EBC0_CFGADDR, PB0CR);
- mtdcr(EBC0_CFGDATA, flashcr);
- }
-
- for (i = 0; i < info->sector_count; i++)
- /* adjust sector start address */
- info->start[i] = flash_base +
- (info->start[i] - CONFIG_SYS_FLASH_BASE);
-
- /* unprotect all sectors */
- flash_protect(FLAG_PROTECT_CLEAR,
- info->start[0],
- 0xFFFFFFFF,
- info);
- flash_protect_default();
- /* protect reset vector too*/
- flash_protect(FLAG_PROTECT_SET,
- info->start[info->sector_count-1],
- 0xFFFFFFFF,
- info);
-
- return 0;
-}
-#endif
-
-static int
-mpl_prg(uchar *src, ulong size)
-{
- ulong start;
- flash_info_t *info = &flash_info[0];
- int i, rc;
-#if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) || \
- defined(CONFIG_TARGET_MIP405T)
- char *copystr = (char *)src;
- ulong *magic = (ulong *)src;
-
- if (uimage_to_cpu (magic[0]) != IH_MAGIC) {
- puts("Bad Magic number\n");
- return -1;
- }
- /* some more checks before we delete the Flash... */
- /* Checking the ISO_STRING prevents to program a
- * wrong Firmware Image into the flash.
- */
- i = 4; /* skip Magic number */
- while (1) {
- if (strncmp(&copystr[i], "MEV-", 4) == 0)
- break;
- if (i++ >= 0x100) {
- puts("Firmware Image for unknown Target\n");
- return -1;
- }
- }
- /* we have the ISO STRING, check */
- if (strncmp(&copystr[i], CONFIG_ISO_STRING, sizeof(CONFIG_ISO_STRING)-1) != 0) {
- printf("Wrong Firmware Image: %s\n", &copystr[i]);
- return -1;
- }
- start = 0 - size;
-
- /* unprotect sectors used by u-boot */
- flash_protect(FLAG_PROTECT_CLEAR,
- start,
- 0xFFFFFFFF,
- info);
-
- /* search start sector */
- for (i = info->sector_count-1; i > 0; i--)
- if (start >= info->start[i])
- break;
-
- /* now erase flash */
- printf("Erasing at %lx (sector %d) (start %lx)\n",
- start,i,info->start[i]);
- if ((rc = flash_erase (info, i, info->sector_count-1)) != 0) {
- puts("ERROR ");
- flash_perror(rc);
- return (1);
- }
-#endif
- printf("flash erased, programming from 0x%lx 0x%lx Bytes\n",
- (ulong)src, size);
- if ((rc = flash_write ((char *)src, start, size)) != 0) {
- puts("ERROR ");
- flash_perror(rc);
- return (1);
- }
- puts("OK programming done\n");
- return 0;
-}
-
-
-static int
-mpl_prg_image(uchar *ld_addr)
-{
- unsigned long len;
- uchar *data;
- image_header_t *hdr = (image_header_t *)ld_addr;
- int rc;
-
-#if defined(CONFIG_FIT)
- if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
- puts ("Non legacy image format not supported\n");
- return -1;
- }
-#endif
-
- if (!image_check_magic (hdr)) {
- puts("Bad Magic Number\n");
- return 1;
- }
- image_print_contents (hdr);
- if (!image_check_os (hdr, IH_OS_U_BOOT)) {
- puts("No U-Boot Image\n");
- return 1;
- }
- if (!image_check_type (hdr, IH_TYPE_FIRMWARE)) {
- puts("No Firmware Image\n");
- return 1;
- }
- if (!image_check_hcrc (hdr)) {
- puts("Bad Header Checksum\n");
- return 1;
- }
- puts("Verifying Checksum ... ");
- if (!image_check_dcrc (hdr)) {
- puts("Bad Data CRC\n");
- return 1;
- }
- puts("OK\n");
-
- data = (uchar *)image_get_data (hdr);
- len = image_get_data_size (hdr);
-
- if (image_get_comp (hdr) != IH_COMP_NONE) {
- uchar *buf;
- /* reserve space for uncompressed image */
- if ((buf = malloc(IMAGE_SIZE)) == NULL) {
- puts("Insufficient space for decompression\n");
- return 1;
- }
-
- switch (image_get_comp (hdr)) {
- case IH_COMP_GZIP:
- puts("Uncompressing (GZIP) ... ");
- rc = gunzip ((void *)(buf), IMAGE_SIZE, data, &len);
- if (rc != 0) {
- puts("GUNZIP ERROR\n");
- free(buf);
- return 1;
- }
- puts("OK\n");
- break;
-#ifdef CONFIG_BZIP2
- case IH_COMP_BZIP2:
- puts("Uncompressing (BZIP2) ... ");
- {
- uint retlen = IMAGE_SIZE;
- rc = BZ2_bzBuffToBuffDecompress ((char *)(buf), &retlen,
- (char *)data, len, 0, 0);
- len = retlen;
- }
- if (rc != BZ_OK) {
- printf ("BUNZIP2 ERROR: %d\n", rc);
- free(buf);
- return 1;
- }
- puts("OK\n");
- break;
-#endif
- default:
- printf ("Unimplemented compression type %d\n",
- image_get_comp (hdr));
- free(buf);
- return 1;
- }
-
- rc = mpl_prg(buf, len);
- free(buf);
- } else {
- rc = mpl_prg(data, len);
- }
-
- return(rc);
-}
-
-void get_backup_values(backup_t *buf)
-{
- i2c_read(CONFIG_SYS_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)buf,sizeof(backup_t));
-}
-
-void set_backup_values(int overwrite)
-{
- backup_t back;
- int i;
-
- get_backup_values(&back);
- if(!overwrite) {
- if(strncmp(back.signature,"MPL\0",4)==0) {
- puts("Not possible to write Backup\n");
- return;
- }
- }
- memcpy(back.signature,"MPL\0",4);
- i = getenv_f("serial#",back.serial_name,16);
- if(i < 0) {
- puts("Not possible to write Backup\n");
- return;
- }
- back.serial_name[16]=0;
- i = getenv_f("ethaddr",back.eth_addr,20);
- if(i < 0) {
- puts("Not possible to write Backup\n");
- return;
- }
- back.eth_addr[20]=0;
- i2c_write(CONFIG_SYS_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)&back,sizeof(backup_t));
-}
-
-void clear_env_values(void)
-{
- backup_t back;
- unsigned char env_crc[4];
-
- memset(&back,0xff,sizeof(backup_t));
- memset(env_crc,0x00,4);
- i2c_write(CONFIG_SYS_DEF_EEPROM_ADDR,I2C_BACKUP_ADDR,2,(void *)&back,sizeof(backup_t));
- i2c_write(CONFIG_SYS_DEF_EEPROM_ADDR,CONFIG_ENV_OFFSET,2,(void *)env_crc,4);
-}
-
-/*
- * check crc of "older" environment
- */
-int check_env_old_size(ulong oldsize)
-{
- ulong crc, len, new;
- unsigned off;
- uchar buf[64];
-
- /* read old CRC */
- eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR,
- CONFIG_ENV_OFFSET,
- (uchar *)&crc, sizeof(ulong));
-
- new = 0;
- len = oldsize;
- off = sizeof(long);
- len = oldsize-off;
- while (len > 0) {
- int n = (len > sizeof(buf)) ? sizeof(buf) : len;
-
- eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, buf, n);
- new = crc32 (new, buf, n);
- len -= n;
- off += n;
- }
-
- return (crc == new);
-}
-
-static ulong oldsizes[] = {
- 0x200,
- 0x800,
- 0
-};
-
-void copy_old_env(ulong size)
-{
- uchar name_buf[64];
- uchar value_buf[0x800];
- uchar c;
- ulong len;
- unsigned off;
- uchar *name, *value;
-
- name = &name_buf[0];
- value = &value_buf[0];
- len=size;
- off = sizeof(long);
- while (len > off) {
- eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, &c, 1);
- if(c != '=') {
- *name++=c;
- off++;
- }
- else {
- *name++='\0';
- off++;
- do {
- eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, &c, 1);
- *value++=c;
- off++;
- if(c == '\0')
- break;
- } while(len > off);
- name = &name_buf[0];
- value = &value_buf[0];
- if(strncmp((char *)name,"baudrate",8)!=0) {
- setenv((char *)name,(char *)value);
- }
-
- }
- }
-}
-
-
-void check_env(void)
-{
- char *s;
- int i=0;
- char buf[32];
- backup_t back;
-
- s=getenv("serial#");
- if(!s) {
- while(oldsizes[i]) {
- if(check_env_old_size(oldsizes[i]))
- break;
- i++;
- }
- if(!oldsizes[i]) {
- /* no old environment has been found */
- get_backup_values (&back);
- if (strncmp (back.signature, "MPL\0", 4) == 0) {
- sprintf (buf, "%s", back.serial_name);
- setenv ("serial#", buf);
- sprintf (buf, "%s", back.eth_addr);
- setenv ("ethaddr", buf);
- printf ("INFO: serial# and ethaddr recovered, use saveenv\n");
- return;
- }
- }
- else {
- copy_old_env(oldsizes[i]);
- puts("INFO: old environment ajusted, use saveenv\n");
- }
- }
- else {
- /* check if back up is set */
- get_backup_values(&back);
- if(strncmp(back.signature,"MPL\0",4)!=0) {
- set_backup_values(0);
- }
- }
-}
-
-int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong ld_addr;
- int result;
- ulong size = IMAGE_SIZE;
- ulong src = MULTI_PURPOSE_SOCKET_ADDR;
- backup_t back;
-
- if (strcmp(argv[1], "flash") == 0)
- {
-#if defined(CONFIG_CMD_FDC)
- if (strcmp(argv[2], "floppy") == 0) {
- char *local_args[3];
- extern int do_fdcboot (cmd_tbl_t *, int, int, char *[]);
- puts("\nupdating bootloader image from floppy\n");
- local_args[0] = argv[0];
- if(argc==4) {
- local_args[1] = argv[3];
- local_args[2] = NULL;
- ld_addr=simple_strtoul(argv[3], NULL, 16);
- result=do_fdcboot(cmdtp, 0, 2, local_args);
- }
- else {
- local_args[1] = NULL;
- ld_addr=CONFIG_SYS_LOAD_ADDR;
- result=do_fdcboot(cmdtp, 0, 1, local_args);
- }
- result=mpl_prg_image((uchar *)ld_addr);
- return result;
- }
-#endif
- if (strcmp(argv[2], "mem") == 0) {
- if(argc==4) {
- ld_addr=simple_strtoul(argv[3], NULL, 16);
- }
- else {
- ld_addr=load_addr;
- }
- printf ("\nupdating bootloader image from memory at %lX\n",ld_addr);
- result=mpl_prg_image((uchar *)ld_addr);
- return result;
- }
- if (strcmp(argv[2], "mps") == 0) {
- puts("\nupdating bootloader image from MPS\n");
- result=mpl_prg((uchar *)src,size);
- return result;
- }
- }
- if (strcmp(argv[1], "clearenvvalues") == 0)
- {
- if (strcmp(argv[2], "yes") == 0)
- {
- clear_env_values();
- return 0;
- }
- }
- if (strcmp(argv[1], "getback") == 0) {
- get_backup_values(&back);
- back.signature[3]=0;
- back.serial_name[16]=0;
- back.eth_addr[20]=0;
- printf("GetBackUp: signature: %s\n",back.signature);
- printf(" serial#: %s\n",back.serial_name);
- printf(" ethaddr: %s\n",back.eth_addr);
- return 0;
- }
- if (strcmp(argv[1], "setback") == 0) {
- set_backup_values(1);
- return 0;
- }
- return cmd_usage(cmdtp);
-}
-
-#ifdef CONFIG_VIDEO
-/******************************************************
- * Routines to display the Board information
- * to the screen (since the VGA will be initialized as last,
- * we must resend the infos)
- */
-
-#ifdef CONFIG_CONSOLE_EXTRA_INFO
-extern GraphicDevice ctfb;
-extern int get_boot_mode(void);
-
-void video_get_info_str (int line_number, char *info)
-{
- /* init video info strings for graphic console */
- PPC4xx_SYS_INFO sys_info;
- char rev;
- int i,boot;
- unsigned long pvr;
- char buf[64];
- char buf1[32], buf2[32], buf3[32], buf4[32];
- char cpustr[16];
- char *s, *e, bc;
- switch (line_number)
- {
- case 2:
- /* CPU and board infos */
- pvr=get_pvr();
- get_sys_info (&sys_info);
- switch (pvr) {
- case PVR_405GP_RB: rev='B'; break;
- case PVR_405GP_RC: rev='C'; break;
- case PVR_405GP_RD: rev='D'; break;
- case PVR_405GP_RE: rev='E'; break;
- case PVR_405GPR_RB: rev='B'; break;
- default: rev='?'; break;
- }
- if(pvr==PVR_405GPR_RB)
- sprintf(cpustr,"PPC405GPr %c",rev);
- else
- sprintf(cpustr,"PPC405GP %c",rev);
- /* Board info */
- i=0;
- s=getenv ("serial#");
-#ifdef CONFIG_PIP405
- if (!s || strncmp (s, "PIP405", 6)) {
- strcpy(buf,"### No HW ID - assuming PIP405");
- }
-#endif
-#if defined(CONFIG_TARGET_MIP405) || defined(CONFIG_TARGET_MIP405T)
- if (!s || strncmp (s, "MIP405", 6)) {
- strcpy(buf,"### No HW ID - assuming MIP405");
- }
-#endif
- else {
- for (e = s; *e; ++e) {
- if (*e == ' ')
- break;
- }
- for (; s < e; ++s) {
- if (*s == '_') {
- ++s;
- break;
- }
- buf[i++] = *s;
- }
- strcpy(&buf[i]," SN ");
- i+=4;
- for (; s < e; ++s) {
- buf[i++] = *s;
- }
- buf[i++]=0;
- }
- sprintf (info," %s %s %s MHz (%s/%s/%s MHz)",
- buf, cpustr,
- strmhz (buf1, gd->cpu_clk),
- strmhz (buf2, sys_info.freqPLB),
- strmhz (buf3, sys_info.freqPLB / sys_info.pllOpbDiv),
- strmhz (buf4, sys_info.freqPLB / sys_info.pllExtBusDiv));
- return;
- case 3:
- /* Memory Info */
- boot = get_boot_mode();
- bc = in8 (CONFIG_PORT_ADDR);
- sprintf(info, " %luMB RAM, %luMB Flash Cfg 0x%02X %s %s",
- gd->bd->bi_memsize / 0x100000,
- gd->bd->bi_flashsize / 0x100000,
- bc,
- (boot & BOOT_MPS) ? "MPS boot" : "Flash boot",
- ctfb.modeIdent);
- return;
- case 1:
- strcpy(buf, CONFIG_IDENT_STRING);
- sprintf (info, " %s", &buf[1]);
- return;
- }
- /* no more info lines */
- *info = 0;
- return;
-}
-#endif /* CONFIG_CONSOLE_EXTRA_INFO */
-
-#endif /* CONFIG_VIDEO */
diff --git a/board/mpl/common/common_util.h b/board/mpl/common/common_util.h
deleted file mode 100644
index 127853d..0000000
--- a/board/mpl/common/common_util.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _COMMON_UTIL_H_
-#define _COMMON_UTIL_H_
-
-typedef struct {
- char signature[4];
- char serial_name[17]; /* "MIP405_1000xxxxx" */
- char eth_addr[21]; /* "00:60:C2:0a:00:00" */
-} backup_t;
-
-extern flash_info_t flash_info[]; /* info for FLASH chips */
-
-void get_backup_values(backup_t *buf);
-
-#define BOOT_MPS 0x01
-#define BOOT_PCI 0x02
-int get_boot_mode(void);
-void setup_cs_reloc(void);
-
-void check_env(void);
-
-#endif /* _COMMON_UTIL_H_ */
diff --git a/board/mpl/common/isa.c b/board/mpl/common/isa.c
deleted file mode 100644
index 54ec66b..0000000
--- a/board/mpl/common/isa.c
+++ /dev/null
@@ -1,470 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * TODO: clean-up
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <stdio_dev.h>
-#include "isa.h"
-#include "piix4_pci.h"
-#include "kbd.h"
-#include "video.h"
-
-
-#undef ISA_DEBUG
-
-#ifdef ISA_DEBUG
-#define PRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-
-#if defined(CONFIG_PIP405)
-
-extern int drv_isa_kbd_init (void);
-
-/* fdc (logical device 0) */
-const SIO_LOGDEV_TABLE sio_fdc[] = {
- {0x60, 3}, /* set IO to FDPort (3F0) */
- {0x61, 0xF0}, /* set IO to FDPort (3F0) */
- {0x70, 06}, /* set IRQ 6 for FDPort */
- {0x74, 02}, /* set DMA 2 for FDPort */
- {0xF0, 0x05}, /* set to PS2 type */
- {0xF1, 0x00}, /* default value */
- {0x30, 1}, /* and activate the device */
- {0xFF, 0} /* end of device table */
-};
-/* paralell port (logical device 3) */
-const SIO_LOGDEV_TABLE sio_pport[] = {
- {0x60, 3}, /* set IO to PPort (378) */
- {0x61, 0x78}, /* set IO to PPort (378) */
- {0x70, 07}, /* set IRQ 7 for PPort */
- {0xF1, 00}, /* set PPort to normal */
- {0x30, 1}, /* and activate the device */
- {0xFF, 0} /* end of device table */
-};
-/* paralell port (logical device 3) Floppy assigned to lpt */
-const SIO_LOGDEV_TABLE sio_pport_fdc[] = {
- {0x60, 3}, /* set IO to PPort (378) */
- {0x61, 0x78}, /* set IO to PPort (378) */
- {0x70, 07}, /* set IRQ 7 for PPort */
- {0xF1, 02}, /* set PPort to Floppy */
- {0x30, 1}, /* and activate the device */
- {0xFF, 0} /* end of device table */
-};
-/* uart 1 (logical device 4) */
-const SIO_LOGDEV_TABLE sio_com1[] = {
- {0x60, 3}, /* set IO to COM1 (3F8) */
- {0x61, 0xF8}, /* set IO to COM1 (3F8) */
- {0x70, 04}, /* set IRQ 4 for COM1 */
- {0x30, 1}, /* and activate the device */
- {0xFF, 0} /* end of device table */
-};
-/* uart 2 (logical device 5) */
-const SIO_LOGDEV_TABLE sio_com2[] = {
- {0x60, 2}, /* set IO to COM2 (2F8) */
- {0x61, 0xF8}, /* set IO to COM2 (2F8) */
- {0x70, 03}, /* set IRQ 3 for COM2 */
- {0x30, 1}, /* and activate the device */
- {0xFF, 0} /* end of device table */
-};
-
-/* keyboard controller (logical device 7) */
-const SIO_LOGDEV_TABLE sio_keyboard[] = {
- {0x70, 1}, /* set IRQ 1 for keyboard */
- {0x72, 12}, /* set IRQ 12 for mouse */
- {0xF0, 0}, /* disable Port92 (this is a PowerPC!!) */
- {0x30, 1}, /* and activate the device */
- {0xFF, 0} /* end of device table */
-};
-
-
-/*******************************************************************************
-* Config SuperIO FDC37C672
-********************************************************************************/
-unsigned char open_cfg_super_IO(int address)
-{
- out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x55); /* open config */
- out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x20); /* set address to DEV ID */
- if(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 0x1)==0x40) /* ok Device ID is correct */
- return true;
- else
- return false;
-}
-
-void close_cfg_super_IO(int address)
-{
- out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0xAA); /* close config */
-}
-
-
-unsigned char read_cfg_super_IO(int address, unsigned char function, unsigned char regaddr)
-{
- /* assuming config reg is open */
- out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x7); /* points to the function reg */
- out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1,function); /* set the function no */
- out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,regaddr); /* sets the address in the function */
- return in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1);
-}
-
-void write_cfg_super_IO(int address, unsigned char function, unsigned char regaddr, unsigned char data)
-{
- /* assuming config reg is open */
- out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x7); /* points to the function reg */
- out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1,function); /* set the function no */
- out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,regaddr); /* sets the address in the function */
- out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1,data); /* writes the data */
-}
-
-void isa_write_table(SIO_LOGDEV_TABLE *ldt,unsigned char ldev)
-{
- while (ldt->index != 0xFF) {
- write_cfg_super_IO(SIO_CFG_PORT, ldev, ldt->index, ldt->val);
- ldt++;
- } /* endwhile */
-}
-
-void isa_sio_loadtable(void)
-{
- char *s = getenv("floppy");
- /* setup Floppy device 0*/
- isa_write_table((SIO_LOGDEV_TABLE *)&sio_fdc,0);
- /* setup parallel port device 3 */
- if(s && !strncmp(s, "lpt", 3)) {
- printf("SIO: Floppy assigned to LPT\n");
- /* floppy is assigned to the LPT */
- isa_write_table((SIO_LOGDEV_TABLE *)&sio_pport_fdc,3);
- }
- else {
- /*printf("Floppy assigned to internal port\n");*/
- isa_write_table((SIO_LOGDEV_TABLE *)&sio_pport,3);
- }
- /* setup Com1 port device 4 */
- isa_write_table((SIO_LOGDEV_TABLE *)&sio_com1,4);
- /* setup Com2 port device 5 */
- isa_write_table((SIO_LOGDEV_TABLE *)&sio_com2,5);
- /* setup keyboards device 7 */
- isa_write_table((SIO_LOGDEV_TABLE *)&sio_keyboard,7);
-}
-
-
-void isa_sio_setup(void)
-{
- if (open_cfg_super_IO(SIO_CFG_PORT) == true)
- {
- isa_sio_loadtable();
- close_cfg_super_IO(0x3F0);
- }
-}
-#endif
-
-/******************************************************************************
- * IRQ Controller
- * we use the Vector mode
- */
-
-struct isa_irq_action {
- interrupt_handler_t *handler;
- void *arg;
- int count;
-};
-
-static struct isa_irq_action isa_irqs[16];
-
-
-/*
- * This contains the irq mask for both 8259A irq controllers,
- */
-static unsigned int cached_irq_mask = 0xfff9;
-
-#define cached_imr1 (unsigned char)cached_irq_mask
-#define cached_imr2 (unsigned char)(cached_irq_mask>>8)
-#define IMR_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_OCW1
-#define IMR_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_OCW1
-#define ICW1_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_ICW1
-#define ICW1_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_ICW1
-#define ICW2_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_ICW2
-#define ICW2_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_ICW2
-#define ICW3_1 ICW2_1
-#define ICW3_2 ICW2_2
-#define ICW4_1 ICW2_1
-#define ICW4_2 ICW2_2
-#define ISR_1 ICW1_1
-#define ISR_2 ICW1_2
-
-
-void disable_8259A_irq(unsigned int irq)
-{
- unsigned int mask = 1 << irq;
-
- cached_irq_mask |= mask;
- if (irq & 8)
- out8(IMR_2,cached_imr2);
- else
- out8(IMR_1,cached_imr1);
-}
-
-void enable_8259A_irq(unsigned int irq)
-{
- unsigned int mask = ~(1 << irq);
-
- cached_irq_mask &= mask;
- if (irq & 8)
- out8(IMR_2,cached_imr2);
- else
- out8(IMR_1,cached_imr1);
-}
-/*
-int i8259A_irq_pending(unsigned int irq)
-{
- unsigned int mask = 1<<irq;
- int ret;
-
- if (irq < 8)
- ret = inb(0x20) & mask;
- else
- ret = inb(0xA0) & (mask >> 8);
- spin_unlock_irqrestore(&i8259A_lock, flags);
-
- return ret;
-}
-*/
-
-/*
- * This function assumes to be called rarely. Switching between
- * 8259A registers is slow.
- */
-int i8259A_irq_real(unsigned int irq)
-{
- int value;
- int irqmask = 1<<irq;
-
- if (irq < 8) {
- out8(ISR_1,0x0B); /* ISR register */
- value = in8(ISR_1) & irqmask;
- out8(ISR_1,0x0A); /* back to the IRR register */
- return value;
- }
- out8(ISR_2,0x0B); /* ISR register */
- value = in8(ISR_2) & (irqmask >> 8);
- out8(ISR_2,0x0A); /* back to the IRR register */
- return value;
-}
-
-/*
- * Careful! The 8259A is a fragile beast, it pretty
- * much _has_ to be done exactly like this (mask it
- * first, _then_ send the EOI, and the order of EOI
- * to the two 8259s is important!
- */
-void mask_and_ack_8259A(unsigned int irq)
-{
- unsigned int irqmask = 1 << irq;
- unsigned int temp_irqmask = cached_irq_mask;
- /*
- * Lightweight spurious IRQ detection. We do not want
- * to overdo spurious IRQ handling - it's usually a sign
- * of hardware problems, so we only do the checks we can
- * do without slowing down good hardware unnecesserily.
- *
- * Note that IRQ7 and IRQ15 (the two spurious IRQs
- * usually resulting from the 8259A-1|2 PICs) occur
- * even if the IRQ is masked in the 8259A. Thus we
- * can check spurious 8259A IRQs without doing the
- * quite slow i8259A_irq_real() call for every IRQ.
- * This does not cover 100% of spurious interrupts,
- * but should be enough to warn the user that there
- * is something bad going on ...
- */
- if (temp_irqmask & irqmask)
- goto spurious_8259A_irq;
- temp_irqmask |= irqmask;
-
-handle_real_irq:
- if (irq & 8) {
- in8(IMR_2); /* DUMMY - (do we need this?) */
- out8(IMR_2,(unsigned char)(temp_irqmask>>8));
- out8(ISR_2,0x60+(irq&7));/* 'Specific EOI' to slave */
- out8(ISR_1,0x62); /* 'Specific EOI' to master-IRQ2 */
- out8(IMR_2,cached_imr2); /* turn it on again */
- } else {
- in8(IMR_1); /* DUMMY - (do we need this?) */
- out8(IMR_1,(unsigned char)temp_irqmask);
- out8(ISR_1,0x60+irq); /* 'Specific EOI' to master */
- out8(IMR_1,cached_imr1); /* turn it on again */
- }
-
- return;
-
-spurious_8259A_irq:
- /*
- * this is the slow path - should happen rarely.
- */
- if (i8259A_irq_real(irq))
- /*
- * oops, the IRQ _is_ in service according to the
- * 8259A - not spurious, go handle it.
- */
- goto handle_real_irq;
-
- {
- static int spurious_irq_mask;
- /*
- * At this point we can be sure the IRQ is spurious,
- * lets ACK and report it. [once per IRQ]
- */
- if (!(spurious_irq_mask & irqmask)) {
- PRINTF("spurious 8259A interrupt: IRQ%d.\n", irq);
- spurious_irq_mask |= irqmask;
- }
- /* irq_err_count++; */
- /*
- * Theoretically we do not have to handle this IRQ,
- * but in Linux this does not cause problems and is
- * simpler for us.
- */
- goto handle_real_irq;
- }
-}
-
-void init_8259A(void)
-{
- out8(IMR_1,0xff); /* mask all of 8259A-1 */
- out8(IMR_2,0xff); /* mask all of 8259A-2 */
-
- out8(ICW1_1,0x11); /* ICW1: select 8259A-1 init */
- out8(ICW2_1,0x20 + 0); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
- out8(ICW3_1,0x04); /* 8259A-1 (the master) has a slave on IR2 */
- out8(ICW4_1,0x01); /* master expects normal EOI */
- out8(ICW1_2,0x11); /* ICW2: select 8259A-2 init */
- out8(ICW2_2,0x20 + 8); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
- out8(ICW3_2,0x02); /* 8259A-2 is a slave on master's IR2 */
- out8(ICW4_2,0x01); /* (slave's support for AEOI in flat mode
- is to be investigated) */
- udelay(10000); /* wait for 8259A to initialize */
- out8(IMR_1,cached_imr1); /* restore master IRQ mask */
- udelay(10000); /* wait for 8259A to initialize */
- out8(IMR_2,cached_imr2); /* restore slave IRQ mask */
-}
-
-
-#define PCI_INT_ACK_ADDR 0xEED00000
-
-int handle_isa_int(void)
-{
- unsigned long irqack;
- unsigned char irq;
- /* first we acknokledge the int via the PCI bus */
- irqack=in32(PCI_INT_ACK_ADDR);
- /* now we get the ISRs */
- in8(ISR_2);
- in8(ISR_1);
- irq=(unsigned char)irqack;
- irq-=32;
-/* if((irq==7)&&((isr1&0x80)==0)) {
- PRINTF("IRQ7 detected but not in ISR\n");
- }
- else {
-*/ /* we should handle cascaded interrupts here also */
- {
-/* printf("ISA Irq %d\n",irq); */
- isa_irqs[irq].count++;
- if(irq!=2) { /* just swallow the cascade irq 2 */
- if (isa_irqs[irq].handler != NULL)
- (*isa_irqs[irq].handler)(isa_irqs[irq].arg); /* call isr */
- else {
- PRINTF ("bogus interrupt vector 0x%x\n", irq);
- }
- }
- }
- /* issue EOI instruction to clear the IRQ */
- mask_and_ack_8259A(irq);
- return 0;
-}
-
-
-/******************************************************************
- * Install and free an ISA interrupt handler.
- */
-
-void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
-{
- if (isa_irqs[vec].handler != NULL) {
- printf ("ISA Interrupt vector %d: handler 0x%x replacing 0x%x\n",
- vec, (uint)handler, (uint)isa_irqs[vec].handler);
- }
- isa_irqs[vec].handler = handler;
- isa_irqs[vec].arg = arg;
- enable_8259A_irq(vec);
- PRINTF ("Install ISA IRQ %d ==> %p, @ %p mask=%04x\n", vec, handler, &isa_irqs[vec].handler,cached_irq_mask);
-
-}
-
-void isa_irq_free_handler(int vec)
-{
- disable_8259A_irq(vec);
- isa_irqs[vec].handler = NULL;
- isa_irqs[vec].arg = NULL;
- PRINTF ("Free ISA IRQ %d mask=%04x\n", vec, cached_irq_mask);
-
-}
-
-/****************************************************************************/
-void isa_init_irq_contr(void)
-{
- int i;
- /* disable all Interrupts */
- /* first write icws controller 1 */
- for(i=0;i<16;i++)
- {
- isa_irqs[i].handler=NULL;
- isa_irqs[i].arg=NULL;
- isa_irqs[i].count=0;
- }
- init_8259A();
- out8(IMR_2,0xFF);
-}
-/*************************************************************************/
-
-void isa_show_irq(void)
-{
- int vec;
-
- printf ("\nISA Interrupt-Information:\n");
- printf ("Nr Routine Arg Count\n");
-
- for (vec=0; vec<16; vec++) {
- if (isa_irqs[vec].handler != NULL) {
- printf ("%02d %08lx %08lx %d\n",
- vec,
- (ulong)isa_irqs[vec].handler,
- (ulong)isa_irqs[vec].arg,
- isa_irqs[vec].count);
- }
- }
-}
-
-int isa_irq_get_count(int vec)
-{
- return(isa_irqs[vec].count);
-}
-
-/******************************************************************
- * Init the ISA bus and devices.
- */
-
-#if defined(CONFIG_PIP405)
-
-int isa_init(void)
-{
- isa_sio_setup();
- isa_init_irq_contr();
- drv_isa_kbd_init();
- return 0;
-}
-#endif
diff --git a/board/mpl/common/isa.h b/board/mpl/common/isa.h
deleted file mode 100644
index c706d67..0000000
--- a/board/mpl/common/isa.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ISA_H_
-#define _ISA_H_
-/* Super IO */
-#define SIO_CFG_PORT 0x3F0 /* Config Port Address */
-
-#if defined(CONFIG_PIP405)
-/* table fore SIO initialization */
-typedef struct {
- const uchar index;
- const uchar val;
-} SIO_LOGDEV_TABLE;
-
-typedef struct {
- const uchar ldev;
- const SIO_LOGDEV_TABLE *ldev_table;
-} SIO_TABLE;
-
-
-unsigned char open_cfg_super_IO(int address);
-unsigned char read_cfg_super_IO(int address, unsigned char function, unsigned char regaddr);
-void write_cfg_super_IO(int address, unsigned char function, unsigned char regaddr, unsigned char data);
-void close_cfg_super_IO(int address);
-void isa_sio_setup(void);
-#endif
-
-void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg);
-void isa_irq_free_handler(int vec);
-int handle_isa_int(void);
-void isa_init_irq_contr(void);
-void isa_show_irq(void);
-int isa_irq_get_count(int vec);
-
-
-#endif
diff --git a/board/mpl/common/kbd.c b/board/mpl/common/kbd.c
deleted file mode 100644
index 36b1694..0000000
--- a/board/mpl/common/kbd.c
+++ /dev/null
@@ -1,625 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Source partly derived from:
- * linux/drivers/char/pc_keyb.c
- */
-#include <common.h>
-#include <console.h>
-#include <asm/processor.h>
-#include <stdio_dev.h>
-#include "isa.h"
-#include "kbd.h"
-
-
-unsigned char kbd_read_status(void);
-unsigned char kbd_read_input(void);
-void kbd_send_data(unsigned char data);
-void disable_8259A_irq(unsigned int irq);
-void enable_8259A_irq(unsigned int irq);
-
-/* used only by send_data - set by keyboard_interrupt */
-
-
-#undef KBG_DEBUG
-
-#ifdef KBG_DEBUG
-#define PRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-
-#define KBD_STAT_KOBF 0x01
-#define KBD_STAT_IBF 0x02
-#define KBD_STAT_SYS 0x04
-#define KBD_STAT_CD 0x08
-#define KBD_STAT_LOCK 0x10
-#define KBD_STAT_MOBF 0x20
-#define KBD_STAT_TI_OUT 0x40
-#define KBD_STAT_PARERR 0x80
-
-#define KBD_INIT_TIMEOUT 1000 /* Timeout in ms for initializing the keyboard */
-#define KBC_TIMEOUT 250 /* Timeout in ms for sending to keyboard controller */
-#define KBD_TIMEOUT 2000 /* Timeout in ms for keyboard command acknowledge */
-/*
- * Keyboard Controller Commands
- */
-
-#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
-#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */
-#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */
-#define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */
-#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */
-#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */
-#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */
-#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */
-#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */
-#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */
-#define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
- initiated by the auxiliary device */
-#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
-
-/*
- * Keyboard Commands
- */
-
-#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
-#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
-#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
-#define KBD_CMD_DISABLE 0xF5 /* Disable scanning */
-#define KBD_CMD_RESET 0xFF /* Reset */
-
-/*
- * Keyboard Replies
- */
-
-#define KBD_REPLY_POR 0xAA /* Power on reset */
-#define KBD_REPLY_ACK 0xFA /* Command ACK */
-#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */
-
-/*
- * Status Register Bits
- */
-
-#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
-#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
-#define KBD_STAT_SELFTEST 0x04 /* Self test successful */
-#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
-#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
-#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
-#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
-#define KBD_STAT_PERR 0x80 /* Parity error */
-
-#define AUX_STAT_OBF (KBD_STAT_OBF | KBD_STAT_MOUSE_OBF)
-
-/*
- * Controller Mode Register Bits
- */
-
-#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
-#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
-#define KBD_MODE_SYS 0x04 /* The system flag (?) */
-#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
-#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
-#define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */
-#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
-#define KBD_MODE_RFU 0x80
-
-
-#define KDB_DATA_PORT 0x60
-#define KDB_COMMAND_PORT 0x64
-
-#define LED_SCR 0x01 /* scroll lock led */
-#define LED_CAP 0x04 /* caps lock led */
-#define LED_NUM 0x02 /* num lock led */
-
-#define KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */
-
-
-static volatile char kbd_buffer[KBD_BUFFER_LEN];
-static volatile int in_pointer = 0;
-static volatile int out_pointer = 0;
-
-
-static unsigned char num_lock = 0;
-static unsigned char caps_lock = 0;
-static unsigned char scroll_lock = 0;
-static unsigned char shift = 0;
-static unsigned char ctrl = 0;
-static unsigned char alt = 0;
-static unsigned char e0 = 0;
-static unsigned char leds = 0;
-
-#define DEVNAME "kbd"
-
-/* Simple translation table for the keys */
-
-static unsigned char kbd_plain_xlate[] = {
- 0xff,0x1b, '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '-', '=','\b','\t', /* 0x00 - 0x0f */
- 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', 'o', 'p', '[', ']','\r',0xff, 'a', 's', /* 0x10 - 0x1f */
- 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';','\'', '`',0xff,'\\', 'z', 'x', 'c', 'v', /* 0x20 - 0x2f */
- 'b', 'n', 'm', ',', '.', '/',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */
- '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */
- '\r',0xff,0xff
- };
-
-static unsigned char kbd_shift_xlate[] = {
- 0xff,0x1b, '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_', '+','\b','\t', /* 0x00 - 0x0f */
- 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', 'O', 'P', '{', '}','\r',0xff, 'A', 'S', /* 0x10 - 0x1f */
- 'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', '"', '~',0xff, '|', 'Z', 'X', 'C', 'V', /* 0x20 - 0x2f */
- 'B', 'N', 'M', '<', '>', '?',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */
- '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */
- '\r',0xff,0xff
- };
-
-static unsigned char kbd_ctrl_xlate[] = {
- 0xff,0x1b, '1',0x00, '3', '4', '5',0x1E, '7', '8', '9', '0',0x1F, '=','\b','\t', /* 0x00 - 0x0f */
- 0x11,0x17,0x05,0x12,0x14,0x18,0x15,0x09,0x0f,0x10,0x1b,0x1d,'\n',0xff,0x01,0x13, /* 0x10 - 0x1f */
- 0x04,0x06,0x08,0x09,0x0a,0x0b,0x0c, ';','\'', '~',0x00,0x1c,0x1a,0x18,0x03,0x16, /* 0x20 - 0x2f */
- 0x02,0x0e,0x0d, '<', '>', '?',0xff,0xff,0xff,0x00,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */
- '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */
- '\r',0xff,0xff
- };
-
-/******************************************************************
- * Init
- ******************************************************************/
-int isa_kbd_init(void)
-{
- char* result;
- result=kbd_initialize();
- if(result==NULL) {
- PRINTF("AT Keyboard initialized\n");
- irq_install_handler(25, (interrupt_handler_t *)handle_isa_int, NULL);
- isa_irq_install_handler(KBD_INTERRUPT, (interrupt_handler_t *)kbd_interrupt, NULL);
- return (1);
- } else {
- printf("%s\n",result);
- return (-1);
- }
-}
-
-#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-extern int overwrite_console (void);
-#else
-int overwrite_console (void)
-{
- return (0);
-}
-#endif
-
-int drv_isa_kbd_init (void)
-{
- int error;
- struct stdio_dev kbddev ;
- char *stdinname = getenv ("stdin");
-
- if(isa_kbd_init()==-1)
- return -1;
- memset (&kbddev, 0, sizeof(kbddev));
- strcpy(kbddev.name, DEVNAME);
- kbddev.flags = DEV_FLAGS_INPUT;
- kbddev.getc = kbd_getc ;
- kbddev.tstc = kbd_testc ;
-
- error = stdio_register (&kbddev);
- if(error==0) {
- /* check if this is the standard input device */
- if(strcmp(stdinname,DEVNAME)==0) {
- /* reassign the console */
- if(overwrite_console()) {
- return 1;
- }
- error=console_assign(stdin,DEVNAME);
- if(error==0)
- return 1;
- else
- return error;
- }
- return 1;
- }
- return error;
-}
-
-/******************************************************************
- * Queue handling
- ******************************************************************/
-/* puts character in the queue and sets up the in and out pointer */
-void kbd_put_queue(char data)
-{
- if((in_pointer+1)==KBD_BUFFER_LEN) {
- if(out_pointer==0) {
- return; /* buffer full */
- } else{
- in_pointer=0;
- }
- } else {
- if((in_pointer+1)==out_pointer)
- return; /* buffer full */
- in_pointer++;
- }
- kbd_buffer[in_pointer]=data;
- return;
-}
-
-/* test if a character is in the queue */
-int kbd_testc(struct stdio_dev *dev)
-{
- if(in_pointer==out_pointer)
- return(0); /* no data */
- else
- return(1);
-}
-/* gets the character from the queue */
-int kbd_getc(struct stdio_dev *dev)
-{
- char c;
- while(in_pointer==out_pointer);
- if((out_pointer+1)==KBD_BUFFER_LEN)
- out_pointer=0;
- else
- out_pointer++;
- c=kbd_buffer[out_pointer];
- return (int)c;
-
-}
-
-
-/* set LEDs */
-
-void kbd_set_leds(void)
-{
- if(caps_lock==0)
- leds&=~LED_CAP; /* switch caps_lock off */
- else
- leds|=LED_CAP; /* switch on LED */
- if(num_lock==0)
- leds&=~LED_NUM; /* switch LED off */
- else
- leds|=LED_NUM; /* switch on LED */
- if(scroll_lock==0)
- leds&=~LED_SCR; /* switch LED off */
- else
- leds|=LED_SCR; /* switch on LED */
- kbd_send_data(KBD_CMD_SET_LEDS);
- kbd_send_data(leds);
-}
-
-
-void handle_keyboard_event (unsigned char scancode)
-{
- unsigned char keycode;
-
- /* Convert scancode to keycode */
- PRINTF ("scancode %x\n", scancode);
- if (scancode == 0xe0) {
- e0 = 1; /* special charakters */
- return;
- }
- if (e0 == 1) {
- e0 = 0; /* delete flag */
- if (!(((scancode & 0x7F) == 0x38) || /* the right ctrl key */
- ((scancode & 0x7F) == 0x1D) || /* the right alt key */
- ((scancode & 0x7F) == 0x35) || /* the right '/' key */
- ((scancode & 0x7F) == 0x1C)))
- /* the right enter key */
- /* we swallow unknown e0 codes */
- return;
- }
- /* special cntrl keys */
- switch (scancode) {
- case 0x2A:
- case 0x36: /* shift pressed */
- shift = 1;
- return; /* do nothing else */
- case 0xAA:
- case 0xB6: /* shift released */
- shift = 0;
- return; /* do nothing else */
- case 0x38: /* alt pressed */
- alt = 1;
- return; /* do nothing else */
- case 0xB8: /* alt released */
- alt = 0;
- return; /* do nothing else */
- case 0x1d: /* ctrl pressed */
- ctrl = 1;
- return; /* do nothing else */
- case 0x9d: /* ctrl released */
- ctrl = 0;
- return; /* do nothing else */
- case 0x46: /* scrollock pressed */
- scroll_lock = ~scroll_lock;
- kbd_set_leds ();
- return; /* do nothing else */
- case 0x3A: /* capslock pressed */
- caps_lock = ~caps_lock;
- kbd_set_leds ();
- return;
- case 0x45: /* numlock pressed */
- num_lock = ~num_lock;
- kbd_set_leds ();
- return;
- case 0xC6: /* scroll lock released */
- case 0xC5: /* num lock released */
- case 0xBA: /* caps lock released */
- return; /* just swallow */
- }
- if ((scancode & 0x80) == 0x80) /* key released */
- return;
- /* now, decide which table we need */
- if (scancode > (sizeof (kbd_plain_xlate) / sizeof (kbd_plain_xlate[0]))) { /* scancode not in list */
- PRINTF ("unkown scancode %X\n", scancode);
- return; /* swallow it */
- }
- /* setup plain code first */
- keycode = kbd_plain_xlate[scancode];
- if (caps_lock == 1) { /* caps_lock is pressed, overwrite plain code */
- if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) { /* scancode not in list */
- PRINTF ("unkown caps-locked scancode %X\n", scancode);
- return; /* swallow it */
- }
- keycode = kbd_shift_xlate[scancode];
- if (keycode < 'A') { /* we only want the alphas capital */
- keycode = kbd_plain_xlate[scancode];
- }
- }
- if (shift == 1) { /* shift overwrites caps_lock */
- if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) { /* scancode not in list */
- PRINTF ("unkown shifted scancode %X\n", scancode);
- return; /* swallow it */
- }
- keycode = kbd_shift_xlate[scancode];
- }
- if (ctrl == 1) { /* ctrl overwrites caps_lock and shift */
- if (scancode > (sizeof (kbd_ctrl_xlate) / sizeof (kbd_ctrl_xlate[0]))) { /* scancode not in list */
- PRINTF ("unkown ctrl scancode %X\n", scancode);
- return; /* swallow it */
- }
- keycode = kbd_ctrl_xlate[scancode];
- }
- /* check if valid keycode */
- if (keycode == 0xff) {
- PRINTF ("unkown scancode %X\n", scancode);
- return; /* swallow unknown codes */
- }
-
- kbd_put_queue (keycode);
- PRINTF ("%x\n", keycode);
-}
-
-/*
- * This reads the keyboard status port, and does the
- * appropriate action.
- *
- */
-unsigned char handle_kbd_event(void)
-{
- unsigned char status = kbd_read_status();
- unsigned int work = 10000;
-
- while ((--work > 0) && (status & KBD_STAT_OBF)) {
- unsigned char scancode;
-
- scancode = kbd_read_input();
-
- /* Error bytes must be ignored to make the
- Synaptics touchpads compaq use work */
- /* Ignore error bytes */
- if (!(status & (KBD_STAT_GTO | KBD_STAT_PERR)))
- {
- if (status & KBD_STAT_MOUSE_OBF)
- ; /* not supported: handle_mouse_event(scancode); */
- else
- handle_keyboard_event(scancode);
- }
- status = kbd_read_status();
- }
- if (!work)
- PRINTF("pc_keyb: controller jammed (0x%02X).\n", status);
- return status;
-}
-
-
-/******************************************************************************
- * Lowlevel Part of keyboard section
- */
-unsigned char kbd_read_status(void)
-{
- return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT));
-}
-
-unsigned char kbd_read_input(void)
-{
- return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT));
-}
-
-void kbd_write_command(unsigned char cmd)
-{
- out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd);
-}
-
-void kbd_write_output(unsigned char data)
-{
- out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data);
-}
-
-int kbd_read_data(void)
-{
- int val;
- unsigned char status;
-
- val = -1;
- status = kbd_read_status();
- if (status & KBD_STAT_OBF) {
- val = kbd_read_input();
- if (status & (KBD_STAT_GTO | KBD_STAT_PERR))
- val = -2;
- }
- return val;
-}
-
-int kbd_wait_for_input(void)
-{
- unsigned long timeout;
- int val;
-
- timeout = KBD_TIMEOUT;
- val=kbd_read_data();
- while(val < 0)
- {
- if(timeout--==0)
- return -1;
- udelay(1000);
- val=kbd_read_data();
- }
- return val;
-}
-
-
-int kb_wait(void)
-{
- unsigned long timeout = KBC_TIMEOUT * 10;
-
- do {
- unsigned char status = handle_kbd_event();
- if (!(status & KBD_STAT_IBF))
- return 0; /* ok */
- udelay(1000);
- timeout--;
- } while (timeout);
- return 1;
-}
-
-void kbd_write_command_w(int data)
-{
- if(kb_wait())
- PRINTF("timeout in kbd_write_command_w\n");
- kbd_write_command(data);
-}
-
-void kbd_write_output_w(int data)
-{
- if(kb_wait())
- PRINTF("timeout in kbd_write_output_w\n");
- kbd_write_output(data);
-}
-
-void kbd_send_data(unsigned char data)
-{
- unsigned char status;
- disable_8259A_irq(1); /* disable interrupt */
- kbd_write_output_w(data);
- status = kbd_wait_for_input();
- if (status == KBD_REPLY_ACK)
- enable_8259A_irq(1); /* enable interrupt */
-}
-
-
-char * kbd_initialize(void)
-{
- int status;
-
- in_pointer = 0; /* delete in Buffer */
- out_pointer = 0;
- /*
- * Test the keyboard interface.
- * This seems to be the only way to get it going.
- * If the test is successful a x55 is placed in the input buffer.
- */
- kbd_write_command_w(KBD_CCMD_SELF_TEST);
- if (kbd_wait_for_input() != 0x55)
- return "Kbd: failed self test";
- /*
- * Perform a keyboard interface test. This causes the controller
- * to test the keyboard clock and data lines. The results of the
- * test are placed in the input buffer.
- */
- kbd_write_command_w(KBD_CCMD_KBD_TEST);
- if (kbd_wait_for_input() != 0x00)
- return "Kbd: interface failed self test";
- /*
- * Enable the keyboard by allowing the keyboard clock to run.
- */
- kbd_write_command_w(KBD_CCMD_KBD_ENABLE);
- status = kbd_wait_for_input();
- /*
- * Reset keyboard. If the read times out
- * then the assumption is that no keyboard is
- * plugged into the machine.
- * This defaults the keyboard to scan-code set 2.
- *
- * Set up to try again if the keyboard asks for RESEND.
- */
- do {
- kbd_write_output_w(KBD_CMD_RESET);
- status = kbd_wait_for_input();
- if (status == KBD_REPLY_ACK)
- break;
- if (status != KBD_REPLY_RESEND) {
- PRINTF("status: %X\n",status);
- return "Kbd: reset failed, no ACK";
- }
- } while (1);
- if (kbd_wait_for_input() != KBD_REPLY_POR)
- return "Kbd: reset failed, no POR";
-
- /*
- * Set keyboard controller mode. During this, the keyboard should be
- * in the disabled state.
- *
- * Set up to try again if the keyboard asks for RESEND.
- */
- do {
- kbd_write_output_w(KBD_CMD_DISABLE);
- status = kbd_wait_for_input();
- if (status == KBD_REPLY_ACK)
- break;
- if (status != KBD_REPLY_RESEND)
- return "Kbd: disable keyboard: no ACK";
- } while (1);
-
- kbd_write_command_w(KBD_CCMD_WRITE_MODE);
- kbd_write_output_w(KBD_MODE_KBD_INT
- | KBD_MODE_SYS
- | KBD_MODE_DISABLE_MOUSE
- | KBD_MODE_KCC);
-
- /* AMCC powerpc portables need this to use scan-code set 1 -- Cort */
- kbd_write_command_w(KBD_CCMD_READ_MODE);
- if (!(kbd_wait_for_input() & KBD_MODE_KCC)) {
- /*
- * If the controller does not support conversion,
- * Set the keyboard to scan-code set 1.
- */
- kbd_write_output_w(0xF0);
- kbd_wait_for_input();
- kbd_write_output_w(0x01);
- kbd_wait_for_input();
- }
- kbd_write_output_w(KBD_CMD_ENABLE);
- if (kbd_wait_for_input() != KBD_REPLY_ACK)
- return "Kbd: enable keyboard: no ACK";
-
- /*
- * Finally, set the typematic rate to maximum.
- */
- kbd_write_output_w(KBD_CMD_SET_RATE);
- if (kbd_wait_for_input() != KBD_REPLY_ACK)
- return "Kbd: Set rate: no ACK";
- kbd_write_output_w(0x00);
- if (kbd_wait_for_input() != KBD_REPLY_ACK)
- return "Kbd: Set rate: no ACK";
- return NULL;
-}
-
-void kbd_interrupt(void)
-{
- handle_kbd_event();
-}
diff --git a/board/mpl/common/kbd.h b/board/mpl/common/kbd.h
deleted file mode 100644
index b549e20..0000000
--- a/board/mpl/common/kbd.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _KBD_H_
-#define _KBD_H_
-
-struct stdio_dev;
-
-int kbd_testc(struct stdio_dev *sdev);
-int kbd_getc(struct stdio_dev *sdev);
-extern void kbd_interrupt(void);
-extern char *kbd_initialize(void);
-
-unsigned char kbd_is_init(void);
-#define KBD_INTERRUPT 1
-#endif
diff --git a/board/mpl/common/pci.c b/board/mpl/common/pci.c
deleted file mode 100644
index ad97ffa..0000000
--- a/board/mpl/common/pci.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * SPDX-License-Identifier: GPL-2.0 IBM-pibs
- */
-/*
- * Adapted for PIP405 03.07.01
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * TODO: Clean-up
- */
-
-#include <common.h>
-#include <pci.h>
-#include "isa.h"
-
-#ifdef CONFIG_405GP
-#ifdef CONFIG_PCI
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#include "piix4_pci.h"
-#include "pci_parts.h"
-
-void pci_405gp_init(struct pci_controller *hose);
-
-void pci_pip405_write_regs(struct pci_controller *hose, pci_dev_t dev,
- struct pci_config_table *entry)
-{
- struct pci_pip405_config_entry *table;
- int i;
-
- table = (struct pci_pip405_config_entry *)entry->priv[0];
-
- for (i = 0; table[i].width; i++) {
-#ifdef DEBUG
- printf("Reg 0x%02X Value 0x%08lX Width %02d written\n",
- table[i].index, table[i].val, table[i].width);
-#endif
-
- switch (table[i].width) {
- case 1:
- pci_hose_write_config_byte(hose, dev,
- table[i].index, table[i].val);
- break;
- case 2:
- pci_hose_write_config_word(hose, dev,
- table[i].index, table[i].val);
- break;
- case 4:
- pci_hose_write_config_dword(hose, dev,
- table[i].index, table[i].val);
- break;
- }
- }
-}
-
-
-static void pci_pip405_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
- unsigned char int_line = 0xff;
- unsigned char pin;
- /*
- * Write pci interrupt line register
- */
- if (PCI_DEV(dev) == 0) /* Device0 = PPC405 -> skip */
- return;
- pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
- if ((pin == 0) || (pin > 4))
- return;
-
- int_line = ((PCI_DEV(dev) + (pin-1) + 10) % 4) + 28;
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
-#ifdef DEBUG
- printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n",
- PCI_DEV(dev), dev, int_line, int_line);
-#endif
-}
-
-
-static struct pci_controller hose = {
-config_table: pci_pip405_config_table,
-fixup_irq : pci_pip405_fixup_irq,
-};
-
-
-void pci_init_board(void)
-{
- /*we want the ptrs to RAM not flash (ie don't use init list)*/
- hose.fixup_irq = pci_pip405_fixup_irq;
- hose.config_table = pci_pip405_config_table;
-#ifdef DEBUG
- printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n",
- pci_pip405_fixup_irq, pci_pip405_config_table, hose);
-#endif
- pci_405gp_init(&hose);
-}
-
-#endif /* CONFIG_PCI */
-#endif /* CONFIG_405GP */
diff --git a/board/mpl/common/pci_parts.h b/board/mpl/common/pci_parts.h
deleted file mode 100644
index 75e8cae..0000000
--- a/board/mpl/common/pci_parts.h
+++ /dev/null
@@ -1,176 +0,0 @@
- /*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _PCI_PARTS_H_
-#define _PCI_PARTS_H_
-
-
-/* Board specific file containing:
- * - PCI Memory Mapping
- * - PCI IO Mapping
- * - PCI Interrupt Mapping
- */
-
-/* PIP405 PCI INT Routing:
- * IRQ0 VECTOR
- * PIXX4 IDSEL = AD16 INTA# 28 (Function 2 USB is INTD# = 31)
- * VGA IDSEL = AD17 INTB# 29
- * SCSI IDSEL = AD18 INTC# 30
- * PC104 IDSEL0 = AD20 INTA# 28
- * PC104 IDSEL1 = AD21 INTB# 29
- * PC104 IDSEL2 = AD22 INTC# 30
- * PC104 IDSEL3 = AD23 INTD# 31
- *
- * busdevfunc = EXXX XXXX BBBB BBBB DDDD DFFF RRRR RR00
- * ^ ^ ^ ^ ^
- * 31 23 15 10 7
- * E = Enabled
- * B = Bussnumber
- * D = Devicenumber (Device0 = AD10)
- * F = Functionnumber
- * R = Registernumber
- *
- * Device = (busdevfunc>>11) + 10
- * Vector = devicenumber % 4 + 28
- *
- */
-#define PCI_HIGHEST_ON_BOARD_ID 19
-/*#define PCI_DEV_NUMBER(x) (((x>>11) & 0x1f) + 10) */
-#define PCI_IRQ_VECTOR(x) ((PCI_DEV(x) + 10) % 4) + 28
-
-
-/* PCI Device List for PIP405 */
-
-/* Mapping:
- * +-------------+------------+------------+--------------------------------+
- * | PCI MemAddr | PCI IOAddr | Local Addr | Device / Function |
- * +-------------+------------+------------+--------------------------------+
- * | 0x00000000 | | 0xA0000000 | ISA Memory (hard wired) |
- * | 0x00FFFFFF | | 0xA0FFFFFF | |
- * +-------------+------------+------------+--------------------------------+
- * | | 0x00000000 | 0xE8000000 | ISA IO (hard wired) |
- * | | 0x0000FFFF | 0xE800FFFF | |
- * +-------------+------------+------------+--------------------------------+
- * | 0x80000000 | | 0x80000000 | VGA Controller Memory |
- * | 0x80FFFFFF | | 0x80FFFFFF | |
- * +-------------+------------+------------+--------------------------------+
- * | 0x81000000 | | 0x81000000 | SCSI Controller Memory |
- * | 0x81FFFFFF | | 0x81FFFFFF | |
- * +-------------+------------+------------+--------------------------------+
- */
-
-struct pci_pip405_config_entry {
- int index; /* address */
- unsigned long val; /* value */
- int width; /* data size */
-};
-
-extern void pci_pip405_write_regs(struct pci_controller *,
- pci_dev_t,
- struct pci_config_table *);
-
-/* PIIX4 ISA Bridge Function 0 */
-static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = {
- {PCI_CFG_PIIX4_SERIRQ, 0xD0, 1}, /* enable Continous SERIRQ Pin */
- {PCI_CFG_PIIX4_GENCFG, 0x00018041, 4}, /* enable SERIRQs, ISA, PNP, GPI11 */
- {PCI_CFG_PIIX4_TOM, 0xFE, 1}, /* Top of Memory */
- {PCI_CFG_PIIX4_XBCS, 0x02C4, 2}, /* disable all peri CS */
- {PCI_CFG_PIIX4_RTCCFG, 0x21, 1}, /* enable RTC */
-#if defined(CONFIG_PIP405)
- {PCI_CFG_PIIX4_MBDMA, 0x82, 1}, /* set MBDMA0 to DMA 2 */
- {PCI_CFG_PIIX4_MBDMA+1, 0x83, 1}, /* set MBDMA1 to DMA 3 */
-#endif
- {PCI_CFG_PIIX4_DLC, 0x0, 1}, /* disable passive release feature */
- { } /* end of device table */
-};
-
-/* PIIX4 IDE Controller Function 1 */
-static struct pci_pip405_config_entry piix4_ide_cntrl_f1[] = {
- {PCI_CFG_PIIX4_BMIBA, 0x0001000, 4}, /* set BMI to a valid address */
- {PCI_COMMAND, 0x0001, 2}, /* enable IO access */
-#if !defined(CONFIG_TARGET_MIP405T)
- {PCI_CFG_PIIX4_IDETIM, 0x80008000, 4}, /* enable Both IDE channels */
-#else
- {PCI_CFG_PIIX4_IDETIM, 0x00008000, 4}, /* enable IDE channel0 */
-#endif
- { } /* end of device table */
-};
-
-/* PIIX4 USB Controller Function 2 */
-static struct pci_pip405_config_entry piix4_usb_cntrl_f2[] = {
-#if !defined(CONFIG_TARGET_MIP405T)
- {PCI_INTERRUPT_LINE, 31, 1}, /* Int vector = 31 */
- {PCI_BASE_ADDRESS_4, 0x0000E001, 4}, /* Set IO Address to 0xe000 to 0xe01F */
- {PCI_LATENCY_TIMER, 0x80, 1}, /* Latency Timer 0x80 */
- {0xC0, 0x2000, 2}, /* Legacy support */
- {PCI_COMMAND, 0x0005, 2}, /* enable IO access and Master */
-#endif
- { } /* end of device table */
-};
-
-/* PIIX4 Power Management Function 3 */
-static struct pci_pip405_config_entry piix4_pmm_cntrl_f3[] = {
- {PCI_CFG_PIIX4_PMBA, 0x00004000, 4}, /* set PMBA to "valid" value */
- {PCI_CFG_PIIX4_SMBBA, 0x00005000, 4}, /* set SMBBA to "valid" value */
- {PCI_CFG_PIIX4_PMMISC, 0x01, 1}, /* enable PMBA IO access */
- {PCI_COMMAND, 0x0001, 2}, /* enable IO access */
- { } /* end of device table */
-};
-/* PPC405 Dummy only used to prevent autosetup on this host bridge */
-static struct pci_pip405_config_entry ppc405_dummy[] = {
- { } /* end of device table */
-};
-
-void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
- struct pci_config_table *entry);
-
-
-static struct pci_config_table pci_pip405_config_table[]={
- {PCI_VENDOR_ID_IBM, /* 405 dummy */
- PCI_DEVICE_ID_IBM_405GP,
- PCI_ANY_ID,
- PCI_ANY_ID, PCI_ANY_ID, 0,
- pci_pip405_write_regs, {(unsigned long) ppc405_dummy}},
-
- {PCI_VENDOR_ID_INTEL, /* PIIX4 ISA Bridge Function 0 */
- PCI_DEVICE_ID_INTEL_82371AB_0,
- PCI_ANY_ID,
- PCI_ANY_ID, PCI_ANY_ID, 0,
- pci_pip405_write_regs, {(unsigned long) piix4_isa_bridge_f0}},
-
- {PCI_VENDOR_ID_INTEL, /* PIIX4 IDE Controller Function 1 */
- PCI_DEVICE_ID_INTEL_82371AB,
- PCI_ANY_ID,
- PCI_ANY_ID, PCI_ANY_ID, 1,
- pci_pip405_write_regs, {(unsigned long) piix4_ide_cntrl_f1}},
-
- {PCI_VENDOR_ID_INTEL, /* PIIX4 USB Controller Function 2 */
- PCI_DEVICE_ID_INTEL_82371AB_2,
- PCI_ANY_ID,
- PCI_ANY_ID, PCI_ANY_ID, 2,
- pci_pip405_write_regs, {(unsigned long) piix4_usb_cntrl_f2}},
-
- {PCI_VENDOR_ID_INTEL, /* PIIX4 USB Controller Function 3 */
- PCI_DEVICE_ID_INTEL_82371AB_3,
- PCI_ANY_ID,
- PCI_ANY_ID, PCI_ANY_ID, 3,
- pci_pip405_write_regs, {(unsigned long) piix4_pmm_cntrl_f3}},
-
- {PCI_ANY_ID,
- PCI_ANY_ID,
- PCI_CLASS_DISPLAY_VGA,
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- pci_405gp_setup_vga},
-
- {PCI_ANY_ID,
- PCI_ANY_ID,
- PCI_CLASS_NOT_DEFINED_VGA,
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- pci_405gp_setup_vga},
-
- { }
-};
-#endif /* _PCI_PARTS_H_ */
diff --git a/board/mpl/common/piix4_pci.h b/board/mpl/common/piix4_pci.h
deleted file mode 100644
index c19b64e..0000000
--- a/board/mpl/common/piix4_pci.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#ifndef _PIIX4_PCI_H
-#define _PIIX4_PCI_H
-
-/***************************************************************************
-* Defines PIIX4 Config Registers
-****************************************************************************/
-
-/* Function 0 ISA Bridge */
-#define PCI_CFG_PIIX4_IORT 0x4C /* 8 bit ISA Recovery Timer Reg (default 0x4D) */
-#define PCI_CFG_PIIX4_XBCS 0x4E /* 16 bit XBus Chip select reg (default 0x0003) */
-#define PCI_CFG_PIIX4_PIRQC 0x60 /* PCI IRQ Route Register 4 x 8bit (default )*/
-#define PCI_CFG_PIIX4_SERIRQ 0x64
-#define PCI_CFG_PIIX4_TOM 0x69
-#define PCI_CFG_PIIX4_MSTAT 0x6A
-#define PCI_CFG_PIIX4_MBDMA 0x76
-#define PCI_CFG_PIIX4_APICBS 0x80
-#define PCI_CFG_PIIX4_DLC 0x82
-#define PCI_CFG_PIIX4_PDMACFG 0x90
-#define PCI_CFG_PIIX4_DDMABS 0x92
-#define PCI_CFG_PIIX4_GENCFG 0xB0
-#define PCI_CFG_PIIX4_RTCCFG 0xCB
-
-/* IO Addresses */
-#define PIIX4_ISA_DMA1_CH0BA 0x00
-#define PIIX4_ISA_DMA1_CH0CA 0x01
-#define PIIX4_ISA_DMA1_CH1BA 0x02
-#define PIIX4_ISA_DMA1_CH1CA 0x03
-#define PIIX4_ISA_DMA1_CH2BA 0x04
-#define PIIX4_ISA_DMA1_CH2CA 0x05
-#define PIIX4_ISA_DMA1_CH3BA 0x06
-#define PIIX4_ISA_DMA1_CH3CA 0x07
-#define PIIX4_ISA_DMA1_CMDST 0x08
-#define PIIX4_ISA_DMA1_REQ 0x09
-#define PIIX4_ISA_DMA1_WSBM 0x0A
-#define PIIX4_ISA_DMA1_CH_MOD 0x0B
-#define PIIX4_ISA_DMA1_CLR_PT 0x0C
-#define PIIX4_ISA_DMA1_M_CLR 0x0D
-#define PIIX4_ISA_DMA1_CLR_M 0x0E
-#define PIIX4_ISA_DMA1_RWAMB 0x0F
-
-#define PIIX4_ISA_DMA2_CH0BA 0xC0
-#define PIIX4_ISA_DMA2_CH0CA 0xC1
-#define PIIX4_ISA_DMA2_CH1BA 0xC2
-#define PIIX4_ISA_DMA2_CH1CA 0xC3
-#define PIIX4_ISA_DMA2_CH2BA 0xC4
-#define PIIX4_ISA_DMA2_CH2CA 0xC5
-#define PIIX4_ISA_DMA2_CH3BA 0xC6
-#define PIIX4_ISA_DMA2_CH3CA 0xC7
-#define PIIX4_ISA_DMA2_CMDST 0xD0
-#define PIIX4_ISA_DMA2_REQ 0xD2
-#define PIIX4_ISA_DMA2_WSBM 0xD4
-#define PIIX4_ISA_DMA2_CH_MOD 0xD6
-#define PIIX4_ISA_DMA2_CLR_PT 0xD8
-#define PIIX4_ISA_DMA2_M_CLR 0xDA
-#define PIIX4_ISA_DMA2_CLR_M 0xDC
-#define PIIX4_ISA_DMA2_RWAMB 0xDE
-
-#define PIIX4_ISA_INT1_ICW1 0x20
-#define PIIX4_ISA_INT1_OCW2 0x20
-#define PIIX4_ISA_INT1_OCW3 0x20
-#define PIIX4_ISA_INT1_ICW2 0x21
-#define PIIX4_ISA_INT1_ICW3 0x21
-#define PIIX4_ISA_INT1_ICW4 0x21
-#define PIIX4_ISA_INT1_OCW1 0x21
-
-#define PIIX4_ISA_INT1_ELCR 0x4D0
-
-#define PIIX4_ISA_INT2_ICW1 0xA0
-#define PIIX4_ISA_INT2_OCW2 0xA0
-#define PIIX4_ISA_INT2_OCW3 0xA0
-#define PIIX4_ISA_INT2_ICW2 0xA1
-#define PIIX4_ISA_INT2_ICW3 0xA1
-#define PIIX4_ISA_INT2_ICW4 0xA1
-#define PIIX4_ISA_INT2_OCW1 0xA1
-#define PIIX4_ISA_INT2_IMR 0xA1 /* read only */
-
-#define PIIX4_ISA_INT2_ELCR 0x4D1
-
-#define PIIX4_ISA_TMR0_CNT_ST 0x40
-#define PIIX4_ISA_TMR1_CNT_ST 0x41
-#define PIIX4_ISA_TMR2_CNT_ST 0x42
-#define PIIX4_ISA_TMR_TCW 0x43
-
-#define PIIX4_ISA_RST_XBUS 0x60
-
-#define PIIX4_ISA_NMI_CNT_ST 0x61
-#define PIIX4_ISA_NMI_ENABLE 0x70
-
-#define PIIX4_ISA_RTC_INDEX 0x70
-#define PIIX4_ISA_RTC_DATA 0x71
-#define PIIX4_ISA_RTCEXT_IND 0x70
-#define PIIX4_ISA_RTCEXT_DATA 0x71
-
-#define PIIX4_ISA_DMA1_CH2LPG 0x81
-#define PIIX4_ISA_DMA1_CH3LPG 0x82
-#define PIIX4_ISA_DMA1_CH1LPG 0x83
-#define PIIX4_ISA_DMA1_CH0LPG 0x87
-#define PIIX4_ISA_DMA2_CH2LPG 0x89
-#define PIIX4_ISA_DMA2_CH3LPG 0x8A
-#define PIIX4_ISA_DMA2_CH1LPG 0x8B
-#define PIIX4_ISA_DMA2_LPGRFR 0x8F
-
-#define PIIX4_ISA_PORT_92 0x92
-
-#define PIIX4_ISA_APM_CONTRL 0xB2
-#define PIIX4_ISA_APM_STATUS 0xB3
-
-#define PIIX4_ISA_COCPU_ERROR 0xF0
-
-/* Function 1 IDE Controller */
-#define PCI_CFG_PIIX4_BMIBA 0x20
-#define PCI_CFG_PIIX4_IDETIM 0x40
-#define PCI_CFG_PIIX4_SIDETIM 0x44
-#define PCI_CFG_PIIX4_UDMACTL 0x48
-#define PCI_CFG_PIIX4_UDMATIM 0x4A
-
-/* Function 2 USB Controller */
-#define PCI_CFG_PIIX4_SBRNUM 0x60
-#define PCI_CFG_PIIX4_LEGSUP 0xC0
-
-/* Function 3 Power Management */
-#define PCI_CFG_PIIX4_PMBA 0x40
-#define PCI_CFG_PIIX4_CNTA 0x44
-#define PCI_CFG_PIIX4_CNTB 0x48
-#define PCI_CFG_PIIX4_GPICTL 0x4C
-#define PCI_CFG_PIIX4_DEVRESD 0x50
-#define PCI_CFG_PIIX4_DEVACTA 0x54
-#define PCI_CFG_PIIX4_DEVACTB 0x58
-#define PCI_CFG_PIIX4_DEVRESA 0x5C
-#define PCI_CFG_PIIX4_DEVRESB 0x60
-#define PCI_CFG_PIIX4_DEVRESC 0x64
-#define PCI_CFG_PIIX4_DEVRESE 0x68
-#define PCI_CFG_PIIX4_DEVRESF 0x6C
-#define PCI_CFG_PIIX4_DEVRESG 0x70
-#define PCI_CFG_PIIX4_DEVRESH 0x74
-#define PCI_CFG_PIIX4_DEVRESI 0x78
-#define PCI_CFG_PIIX4_PMMISC 0x80
-#define PCI_CFG_PIIX4_SMBBA 0x90
-
-
-#endif
diff --git a/board/mpl/common/usb_uhci.c b/board/mpl/common/usb_uhci.c
deleted file mode 100644
index 8399407..0000000
--- a/board/mpl/common/usb_uhci.c
+++ /dev/null
@@ -1,1042 +0,0 @@
-/*
- * Part of this code has been derived from linux:
- * Universal Host Controller Interface driver for USB (take II).
- *
- * (c) 1999-2001 Georg Acher, acher@in.tum.de (executive slave) (base guitar)
- * Deti Fliegl, deti@fliegl.de (executive slave) (lead voice)
- * Thomas Sailer, sailer@ife.ee.ethz.ch (chief consultant) (cheer leader)
- * Roman Weissgaerber, weissg@vienna.at (virt root hub) (studio porter)
- * (c) 2000 Yggdrasil Computing, Inc. (port of new PCI interface support
- * from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
- * (C) 2000 David Brownell, david-b@pacbell.net (usb-ohci.c)
- *
- * HW-initalization based on material of
- *
- * (C) Copyright 1999 Linus Torvalds
- * (C) Copyright 1999 Johannes Erdfelt
- * (C) Copyright 1999 Randy Dunlap
- * (C) Copyright 1999 Gregory P. Smith
- *
- *
- * Adapted for U-Boot:
- * (C) Copyright 2001 Denis Peter, MPL AG Switzerland
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/**********************************************************************
- * How it works:
- * -------------
- * The framelist / Transfer descriptor / Queue Heads are similar like
- * in the linux usb_uhci.c.
- *
- * During initialization, the following skeleton is allocated in init_skel:
- *
- * framespecific | common chain
- *
- * framelist[]
- * [ 0 ]-----> TD ---------\
- * [ 1 ]-----> TD ----------> TD ------> QH -------> QH -------> QH ---> NULL
- * ... TD ---------/
- * [1023]-----> TD --------/
- *
- * ^^ ^^ ^^ ^^ ^^
- * 7 TDs for 1 TD for Start of Start of End Chain
- * INT (2-128ms) 1ms-INT CTRL Chain BULK Chain
- *
- *
- * Since this is a bootloader, the isochronous transfer descriptor have been removed.
- *
- * Interrupt Transfers.
- * --------------------
- * For Interrupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
- * will be inserted after the appropriate (depending the interval setting) skeleton TD.
- * If an interrupt has been detected the dev->irqhandler is called. The status and number
- * of transferred bytes is stored in dev->irq_status resp. dev->irq_act_len. If the
- * dev->irqhandler returns 0, the interrupt TD is removed and disabled. If an 1 is returned,
- * the interrupt TD will be reactivated.
- *
- * Control Transfers
- * -----------------
- * Control Transfers are issued by filling the tmp_td with the appropriate data and connect
- * them to the qh_cntrl queue header. Before other control/bulk transfers can be issued,
- * the programm has to wait for completion. This does not allows asynchronous data transfer.
- *
- * Bulk Transfers
- * --------------
- * Bulk Transfers are issued by filling the tmp_td with the appropriate data and connect
- * them to the qh_bulk queue header. Before other control/bulk transfers can be issued,
- * the programm has to wait for completion. This does not allows asynchronous data transfer.
- *
- *
- */
-
-#include <common.h>
-#include <pci.h>
-
-#ifdef CONFIG_USB_UHCI
-
-#include <usb.h>
-#include "usb_uhci.h"
-
-#define USB_MAX_TEMP_TD 128 /* number of temporary TDs for bulk and control transfers */
-#define USB_MAX_TEMP_INT_TD 32 /* number of temporary TDs for Interrupt transfers */
-
-
-#undef USB_UHCI_DEBUG
-
-#ifdef USB_UHCI_DEBUG
-#define USB_UHCI_PRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#define USB_UHCI_PRINTF(fmt,args...)
-#endif
-
-
-static int irqvec = -1; /* irq vector, if -1 uhci is stopped / reseted */
-unsigned int usb_base_addr; /* base address */
-
-static uhci_td_t td_int[8]; /* Interrupt Transfer descriptors */
-static uhci_qh_t qh_cntrl; /* control Queue Head */
-static uhci_qh_t qh_bulk; /* bulk Queue Head */
-static uhci_qh_t qh_end; /* end Queue Head */
-static uhci_td_t td_last; /* last TD (linked with end chain) */
-
-/* temporary tds */
-static uhci_td_t tmp_td[USB_MAX_TEMP_TD]; /* temporary bulk/control td's */
-static uhci_td_t tmp_int_td[USB_MAX_TEMP_INT_TD]; /* temporary interrupt td's */
-
-static unsigned long framelist[1024] __attribute__ ((aligned (0x1000))); /* frame list */
-
-static struct virt_root_hub rh; /* struct for root hub */
-
-/**********************************************************************
- * some forward decleration
- */
-int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
- void *buffer, int transfer_len,struct devrequest *setup);
-
-/* fill a td with the approproiate data. Link, status, info and buffer
- * are used by the USB controller itselfes, dev is used to identify the
- * "connected" device
- */
-void usb_fill_td(uhci_td_t* td,unsigned long link,unsigned long status,
- unsigned long info, unsigned long buffer, unsigned long dev)
-{
- td->link=swap_32(link);
- td->status=swap_32(status);
- td->info=swap_32(info);
- td->buffer=swap_32(buffer);
- td->dev_ptr=dev;
-}
-
-/* fill a qh with the approproiate data. Head and element are used by the USB controller
- * itselfes. As soon as a valid dev_ptr is filled, a td chain is connected to the qh.
- * Please note, that after completion of the td chain, the entry element is removed /
- * marked invalid by the USB controller.
- */
-void usb_fill_qh(uhci_qh_t* qh,unsigned long head,unsigned long element)
-{
- qh->head=swap_32(head);
- qh->element=swap_32(element);
- qh->dev_ptr=0L;
-}
-
-/* get the status of a td->status
- */
-unsigned long usb_uhci_td_stat(unsigned long status)
-{
- unsigned long result=0;
- result |= (status & TD_CTRL_NAK) ? USB_ST_NAK_REC : 0;
- result |= (status & TD_CTRL_STALLED) ? USB_ST_STALLED : 0;
- result |= (status & TD_CTRL_DBUFERR) ? USB_ST_BUF_ERR : 0;
- result |= (status & TD_CTRL_BABBLE) ? USB_ST_BABBLE_DET : 0;
- result |= (status & TD_CTRL_CRCTIMEO) ? USB_ST_CRC_ERR : 0;
- result |= (status & TD_CTRL_BITSTUFF) ? USB_ST_BIT_ERR : 0;
- result |= (status & TD_CTRL_ACTIVE) ? USB_ST_NOT_PROC : 0;
- return result;
-}
-
-/* get the status and the transferred len of a td chain.
- * called from the completion handler
- */
-int usb_get_td_status(uhci_td_t *td,struct usb_device *dev)
-{
- unsigned long temp,info;
- unsigned long stat;
- uhci_td_t *mytd=td;
-
- if(dev->devnum==rh.devnum)
- return 0;
- dev->act_len=0;
- stat=0;
- do {
- temp=swap_32((unsigned long)mytd->status);
- stat=usb_uhci_td_stat(temp);
- info=swap_32((unsigned long)mytd->info);
- if(((info & 0xff)!= USB_PID_SETUP) &&
- (((info >> 21) & 0x7ff)!= 0x7ff) &&
- (temp & 0x7FF)!=0x7ff)
- { /* if not setup and not null data pack */
- dev->act_len+=(temp & 0x7FF) + 1; /* the transferred len is act_len + 1 */
- }
- if(stat) { /* status no ok */
- dev->status=stat;
- return -1;
- }
- temp=swap_32((unsigned long)mytd->link);
- mytd=(uhci_td_t *)(temp & 0xfffffff0);
- }while((temp & 0x1)==0); /* process all TDs */
- dev->status=stat;
- return 0; /* Ok */
-}
-
-
-/*-------------------------------------------------------------------
- * LOW LEVEL STUFF
- * assembles QHs und TDs for control, bulk and iso
- *-------------------------------------------------------------------*/
-
-/* Submits a control message. That is a Setup, Data and Status transfer.
- * Routine does not wait for completion.
- */
-int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len,struct devrequest *setup)
-{
- unsigned long destination, status;
- int maxsze = usb_maxpacket(dev, pipe);
- unsigned long dataptr;
- int len;
- int pktsze;
- int i=0;
-
- if (!maxsze) {
- USB_UHCI_PRINTF("uhci_submit_control_urb: pipesize for pipe %lx is zero\n", pipe);
- return -1;
- }
- if(((pipe>>8)&0x7f)==rh.devnum) {
- /* this is the root hub -> redirect it */
- return uhci_submit_rh_msg(dev,pipe,buffer,transfer_len,setup);
- }
- USB_UHCI_PRINTF("uhci_submit_control start len %x, maxsize %x\n",transfer_len,maxsze);
- /* The "pipe" thing contains the destination in bits 8--18 */
- destination = (pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP; /* Setup stage */
- /* 3 errors */
- status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27);
- /* (urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD); */
- /* Build the TD for the control request, try forever, 8 bytes of data */
- usb_fill_td(&tmp_td[i],UHCI_PTR_TERM ,status, destination | (7 << 21),(unsigned long)setup,(unsigned long)dev);
-#if 0
- {
- char *sp=(char *)setup;
- printf("SETUP to pipe %lx: %x %x %x %x %x %x %x %x\n", pipe,
- sp[0],sp[1],sp[2],sp[3],sp[4],sp[5],sp[6],sp[7]);
- }
-#endif
- dataptr = (unsigned long)buffer;
- len=transfer_len;
-
- /* If direction is "send", change the frame from SETUP (0x2D)
- to OUT (0xE1). Else change it from SETUP to IN (0x69). */
- destination = (pipe & PIPE_DEVEP_MASK) | ((pipe & USB_DIR_IN)==0 ? USB_PID_OUT : USB_PID_IN);
- while (len > 0) {
- /* data stage */
- pktsze = len;
- i++;
- if (pktsze > maxsze)
- pktsze = maxsze;
- destination ^= 1 << TD_TOKEN_TOGGLE; /* toggle DATA0/1 */
- usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status, destination | ((pktsze - 1) << 21),dataptr,(unsigned long)dev); /* Status, pktsze bytes of data */
- tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]);
-
- dataptr += pktsze;
- len -= pktsze;
- }
-
- /* Build the final TD for control status */
- /* It's only IN if the pipe is out AND we aren't expecting data */
-
- destination &= ~UHCI_PID;
- if (((pipe & USB_DIR_IN)==0) || (transfer_len == 0))
- destination |= USB_PID_IN;
- else
- destination |= USB_PID_OUT;
- destination |= 1 << TD_TOKEN_TOGGLE; /* End in Data1 */
- i++;
- status &=~TD_CTRL_SPD;
- /* no limit on errors on final packet , 0 bytes of data */
- usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status | TD_CTRL_IOC, destination | (UHCI_NULL_DATA_SIZE << 21),0,(unsigned long)dev);
- tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]); /* queue status td */
- /* usb_show_td(i+1);*/
- USB_UHCI_PRINTF("uhci_submit_control end (%d tmp_tds used)\n",i);
- /* first mark the control QH element terminated */
- qh_cntrl.element=0xffffffffL;
- /* set qh active */
- qh_cntrl.dev_ptr=(unsigned long)dev;
- /* fill in tmp_td_chain */
- qh_cntrl.element=swap_32((unsigned long)&tmp_td[0]);
- return 0;
-}
-
-/*-------------------------------------------------------------------
- * Prepare TDs for bulk transfers.
- */
-int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len)
-{
- unsigned long destination, status,info;
- unsigned long dataptr;
- int maxsze = usb_maxpacket(dev, pipe);
- int len;
- int i=0;
-
- if(transfer_len < 0) {
- printf("Negative transfer length in submit_bulk\n");
- return -1;
- }
- if (!maxsze)
- return -1;
- /* The "pipe" thing contains the destination in bits 8--18. */
- destination = (pipe & PIPE_DEVEP_MASK) | usb_packetid (pipe);
- /* 3 errors */
- status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27);
- /* ((urb->transfer_flags & USB_DISABLE_SPD) ? 0 : TD_CTRL_SPD) | (3 << 27); */
- /* Build the TDs for the bulk request */
- len = transfer_len;
- dataptr = (unsigned long)buffer;
- do {
- int pktsze = len;
- if (pktsze > maxsze)
- pktsze = maxsze;
- /* pktsze bytes of data */
- info = destination | (((pktsze - 1)&UHCI_NULL_DATA_SIZE) << 21) |
- (usb_gettoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe)) << TD_TOKEN_TOGGLE);
-
- if((len-pktsze)==0)
- status |= TD_CTRL_IOC; /* last one generates INT */
-
- usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status, info,dataptr,(unsigned long)dev); /* Status, pktsze bytes of data */
- if(i>0)
- tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]);
- i++;
- dataptr += pktsze;
- len -= pktsze;
- usb_dotoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe));
- } while (len > 0);
- /* first mark the bulk QH element terminated */
- qh_bulk.element=0xffffffffL;
- /* set qh active */
- qh_bulk.dev_ptr=(unsigned long)dev;
- /* fill in tmp_td_chain */
- qh_bulk.element=swap_32((unsigned long)&tmp_td[0]);
- return 0;
-}
-
-
-/* search a free interrupt td
- */
-uhci_td_t *uhci_alloc_int_td(void)
-{
- int i;
- for(i=0;i<USB_MAX_TEMP_INT_TD;i++) {
- if(tmp_int_td[i].dev_ptr==0) /* no device assigned -> free TD */
- return &tmp_int_td[i];
- }
- return NULL;
-}
-
-#if 0
-void uhci_show_temp_int_td(void)
-{
- int i;
- for(i=0;i<USB_MAX_TEMP_INT_TD;i++) {
- if((tmp_int_td[i].dev_ptr&0x01)!=0x1L) /* no device assigned -> free TD */
- printf("temp_td %d is assigned to dev %lx\n",i,tmp_int_td[i].dev_ptr);
- }
- printf("all others temp_tds are free\n");
-}
-#endif
-/*-------------------------------------------------------------------
- * submits USB interrupt (ie. polling ;-)
- */
-int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len, int interval)
-{
- int nint, n;
- unsigned long status, destination;
- unsigned long info,tmp;
- uhci_td_t *mytd;
- if (interval < 0 || interval >= 256)
- return -1;
-
- if (interval == 0)
- nint = 0;
- else {
- for (nint = 0, n = 1; nint <= 8; nint++, n += n) /* round interval down to 2^n */
- {
- if(interval < n) {
- interval = n / 2;
- break;
- }
- }
- nint--;
- }
-
- USB_UHCI_PRINTF("Rounded interval to %i, chain %i\n", interval, nint);
- mytd=uhci_alloc_int_td();
- if(mytd==NULL) {
- printf("No free INT TDs found\n");
- return -1;
- }
- status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | TD_CTRL_IOC | (3 << 27);
-/* (urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD) | (3 << 27);
-*/
-
- destination =(pipe & PIPE_DEVEP_MASK) | usb_packetid (pipe) | (((transfer_len - 1) & 0x7ff) << 21);
-
- info = destination | (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)) << TD_TOKEN_TOGGLE);
- tmp = swap_32(td_int[nint].link);
- usb_fill_td(mytd,tmp,status, info,(unsigned long)buffer,(unsigned long)dev);
- /* Link it */
- tmp = swap_32((unsigned long)mytd);
- td_int[nint].link=tmp;
-
- usb_dotoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe));
-
- return 0;
-}
-
-/**********************************************************************
- * Low Level functions
- */
-
-
-void reset_hc(void)
-{
-
- /* Global reset for 100ms */
- out16r( usb_base_addr + USBPORTSC1,0x0204);
- out16r( usb_base_addr + USBPORTSC2,0x0204);
- out16r( usb_base_addr + USBCMD,USBCMD_GRESET | USBCMD_RS);
- /* Turn off all interrupts */
- out16r(usb_base_addr + USBINTR,0);
- mdelay(50);
- out16r( usb_base_addr + USBCMD,0);
- mdelay(10);
-}
-
-void start_hc(void)
-{
- int timeout = 1000;
-
- while(in16r(usb_base_addr + USBCMD) & USBCMD_HCRESET) {
- if (!--timeout) {
- printf("USBCMD_HCRESET timed out!\n");
- break;
- }
- }
- /* Turn on all interrupts */
- out16r(usb_base_addr + USBINTR,USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP);
- /* Start at frame 0 */
- out16r(usb_base_addr + USBFRNUM,0);
- /* set Framebuffer base address */
- out32r(usb_base_addr+USBFLBASEADD,(unsigned long)&framelist);
- /* Run and mark it configured with a 64-byte max packet */
- out16r(usb_base_addr + USBCMD,USBCMD_RS | USBCMD_CF | USBCMD_MAXP);
-}
-
-/* Initialize the skeleton
- */
-void usb_init_skel(void)
-{
- unsigned long temp;
- int n;
-
- for(n=0;n<USB_MAX_TEMP_INT_TD;n++)
- tmp_int_td[n].dev_ptr=0L; /* no devices connected */
- /* last td */
- usb_fill_td(&td_last,UHCI_PTR_TERM,TD_CTRL_IOC ,0,0,0L);
- /* usb_fill_td(&td_last,UHCI_PTR_TERM,0,0,0); */
- /* End Queue Header */
- usb_fill_qh(&qh_end,UHCI_PTR_TERM,(unsigned long)&td_last);
- /* Bulk Queue Header */
- temp=(unsigned long)&qh_end;
- usb_fill_qh(&qh_bulk,temp | UHCI_PTR_QH,UHCI_PTR_TERM);
- /* Control Queue Header */
- temp=(unsigned long)&qh_bulk;
- usb_fill_qh(&qh_cntrl, temp | UHCI_PTR_QH,UHCI_PTR_TERM);
- /* 1ms Interrupt td */
- temp=(unsigned long)&qh_cntrl;
- usb_fill_td(&td_int[0],temp | UHCI_PTR_QH,0,0,0,0L);
- temp=(unsigned long)&td_int[0];
- for(n=1; n<8; n++)
- usb_fill_td(&td_int[n],temp,0,0,0,0L);
- for (n = 0; n < 1024; n++) {
- /* link all framelist pointers to one of the interrupts */
- int m, o;
- if ((n&127)==127)
- framelist[n]= swap_32((unsigned long)&td_int[0]);
- else
- for (o = 1, m = 2; m <= 128; o++, m += m)
- if ((n & (m - 1)) == ((m - 1) / 2))
- framelist[n]= swap_32((unsigned long)&td_int[o]);
- }
-}
-
-/* check the common skeleton for completed transfers, and update the status
- * of the "connected" device. Called from the IRQ routine.
- */
-void usb_check_skel(void)
-{
- struct usb_device *dev;
- /* start with the control qh */
- if(qh_cntrl.dev_ptr!=0) /* it's a device assigned check if this caused IRQ */
- {
- dev=(struct usb_device *)qh_cntrl.dev_ptr;
- usb_get_td_status(&tmp_td[0],dev); /* update status */
- if(!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */
- qh_cntrl.dev_ptr=0;
- }
- }
- /* now process the bulk */
- if(qh_bulk.dev_ptr!=0) /* it's a device assigned check if this caused IRQ */
- {
- dev=(struct usb_device *)qh_bulk.dev_ptr;
- usb_get_td_status(&tmp_td[0],dev); /* update status */
- if(!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */
- qh_bulk.dev_ptr=0;
- }
- }
-}
-
-/* check the interrupt chain, ubdate the status of the appropriate device,
- * call the appropriate irqhandler and reactivate the TD if the irqhandler
- * returns with 1
- */
-void usb_check_int_chain(void)
-{
- int i,res;
- unsigned long link,status;
- struct usb_device *dev;
- uhci_td_t *td,*prevtd;
-
- for(i=0;i<8;i++) {
- prevtd = &td_int[i]; /* the first previous td is the skeleton td */
- link=swap_32(td_int[i].link) & 0xfffffff0; /* next in chain */
- td=(uhci_td_t *)link; /* assign it */
- /* all interrupt TDs are finally linked to the td_int[0].
- * so we process all until we find the td_int[0].
- * if int0 chain points to a QH, we're also done
- */
- while(((i>0) && (link != (unsigned long)&td_int[0])) ||
- ((i==0) && !(swap_32(td->link) & UHCI_PTR_QH)))
- {
- /* check if a device is assigned with this td */
- status=swap_32(td->status);
- if((td->dev_ptr!=0L) && !(status & TD_CTRL_ACTIVE)) {
- /* td is not active and a device is assigned -> call irqhandler */
- dev=(struct usb_device *)td->dev_ptr;
- dev->irq_act_len=((status & 0x7FF)==0x7FF) ? 0 : (status & 0x7FF) + 1; /* transferred length */
- dev->irq_status=usb_uhci_td_stat(status); /* get status */
- res=dev->irq_handle(dev); /* call irqhandler */
- if(res==1) {
- /* reactivate */
- status|=TD_CTRL_ACTIVE;
- td->status=swap_32(status);
- prevtd=td; /* previous td = this td */
- }
- else {
- prevtd->link=td->link; /* link previous td directly to the nex td -> unlinked */
- /* remove device pointer */
- td->dev_ptr=0L;
- }
- } /* if we call the irq handler */
- link=swap_32(td->link) & 0xfffffff0; /* next in chain */
- td=(uhci_td_t *)link; /* assign it */
- } /* process all td in this int chain */
- } /* next interrupt chain */
-}
-
-
-/* usb interrupt service routine.
- */
-void handle_usb_interrupt(void)
-{
- unsigned short status;
-
- /*
- * Read the interrupt status, and write it back to clear the
- * interrupt cause
- */
-
- status = in16r(usb_base_addr + USBSTS);
-
- if (!status) /* shared interrupt, not mine */
- return;
- if (status != 1) {
- /* remove host controller halted state */
- if ((status&0x20) && ((in16r(usb_base_addr+USBCMD) && USBCMD_RS)==0)) {
- out16r(usb_base_addr + USBCMD, USBCMD_RS | in16r(usb_base_addr + USBCMD));
- }
- }
- usb_check_int_chain(); /* call interrupt handlers for int tds */
- usb_check_skel(); /* call completion handler for common transfer routines */
- out16r(usb_base_addr+USBSTS,status);
-}
-
-
-/* init uhci
- */
-int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
-{
- unsigned char temp;
- int busdevfunc;
-
- busdevfunc=pci_find_device(USB_UHCI_VEND_ID,USB_UHCI_DEV_ID,0); /* get PCI Device ID */
- if(busdevfunc==-1) {
- printf("Error USB UHCI (%04X,%04X) not found\n",USB_UHCI_VEND_ID,USB_UHCI_DEV_ID);
- return -1;
- }
- pci_read_config_byte(busdevfunc,PCI_INTERRUPT_LINE,&temp);
- irqvec = temp;
- irq_free_handler(irqvec);
- USB_UHCI_PRINTF("Interrupt Line = %d, is %d\n",irqvec);
- pci_read_config_byte(busdevfunc,PCI_INTERRUPT_PIN,&temp);
- USB_UHCI_PRINTF("Interrupt Pin = %ld\n",temp);
- pci_read_config_dword(busdevfunc,PCI_BASE_ADDRESS_4,&usb_base_addr);
- USB_UHCI_PRINTF("IO Base Address = 0x%lx\n",usb_base_addr);
- usb_base_addr&=0xFFFFFFF0;
- usb_base_addr+=CONFIG_SYS_ISA_IO_BASE_ADDRESS;
- rh.devnum = 0;
- usb_init_skel();
- reset_hc();
- start_hc();
- irq_install_handler(irqvec, (interrupt_handler_t *)handle_usb_interrupt, NULL);
- return 0;
-}
-
-/* stop uhci
- */
-int usb_lowlevel_stop(int index)
-{
- if(irqvec==-1)
- return 1;
- irq_free_handler(irqvec);
- reset_hc();
- irqvec = -1;
- return 0;
-}
-
-/*******************************************************************************************
- * Virtual Root Hub
- * Since the uhci does not have a real HUB, we simulate one ;-)
- */
-#undef USB_RH_DEBUG
-
-#ifdef USB_RH_DEBUG
-#define USB_RH_PRINTF(fmt,args...) printf (fmt ,##args)
-static void usb_display_wValue(unsigned short wValue,unsigned short wIndex);
-static void usb_display_Req(unsigned short req);
-#else
-#define USB_RH_PRINTF(fmt,args...)
-static void usb_display_wValue(unsigned short wValue,unsigned short wIndex) {}
-static void usb_display_Req(unsigned short req) {}
-#endif
-
-#define WANT_USB_ROOT_HUB_HUB_DES
-#include <usbroothubdes.h>
-#undef WANT_USB_ROOT_HUB_HUB_DES
-
-/*
- * Root Hub Control Pipe (interrupt Pipes are not supported)
- */
-
-
-int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len,struct devrequest *cmd)
-{
- void *data = buffer;
- int leni = transfer_len;
- int len = 0;
- int status = 0;
- int stat = 0;
- int i;
-
- unsigned short cstatus;
-
- unsigned short bmRType_bReq;
- unsigned short wValue;
- unsigned short wIndex;
- unsigned short wLength;
-
- if (usb_pipeint(pipe)) {
- printf("Root-Hub submit IRQ: NOT implemented\n");
-#if 0
- uhci->rh.urb = urb;
- uhci->rh.send = 1;
- uhci->rh.interval = urb->interval;
- rh_init_int_timer (urb);
-#endif
- return 0;
- }
- bmRType_bReq = cmd->requesttype | cmd->request << 8;
- wValue = swap_16(cmd->value);
- wIndex = swap_16(cmd->index);
- wLength = swap_16(cmd->length);
- usb_display_Req(bmRType_bReq);
- for (i = 0; i < 8; i++)
- rh.c_p_r[i] = 0;
- USB_RH_PRINTF("Root-Hub: adr: %2x cmd(%1x): %02x%02x %04x %04x %04x\n",
- dev->devnum, 8, cmd->requesttype,cmd->request, wValue, wIndex, wLength);
-
- switch (bmRType_bReq) {
- /* Request Destination:
- without flags: Device,
- RH_INTERFACE: interface,
- RH_ENDPOINT: endpoint,
- RH_CLASS means HUB here,
- RH_OTHER | RH_CLASS almost ever means HUB_PORT here
- */
-
- case RH_GET_STATUS:
- *(unsigned short *) data = swap_16(1);
- len=2;
- break;
- case RH_GET_STATUS | RH_INTERFACE:
- *(unsigned short *) data = swap_16(0);
- len=2;
- break;
- case RH_GET_STATUS | RH_ENDPOINT:
- *(unsigned short *) data = swap_16(0);
- len=2;
- break;
- case RH_GET_STATUS | RH_CLASS:
- *(unsigned long *) data = swap_32(0);
- len=4;
- break; /* hub power ** */
- case RH_GET_STATUS | RH_OTHER | RH_CLASS:
-
- status = in16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1));
- cstatus = ((status & USBPORTSC_CSC) >> (1 - 0)) |
- ((status & USBPORTSC_PEC) >> (3 - 1)) |
- (rh.c_p_r[wIndex - 1] << (0 + 4));
- status = (status & USBPORTSC_CCS) |
- ((status & USBPORTSC_PE) >> (2 - 1)) |
- ((status & USBPORTSC_SUSP) >> (12 - 2)) |
- ((status & USBPORTSC_PR) >> (9 - 4)) |
- (1 << 8) | /* power on ** */
- ((status & USBPORTSC_LSDA) << (-8 + 9));
-
- *(unsigned short *) data = swap_16(status);
- *(unsigned short *) (data + 2) = swap_16(cstatus);
- len=4;
- break;
- case RH_CLEAR_FEATURE | RH_ENDPOINT:
- switch (wValue) {
- case (RH_ENDPOINT_STALL):
- len=0;
- break;
- }
- break;
-
- case RH_CLEAR_FEATURE | RH_CLASS:
- switch (wValue) {
- case (RH_C_HUB_OVER_CURRENT):
- len=0; /* hub power over current ** */
- break;
- }
- break;
-
- case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
- usb_display_wValue(wValue,wIndex);
- switch (wValue) {
- case (RH_PORT_ENABLE):
- status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
- status = (status & 0xfff5) & ~USBPORTSC_PE;
- out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
- len=0;
- break;
- case (RH_PORT_SUSPEND):
- status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
- status = (status & 0xfff5) & ~USBPORTSC_SUSP;
- out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
- len=0;
- break;
- case (RH_PORT_POWER):
- len=0; /* port power ** */
- break;
- case (RH_C_PORT_CONNECTION):
- status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
- status = (status & 0xfff5) | USBPORTSC_CSC;
- out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
- len=0;
- break;
- case (RH_C_PORT_ENABLE):
- status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
- status = (status & 0xfff5) | USBPORTSC_PEC;
- out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
- len=0;
- break;
- case (RH_C_PORT_SUSPEND):
-/*** WR_RH_PORTSTAT(RH_PS_PSSC); */
- len=0;
- break;
- case (RH_C_PORT_OVER_CURRENT):
- len=0;
- break;
- case (RH_C_PORT_RESET):
- rh.c_p_r[wIndex - 1] = 0;
- len=0;
- break;
- }
- break;
- case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
- usb_display_wValue(wValue,wIndex);
- switch (wValue) {
- case (RH_PORT_SUSPEND):
- status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
- status = (status & 0xfff5) | USBPORTSC_SUSP;
- out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
- len=0;
- break;
- case (RH_PORT_RESET):
- status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
- status = (status & 0xfff5) | USBPORTSC_PR;
- out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
- mdelay(10);
- status = (status & 0xfff5) & ~USBPORTSC_PR;
- out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
- udelay(10);
- status = (status & 0xfff5) | USBPORTSC_PE;
- out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
- mdelay(10);
- status = (status & 0xfff5) | 0xa;
- out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
- len=0;
- break;
- case (RH_PORT_POWER):
- len=0; /* port power ** */
- break;
- case (RH_PORT_ENABLE):
- status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
- status = (status & 0xfff5) | USBPORTSC_PE;
- out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
- len=0;
- break;
- }
- break;
-
- case RH_SET_ADDRESS:
- rh.devnum = wValue;
- len=0;
- break;
- case RH_GET_DESCRIPTOR:
- switch ((wValue & 0xff00) >> 8) {
- case (0x01): /* device descriptor */
- i=sizeof(root_hub_config_des);
- status=i > wLength ? wLength : i;
- len = leni > status ? status : leni;
- memcpy (data, root_hub_dev_des, len);
- break;
- case (0x02): /* configuration descriptor */
- i=sizeof(root_hub_config_des);
- status=i > wLength ? wLength : i;
- len = leni > status ? status : leni;
- memcpy (data, root_hub_config_des, len);
- break;
- case (0x03): /*string descriptors */
- if(wValue==0x0300) {
- i=sizeof(root_hub_str_index0);
- status = i > wLength ? wLength : i;
- len = leni > status ? status : leni;
- memcpy (data, root_hub_str_index0, len);
- break;
- }
- if(wValue==0x0301) {
- i=sizeof(root_hub_str_index1);
- status = i > wLength ? wLength : i;
- len = leni > status ? status : leni;
- memcpy (data, root_hub_str_index1, len);
- break;
- }
- stat = USB_ST_STALLED;
- }
- break;
-
- case RH_GET_DESCRIPTOR | RH_CLASS:
- root_hub_hub_des[2] = 2;
- i=sizeof(root_hub_hub_des);
- status= i > wLength ? wLength : i;
- len = leni > status ? status : leni;
- memcpy (data, root_hub_hub_des, len);
- break;
- case RH_GET_CONFIGURATION:
- *(unsigned char *) data = 0x01;
- len = 1;
- break;
- case RH_SET_CONFIGURATION:
- len=0;
- break;
- default:
- stat = USB_ST_STALLED;
- }
- USB_RH_PRINTF("Root-Hub stat %lx port1: %x port2: %x\n\n",stat,
- in16r(usb_base_addr + USBPORTSC1), in16r(usb_base_addr + USBPORTSC2));
- dev->act_len=len;
- dev->status=stat;
- return stat;
-
-}
-
-/********************************************************************************
- * Some Debug Routines
- */
-
-#ifdef USB_RH_DEBUG
-
-static void usb_display_Req(unsigned short req)
-{
- USB_RH_PRINTF("- Root-Hub Request: ");
- switch (req) {
- case RH_GET_STATUS:
- USB_RH_PRINTF("Get Status ");
- break;
- case RH_GET_STATUS | RH_INTERFACE:
- USB_RH_PRINTF("Get Status Interface ");
- break;
- case RH_GET_STATUS | RH_ENDPOINT:
- USB_RH_PRINTF("Get Status Endpoint ");
- break;
- case RH_GET_STATUS | RH_CLASS:
- USB_RH_PRINTF("Get Status Class");
- break; /* hub power ** */
- case RH_GET_STATUS | RH_OTHER | RH_CLASS:
- USB_RH_PRINTF("Get Status Class Others");
- break;
- case RH_CLEAR_FEATURE | RH_ENDPOINT:
- USB_RH_PRINTF("Clear Feature Endpoint ");
- break;
- case RH_CLEAR_FEATURE | RH_CLASS:
- USB_RH_PRINTF("Clear Feature Class ");
- break;
- case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
- USB_RH_PRINTF("Clear Feature Other Class ");
- break;
- case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
- USB_RH_PRINTF("Set Feature Other Class ");
- break;
- case RH_SET_ADDRESS:
- USB_RH_PRINTF("Set Address ");
- break;
- case RH_GET_DESCRIPTOR:
- USB_RH_PRINTF("Get Descriptor ");
- break;
- case RH_GET_DESCRIPTOR | RH_CLASS:
- USB_RH_PRINTF("Get Descriptor Class ");
- break;
- case RH_GET_CONFIGURATION:
- USB_RH_PRINTF("Get Configuration ");
- break;
- case RH_SET_CONFIGURATION:
- USB_RH_PRINTF("Get Configuration ");
- break;
- default:
- USB_RH_PRINTF("****UNKNOWN**** 0x%04X ",req);
- }
- USB_RH_PRINTF("\n");
-
-}
-
-static void usb_display_wValue(unsigned short wValue,unsigned short wIndex)
-{
- switch (wValue) {
- case (RH_PORT_ENABLE):
- USB_RH_PRINTF("Root-Hub: Enable Port %d\n",wIndex);
- break;
- case (RH_PORT_SUSPEND):
- USB_RH_PRINTF("Root-Hub: Suspend Port %d\n",wIndex);
- break;
- case (RH_PORT_POWER):
- USB_RH_PRINTF("Root-Hub: Port Power %d\n",wIndex);
- break;
- case (RH_C_PORT_CONNECTION):
- USB_RH_PRINTF("Root-Hub: C Port Connection Port %d\n",wIndex);
- break;
- case (RH_C_PORT_ENABLE):
- USB_RH_PRINTF("Root-Hub: C Port Enable Port %d\n",wIndex);
- break;
- case (RH_C_PORT_SUSPEND):
- USB_RH_PRINTF("Root-Hub: C Port Suspend Port %d\n",wIndex);
- break;
- case (RH_C_PORT_OVER_CURRENT):
- USB_RH_PRINTF("Root-Hub: C Port Over Current Port %d\n",wIndex);
- break;
- case (RH_C_PORT_RESET):
- USB_RH_PRINTF("Root-Hub: C Port reset Port %d\n",wIndex);
- break;
- default:
- USB_RH_PRINTF("Root-Hub: unknown %x %x\n",wValue,wIndex);
- break;
- }
-}
-
-#endif
-
-
-#ifdef USB_UHCI_DEBUG
-
-static int usb_display_td(uhci_td_t *td)
-{
- unsigned long tmp;
- int valid;
-
- printf("TD at %p:\n",td);
-
- tmp=swap_32(td->link);
- printf("Link points to 0x%08lX, %s first, %s, %s\n",tmp&0xfffffff0,
- ((tmp & 0x4)==0x4) ? "Depth" : "Breath",
- ((tmp & 0x2)==0x2) ? "QH" : "TD",
- ((tmp & 0x1)==0x1) ? "invalid" : "valid");
- valid=((tmp & 0x1)==0x0);
- tmp=swap_32(td->status);
- printf(" %s %ld Errors %s %s %s \n %s %s %s %s %s %s\n Len 0x%lX\n",
- (((tmp>>29)&0x1)==0x1) ? "SPD Enable" : "SPD Disable",
- ((tmp>>28)&0x3),
- (((tmp>>26)&0x1)==0x1) ? "Low Speed" : "Full Speed",
- (((tmp>>25)&0x1)==0x1) ? "ISO " : "",
- (((tmp>>24)&0x1)==0x1) ? "IOC " : "",
- (((tmp>>23)&0x1)==0x1) ? "Active " : "Inactive ",
- (((tmp>>22)&0x1)==0x1) ? "Stalled" : "",
- (((tmp>>21)&0x1)==0x1) ? "Data Buffer Error" : "",
- (((tmp>>20)&0x1)==0x1) ? "Babble" : "",
- (((tmp>>19)&0x1)==0x1) ? "NAK" : "",
- (((tmp>>18)&0x1)==0x1) ? "Bitstuff Error" : "",
- (tmp&0x7ff));
- tmp=swap_32(td->info);
- printf(" MaxLen 0x%lX\n",((tmp>>21)&0x7FF));
- printf(" %s Endpoint 0x%lX Dev Addr 0x%lX PID 0x%lX\n",((tmp>>19)&0x1)==0x1 ? "TOGGLE" : "",
- ((tmp>>15)&0xF),((tmp>>8)&0x7F),tmp&0xFF);
- tmp=swap_32(td->buffer);
- printf(" Buffer 0x%08lX\n",tmp);
- printf(" DEV %08lX\n",td->dev_ptr);
- return valid;
-}
-
-
-void usb_show_td(int max)
-{
- int i;
- if(max>0) {
- for(i=0;i<max;i++) {
- usb_display_td(&tmp_td[i]);
- }
- }
- else {
- i=0;
- do {
- printf("tmp_td[%d]\n",i);
- }while(usb_display_td(&tmp_td[i++]));
- }
-}
-
-
-#endif
-#endif /* CONFIG_USB_UHCI */
-
-/* EOF */
diff --git a/board/mpl/common/usb_uhci.h b/board/mpl/common/usb_uhci.h
deleted file mode 100644
index 582015f..0000000
--- a/board/mpl/common/usb_uhci.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Note: Part of this code has been derived from linux
- */
-#ifndef _USB_UHCI_H_
-#define _USB_UHCI_H_
-
-
-/* Command register */
-#define USBCMD 0
-#define USBCMD_RS 0x0001 /* Run/Stop */
-#define USBCMD_HCRESET 0x0002 /* Host reset */
-#define USBCMD_GRESET 0x0004 /* Global reset */
-#define USBCMD_EGSM 0x0008 /* Global Suspend Mode */
-#define USBCMD_FGR 0x0010 /* Force Global Resume */
-#define USBCMD_SWDBG 0x0020 /* SW Debug mode */
-#define USBCMD_CF 0x0040 /* Config Flag (sw only) */
-#define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */
-
-/* Status register */
-#define USBSTS 2
-#define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */
-#define USBSTS_ERROR 0x0002 /* Interrupt due to error */
-#define USBSTS_RD 0x0004 /* Resume Detect */
-#define USBSTS_HSE 0x0008 /* Host System Error - basically PCI problems */
-#define USBSTS_HCPE 0x0010 /* Host Controller Process Error - the scripts were buggy */
-#define USBSTS_HCH 0x0020 /* HC Halted */
-
-/* Interrupt enable register */
-#define USBINTR 4
-#define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */
-#define USBINTR_RESUME 0x0002 /* Resume interrupt enable */
-#define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */
-#define USBINTR_SP 0x0008 /* Short packet interrupt enable */
-
-#define USBFRNUM 6
-#define USBFLBASEADD 8
-#define USBSOF 12
-
-/* USB port status and control registers */
-#define USBPORTSC1 16
-#define USBPORTSC2 18
-#define USBPORTSC_CCS 0x0001 /* Current Connect Status ("device present") */
-#define USBPORTSC_CSC 0x0002 /* Connect Status Change */
-#define USBPORTSC_PE 0x0004 /* Port Enable */
-#define USBPORTSC_PEC 0x0008 /* Port Enable Change */
-#define USBPORTSC_LS 0x0030 /* Line Status */
-#define USBPORTSC_RD 0x0040 /* Resume Detect */
-#define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */
-#define USBPORTSC_PR 0x0200 /* Port Reset */
-#define USBPORTSC_SUSP 0x1000 /* Suspend */
-
-/* Legacy support register */
-#define USBLEGSUP 0xc0
-#define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
-
-#define UHCI_NULL_DATA_SIZE 0x7ff /* for UHCI controller TD */
-#define UHCI_PID 0xff /* PID MASK */
-
-#define UHCI_PTR_BITS 0x000F
-#define UHCI_PTR_TERM 0x0001
-#define UHCI_PTR_QH 0x0002
-#define UHCI_PTR_DEPTH 0x0004
-
-/* for TD <status>: */
-#define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */
-#define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */
-#define TD_CTRL_LS (1 << 26) /* Low Speed Device */
-#define TD_CTRL_IOS (1 << 25) /* Isochronous Select */
-#define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */
-#define TD_CTRL_ACTIVE (1 << 23) /* TD Active */
-#define TD_CTRL_STALLED (1 << 22) /* TD Stalled */
-#define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */
-#define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */
-#define TD_CTRL_NAK (1 << 19) /* NAK Received */
-#define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */
-#define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */
-#define TD_CTRL_ACTLEN_MASK 0x7ff /* actual length, encoded as n - 1 */
-
-#define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
- TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF)
-
-#define TD_TOKEN_TOGGLE 19
-
-/* ------------------------------------------------------------------------------------
- Virtual Root HUB
- ------------------------------------------------------------------------------------ */
-/* destination of request */
-#define RH_INTERFACE 0x01
-#define RH_ENDPOINT 0x02
-#define RH_OTHER 0x03
-
-#define RH_CLASS 0x20
-#define RH_VENDOR 0x40
-
-/* Requests: bRequest << 8 | bmRequestType */
-#define RH_GET_STATUS 0x0080
-#define RH_CLEAR_FEATURE 0x0100
-#define RH_SET_FEATURE 0x0300
-#define RH_SET_ADDRESS 0x0500
-#define RH_GET_DESCRIPTOR 0x0680
-#define RH_SET_DESCRIPTOR 0x0700
-#define RH_GET_CONFIGURATION 0x0880
-#define RH_SET_CONFIGURATION 0x0900
-#define RH_GET_STATE 0x0280
-#define RH_GET_INTERFACE 0x0A80
-#define RH_SET_INTERFACE 0x0B00
-#define RH_SYNC_FRAME 0x0C80
-/* Our Vendor Specific Request */
-#define RH_SET_EP 0x2000
-
-/* Hub port features */
-#define RH_PORT_CONNECTION 0x00
-#define RH_PORT_ENABLE 0x01
-#define RH_PORT_SUSPEND 0x02
-#define RH_PORT_OVER_CURRENT 0x03
-#define RH_PORT_RESET 0x04
-#define RH_PORT_POWER 0x08
-#define RH_PORT_LOW_SPEED 0x09
-#define RH_C_PORT_CONNECTION 0x10
-#define RH_C_PORT_ENABLE 0x11
-#define RH_C_PORT_SUSPEND 0x12
-#define RH_C_PORT_OVER_CURRENT 0x13
-#define RH_C_PORT_RESET 0x14
-
-/* Hub features */
-#define RH_C_HUB_LOCAL_POWER 0x00
-#define RH_C_HUB_OVER_CURRENT 0x01
-
-#define RH_DEVICE_REMOTE_WAKEUP 0x00
-#define RH_ENDPOINT_STALL 0x01
-
-/* Our Vendor Specific feature */
-#define RH_REMOVE_EP 0x00
-
-
-#define RH_ACK 0x01
-#define RH_REQ_ERR -1
-#define RH_NACK 0x00
-
-
-/* Transfer descriptor structure */
-typedef struct {
- unsigned long link; /* next td/qh (LE)*/
- unsigned long status; /* status of the td */
- unsigned long info; /* Max Lenght / Endpoint / device address and PID */
- unsigned long buffer; /* pointer to data buffer (LE) */
- unsigned long dev_ptr; /* pointer to the assigned device (BE) */
- unsigned long res[3]; /* reserved (TDs must be 8Byte aligned) */
-} uhci_td_t, *puhci_td_t;
-
-/* Queue Header structure */
-typedef struct {
- unsigned long head; /* Next QH (LE)*/
- unsigned long element; /* Queue element pointer (LE) */
- unsigned long res[5]; /* reserved */
- unsigned long dev_ptr; /* if 0 no tds have been assigned to this qh */
-} uhci_qh_t, *puhci_qh_t;
-
-struct virt_root_hub {
- int devnum; /* Address of Root Hub endpoint */
- int numports; /* number of ports */
- int c_p_r[8]; /* C_PORT_RESET */
-};
-
-
-#endif /* _USB_UHCI_H_ */
diff --git a/board/mpl/mip405/Kconfig b/board/mpl/mip405/Kconfig
deleted file mode 100644
index e003a43..0000000
--- a/board/mpl/mip405/Kconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-if TARGET_MIP405 || TARGET_MIP405T
-
-config SYS_BOARD
- default "mip405"
-
-config SYS_VENDOR
- default "mpl"
-
-config SYS_CONFIG_NAME
- default "MIP405"
-
-config ISO_STRING
- string
- default "MEV-10082-001" if TARGET_MIP405T
- default "MEV-10072-001" if TARGET_MIP405
-
-endif
diff --git a/board/mpl/mip405/MAINTAINERS b/board/mpl/mip405/MAINTAINERS
deleted file mode 100644
index b323e5a..0000000
--- a/board/mpl/mip405/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MIP405 BOARD
-M: Denis Peter <d.peter@mpl.ch>
-S: Maintained
-F: board/mpl/mip405/
-F: include/configs/MIP405.h
-F: configs/MIP405_defconfig
-F: configs/MIP405T_defconfig
diff --git a/board/mpl/mip405/Makefile b/board/mpl/mip405/Makefile
deleted file mode 100644
index 5bcf130..0000000
--- a/board/mpl/mip405/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = mip405.o cmd_mip405.o \
- ../common/pci.o \
- ../common/usb_uhci.o \
- ../common/common_util.o
-obj-y += init.o
diff --git a/board/mpl/mip405/cmd_mip405.c b/board/mpl/mip405/cmd_mip405.c
deleted file mode 100644
index ca6f0af..0000000
--- a/board/mpl/mip405/cmd_mip405.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * hacked for MIP405
- */
-
-#include <common.h>
-#include <command.h>
-#include "mip405.h"
-#include "../common/common_util.h"
-
-
-extern void print_mip405_info(void);
-extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
-
-/* ------------------------------------------------------------------------- */
-
-int do_mip405(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-
- ulong led_on;
-
- if (strcmp(argv[1], "info") == 0)
- {
- print_mip405_info();
- return 0;
- }
- if (strcmp(argv[1], "led") == 0)
- {
- led_on = (ulong)simple_strtoul(argv[2], NULL, 10);
- user_led0(led_on);
- return 0;
- }
- return (do_mplcommon(cmdtp, flag, argc, argv));
-}
-U_BOOT_CMD(
- mip405, 8, 1, do_mip405,
- "MIP405 specific Cmds",
- "flash mem [SrcAddr] - updates U-Boot with image in memory\n"
- "mip405 flash mps - updates U-Boot with image from MPS\n"
- "mip405 info - displays board information\n"
- "mip405 led <on> - switches LED on (on=1) or off (on=0)"
-);
-
-/* ------------------------------------------------------------------------- */
diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S
deleted file mode 100644
index 2ea2e29..0000000
--- a/board/mpl/mip405/init.S
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- * SPDX-License-Identifier: GPL-2.0 IBM-pibs
- */
-/*-----------------------------------------------------------------------------
- * Function: ext_bus_cntlr_init
- * Description: Initializes the External Bus Controller for the external
- * peripherals. IMPORTANT: For pass1 this code must run from
- * cache since you can not reliably change a peripheral banks
- * timing register (pbxap) while running code from that bank.
- * For ex., since we are running from ROM on bank 0, we can NOT
- * execute the code that modifies bank 0 timings from ROM, so
- * we run it from cache.
- * Bank 0 - Flash or Multi Purpose Socket
- * Bank 1 - Multi Purpose Socket or Flash (set in C-Code)
- * Bank 2 - UART 1 (set in C-Code)
- * Bank 3 - UART 2 (set in C-Code)
- * Bank 4 - not used
- * Bank 5 - not used
- * Bank 6 - not used
- * Bank 7 - PLD Register
- *-----------------------------------------------------------------------------*/
-
-#include <configs/MIP405.h>
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <asm/ppc4xx.h>
-#include "mip405.h"
-
-
- .globl ext_bus_cntlr_init
-ext_bus_cntlr_init:
- mflr r4 /* save link register */
- mfdcr r3,CPC0_PSR /* get strapping reg */
- andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */
- bnelr /* jump back if PCI boot */
-
- bl ..getAddr
-..getAddr:
- mflr r3 /* get address of ..getAddr */
- mtlr r4 /* restore link register */
- addi r4,0,14 /* set ctr to 14; used to prefetch */
- mtctr r4 /* 14 cache lines to fit this function */
- /* in cache (gives us 8x14=112 instrctns) */
-..ebcloop:
- icbt r0,r3 /* prefetch cache line for addr in r3 */
- addi r3,r3,32 /* move to next cache line */
- bdnz ..ebcloop /* continue for 14 cache lines */
-
- /*-------------------------------------------------------------------
- * Delay to ensure all accesses to ROM are complete before changing
- * bank 0 timings.
- *------------------------------------------------------------------- */
- addis r3,0,0x0
- ori r3,r3,0xA000
- mtctr r3
-..spinlp:
- bdnz ..spinlp /* spin loop */
-
- /*-----------------------------------------------------------------------
- * decide boot up mode
- *----------------------------------------------------------------------- */
- addi r4,0,PB0CR
- mtdcr EBC0_CFGADDR,r4
- mfdcr r4,EBC0_CFGDATA
-
- andi. r0, r4, 0x2000 /* mask out irrelevant bits */
- beq 0f /* jump if 8 bit bus width */
-
- /* setup 16 bit things
- *-----------------------------------------------------------------------
- * Memory Bank 0 (16 Bit Flash) initialization
- *---------------------------------------------------------------------- */
-
- addi r4,0,PB1AP
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,(FLASH_AP_B)@h
- ori r4,r4,(FLASH_AP_B)@l
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB0CR
- mtdcr EBC0_CFGADDR,r4
- /* BS=0x010(4MB),BU=0x3(R/W), */
- addis r4,0,(FLASH_CR_B)@h
- ori r4,r4,(FLASH_CR_B)@l
- mtdcr EBC0_CFGDATA,r4
- b 1f
-
-0:
-
- /* 8Bit boot mode: */
- /*-----------------------------------------------------------------------
- * Memory Bank 0 Multi Purpose Socket initialization
- *----------------------------------------------------------------------- */
- /* 0x7F8FFE80 slowest boot */
- addi r4,0,PB1AP
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,(MPS_AP_B)@h
- ori r4,r4,(MPS_AP_B)@l
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB0CR
- mtdcr EBC0_CFGADDR,r4
- /* BS=0x010(4MB),BU=0x3(R/W), */
- addis r4,0,(MPS_CR_B)@h
- ori r4,r4,(MPS_CR_B)@l
-
- mtdcr EBC0_CFGDATA,r4
-
-
-1:
- /*-----------------------------------------------------------------------
- * Memory Bank 2-3-4-5-6 (not used) initialization
- *-----------------------------------------------------------------------*/
- addi r4,0,PB1CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB2CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB3CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB4CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB5CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB6CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB7CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
- nop /* pass2 DCR errata #8 */
- blr
-
-#if defined(CONFIG_BOOT_PCI)
- .section .bootpg,"ax"
- .globl _start_pci
-/*******************************************
- */
-
-_start_pci:
- /* first handle errata #68 / PCI_18 */
- iccci r0, r0 /* invalidate I-cache */
- lis r31, 0
- mticcr r31 /* ICCR = 0 (all uncachable) */
- isync
-
- mfccr0 r28 /* set CCR0[24] = 1 */
- ori r28, r28, 0x0080
- mtccr0 r28
-
- /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
- lis r28, 0xEF40
- addi r28, r28, 0x0004
- stw r31, 0x0C(r28) /* clear PMM0PCIHA */
- lis r29, 0xFFF8 /* open 512 kByte */
- addi r29, r29, 0x0001/* and enable this region */
- stwbrx r29, r0, r28 /* write PMM0MA */
-
- lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */
- addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */
-
- lis r31, 0x8000 /* set en bit bus 0 */
- ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
- stwbrx r31, r0, r28 /* write it */
-
- lwbrx r31, r0, r29 /* load XBCS register */
- oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
- stwbrx r31, r0, r29 /* write back XBCS register */
-
- nop
- nop
- b _start /* normal start */
-#endif
diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c
deleted file mode 100644
index 4d8671f..0000000
--- a/board/mpl/mip405/mip405.c
+++ /dev/null
@@ -1,805 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * TODO: clean-up
- */
-
-/*
- * How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM?
- *
- * As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being
- * used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum
- * parameters from the datasheet are:
- * Tclk = 7.5ns (CL = 2)
- * Trp = 15ns
- * Trc = 60ns
- * Trcd = 15ns
- * Trfc = 66ns
- *
- * If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock
- * period is 10ns and the parameters needed for the Timing Register are:
- * CASL = CL = 2 clock cycles
- * PTA = Trp = 15ns / 10ns = 2 clock cycles
- * CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles
- * LDF = 2 clock cycles (but can be extended to meet board-level timing)
- * RFTA = Trfc = 66ns / 10ns= 7 clock cycles
- * RCD = Trcd = 15ns / 10ns= 2 clock cycles
- *
- * The actual bit settings in the register would be:
- *
- * CASL = 0b01
- * PTA = 0b01
- * CTP = 0b10
- * LDF = 0b01
- * RFTA = 0b011
- * RCD = 0b01
- *
- * If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc
- * instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay
- * defined as Trc rather than Trfc.
- * When using DIMM modules, most but not all of the required timing parameters can be read
- * from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc
- * are not available from the EEPROM
- */
-
-#include <common.h>
-#include "mip405.h"
-#include <asm/processor.h>
-#include <asm/ppc4xx.h>
-#include <asm/ppc4xx-i2c.h>
-#include <miiphy.h>
-#include "../common/common_util.h"
-#include <stdio_dev.h>
-#include <i2c.h>
-#include <rtc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#undef SDRAM_DEBUG
-#define ENABLE_ECC /* for ecc boards */
-
-/* stdlib.h causes some compatibility problems; should fixe these! -- wd */
-#ifndef __ldiv_t_defined
-typedef struct {
- long int quot; /* Quotient */
- long int rem; /* Remainder */
-} ldiv_t;
-extern ldiv_t ldiv (long int __numer, long int __denom);
-# define __ldiv_t_defined 1
-#endif
-
-
-#define PLD_PART_REG PER_PLD_ADDR + 0
-#define PLD_VERS_REG PER_PLD_ADDR + 1
-#define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2
-#define PLD_IRQ_REG PER_PLD_ADDR + 3
-#define PLD_COM_MODE_REG PER_PLD_ADDR + 4
-#define PLD_EXT_CONF_REG PER_PLD_ADDR + 5
-
-#define MEGA_BYTE (1024*1024)
-
-typedef struct {
- unsigned char boardtype; /* Board revision and Population Options */
- unsigned char cal; /* cas Latency (will be programmend as cal-1) */
- unsigned char trp; /* datain27 in clocks */
- unsigned char trcd; /* datain29 in clocks */
- unsigned char tras; /* datain30 in clocks */
- unsigned char tctp; /* tras - trcd in clocks */
- unsigned char am; /* Address Mod (will be programmed as am-1) */
- unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
- unsigned char ecc; /* if true, ecc is enabled */
-} sdram_t;
-#if defined(CONFIG_TARGET_MIP405T)
-const sdram_t sdram_table[] = {
- { 0x0F, /* MIP405T Rev A, 64MByte -1 Board */
- 3, /* Case Latenty = 3 */
- 3, /* trp 20ns / 7.5 ns datain[27] */
- 3, /* trcd 20ns /7.5 ns (datain[29]) */
- 6, /* tras 44ns /7.5 ns (datain[30]) */
- 4, /* tcpt 44 - 20ns = 24ns */
- 2, /* Address Mode = 2 (12x9x4) */
- 3, /* size value (32MByte) */
- 0}, /* ECC disabled */
- { 0xff, /* terminator */
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff }
-};
-#else
-const sdram_t sdram_table[] = {
- { 0x0f, /* Rev A, 128MByte -1 Board */
- 3, /* Case Latenty = 3 */
- 3, /* trp 20ns / 7.5 ns datain[27] */
- 3, /* trcd 20ns /7.5 ns (datain[29]) */
- 6, /* tras 44ns /7.5 ns (datain[30]) */
- 4, /* tcpt 44 - 20ns = 24ns */
- 3, /* Address Mode = 3 */
- 5, /* size value */
- 1}, /* ECC enabled */
- { 0x07, /* Rev A, 64MByte -2 Board */
- 3, /* Case Latenty = 3 */
- 3, /* trp 20ns / 7.5 ns datain[27] */
- 3, /* trcd 20ns /7.5 ns (datain[29]) */
- 6, /* tras 44ns /7.5 ns (datain[30]) */
- 4, /* tcpt 44 - 20ns = 24ns */
- 2, /* Address Mode = 2 */
- 4, /* size value */
- 1}, /* ECC enabled */
- { 0x03, /* Rev A, 128MByte -4 Board */
- 3, /* Case Latenty = 3 */
- 3, /* trp 20ns / 7.5 ns datain[27] */
- 3, /* trcd 20ns /7.5 ns (datain[29]) */
- 6, /* tras 44ns /7.5 ns (datain[30]) */
- 4, /* tcpt 44 - 20ns = 24ns */
- 3, /* Address Mode = 3 */
- 5, /* size value */
- 1}, /* ECC enabled */
- { 0x1f, /* Rev B, 128MByte -3 Board */
- 3, /* Case Latenty = 3 */
- 3, /* trp 20ns / 7.5 ns datain[27] */
- 3, /* trcd 20ns /7.5 ns (datain[29]) */
- 6, /* tras 44ns /7.5 ns (datain[30]) */
- 4, /* tcpt 44 - 20ns = 24ns */
- 3, /* Address Mode = 3 */
- 5, /* size value */
- 1}, /* ECC enabled */
- { 0x2f, /* Rev C, 128MByte -3 Board */
- 3, /* Case Latenty = 3 */
- 3, /* trp 20ns / 7.5 ns datain[27] */
- 3, /* trcd 20ns /7.5 ns (datain[29]) */
- 6, /* tras 44ns /7.5 ns (datain[30]) */
- 4, /* tcpt 44 - 20ns = 24ns */
- 3, /* Address Mode = 3 */
- 5, /* size value */
- 1}, /* ECC enabled */
- { 0xff, /* terminator */
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff,
- 0xff }
-};
-#endif /*CONFIG_TARGET_MIP405T */
-void SDRAM_err (const char *s)
-{
-#ifndef SDRAM_DEBUG
- (void) get_clocks ();
- gd->baudrate = 9600;
- serial_init ();
-#endif
- serial_puts ("\n");
- serial_puts (s);
- serial_puts ("\n enable SDRAM_DEBUG for more info\n");
- for (;;);
-}
-
-
-unsigned char get_board_revcfg (void)
-{
- out8 (PER_BOARD_ADDR, 0);
- return (in8 (PER_BOARD_ADDR));
-}
-
-
-#ifdef SDRAM_DEBUG
-
-void write_hex (unsigned char i)
-{
- char cc;
-
- cc = i >> 4;
- cc &= 0xf;
- if (cc > 9)
- serial_putc (cc + 55);
- else
- serial_putc (cc + 48);
- cc = i & 0xf;
- if (cc > 9)
- serial_putc (cc + 55);
- else
- serial_putc (cc + 48);
-}
-
-void write_4hex (unsigned long val)
-{
- write_hex ((unsigned char) (val >> 24));
- write_hex ((unsigned char) (val >> 16));
- write_hex ((unsigned char) (val >> 8));
- write_hex ((unsigned char) val);
-}
-
-#endif
-
-
-int init_sdram (void)
-{
- unsigned long tmp, baseaddr;
- unsigned short i;
- unsigned char trp_clocks,
- trcd_clocks,
- tras_clocks,
- trc_clocks;
- unsigned char cal_val;
- unsigned char bc;
- unsigned long sdram_tim, sdram_bank;
-
- /*i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);*/
- (void) get_clocks ();
- gd->baudrate = 9600;
- serial_init ();
- /* set up the pld */
- mtdcr (EBC0_CFGADDR, PB7AP);
- mtdcr (EBC0_CFGDATA, PLD_AP);
- mtdcr (EBC0_CFGADDR, PB7CR);
- mtdcr (EBC0_CFGDATA, PLD_CR);
- /* THIS IS OBSOLETE */
- /* set up the board rev reg*/
- mtdcr (EBC0_CFGADDR, PB5AP);
- mtdcr (EBC0_CFGDATA, BOARD_AP);
- mtdcr (EBC0_CFGADDR, PB5CR);
- mtdcr (EBC0_CFGDATA, BOARD_CR);
-#ifdef SDRAM_DEBUG
- /* get all informations from PLD */
- serial_puts ("\nPLD Part 0x");
- bc = in8 (PLD_PART_REG);
- write_hex (bc);
- serial_puts ("\nPLD Vers 0x");
- bc = in8 (PLD_VERS_REG);
- write_hex (bc);
- serial_puts ("\nBoard Rev 0x");
- bc = in8 (PLD_BOARD_CFG_REG);
- write_hex (bc);
- serial_puts ("\n");
-#endif
- /* check board */
- bc = in8 (PLD_PART_REG);
-#if defined(CONFIG_TARGET_MIP405T)
- if((bc & 0x80)==0)
- SDRAM_err ("U-Boot configured for a MIP405T not for a MIP405!!!\n");
-#else
- if((bc & 0x80)==0x80)
- SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n");
-#endif
- /* set-up the chipselect machine */
- mtdcr (EBC0_CFGADDR, PB0CR); /* get cs0 config reg */
- tmp = mfdcr (EBC0_CFGDATA);
- if ((tmp & 0x00002000) == 0) {
- /* MPS Boot, set up the flash */
- mtdcr (EBC0_CFGADDR, PB1AP);
- mtdcr (EBC0_CFGDATA, FLASH_AP);
- mtdcr (EBC0_CFGADDR, PB1CR);
- mtdcr (EBC0_CFGDATA, FLASH_CR);
- } else {
- /* Flash boot, set up the MPS */
- mtdcr (EBC0_CFGADDR, PB1AP);
- mtdcr (EBC0_CFGDATA, MPS_AP);
- mtdcr (EBC0_CFGADDR, PB1CR);
- mtdcr (EBC0_CFGDATA, MPS_CR);
- }
- /* set up UART0 (CS2) and UART1 (CS3) */
- mtdcr (EBC0_CFGADDR, PB2AP);
- mtdcr (EBC0_CFGDATA, UART0_AP);
- mtdcr (EBC0_CFGADDR, PB2CR);
- mtdcr (EBC0_CFGDATA, UART0_CR);
- mtdcr (EBC0_CFGADDR, PB3AP);
- mtdcr (EBC0_CFGDATA, UART1_AP);
- mtdcr (EBC0_CFGADDR, PB3CR);
- mtdcr (EBC0_CFGDATA, UART1_CR);
- bc = in8 (PLD_BOARD_CFG_REG);
-#ifdef SDRAM_DEBUG
- serial_puts ("\nstart SDRAM Setup\n");
- serial_puts ("\nBoard Rev: ");
- write_hex (bc);
- serial_puts ("\n");
-#endif
- i = 0;
- baseaddr = CONFIG_SYS_SDRAM_BASE;
- while (sdram_table[i].sz != 0xff) {
- if (sdram_table[i].boardtype == bc)
- break;
- i++;
- }
- if (sdram_table[i].boardtype != bc)
- SDRAM_err ("No SDRAM table found for this board!!!\n");
-#ifdef SDRAM_DEBUG
- serial_puts (" found table ");
- write_hex (i);
- serial_puts (" \n");
-#endif
- /* since the ECC initialisation needs some time,
- * we show that we're alive
- */
- if (sdram_table[i].ecc)
- serial_puts ("\nInitializing SDRAM, Please stand by");
- cal_val = sdram_table[i].cal - 1; /* Cas Latency */
- trp_clocks = sdram_table[i].trp; /* 20ns / 7.5 ns datain[27] */
- trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */
- tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */
- /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
- /* trc_clocks is sum of trp_clocks + tras_clocks */
- trc_clocks = trp_clocks + tras_clocks;
- /* get SDRAM timing register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
- sdram_tim = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
- /* insert CASL value */
- sdram_tim |= ((unsigned long) (cal_val)) << 23;
- /* insert PTA value */
- sdram_tim |= ((unsigned long) (trp_clocks - 1)) << 18;
- /* insert CTP value */
- sdram_tim |=
- ((unsigned long) (trc_clocks - trp_clocks -
- trcd_clocks)) << 16;
- /* insert LDF (always 01) */
- sdram_tim |= ((unsigned long) 0x01) << 14;
- /* insert RFTA value */
- sdram_tim |= ((unsigned long) (trc_clocks - 4)) << 2;
- /* insert RCD value */
- sdram_tim |= ((unsigned long) (trcd_clocks - 1)) << 0;
-
- tmp = ((unsigned long) (sdram_table[i].am - 1) << 13); /* AM = 3 */
- /* insert SZ value; */
- tmp |= ((unsigned long) sdram_table[i].sz << 17);
- /* get SDRAM bank 0 register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
- sdram_bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
- sdram_bank |= (baseaddr | tmp | 0x01);
-
-#ifdef SDRAM_DEBUG
- serial_puts ("sdtr: ");
- write_4hex (sdram_tim);
- serial_puts ("\n");
-#endif
-
- /* write SDRAM timing register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
- mtdcr (SDRAM0_CFGDATA, sdram_tim);
-
-#ifdef SDRAM_DEBUG
- serial_puts ("mb0cf: ");
- write_4hex (sdram_bank);
- serial_puts ("\n");
-#endif
-
- /* write SDRAM bank 0 register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
- mtdcr (SDRAM0_CFGDATA, sdram_bank);
-
- if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */
- /* get SDRAM refresh interval register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
- tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
- tmp |= 0x07F00000;
- } else {
- /* get SDRAM refresh interval register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
- tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
- tmp |= 0x05F00000;
- }
- /* write SDRAM refresh interval register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
- mtdcr (SDRAM0_CFGDATA, tmp);
- /* enable ECC if used */
-#if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI)
- if (sdram_table[i].ecc) {
- /* disable checking for all banks */
- unsigned long *p;
-#ifdef SDRAM_DEBUG
- serial_puts ("disable ECC.. ");
-#endif
- mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
- tmp = mfdcr (SDRAM0_CFGDATA);
- tmp &= 0xff0fffff; /* disable all banks */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
- /* set up SDRAM Controller with ECC enabled */
-#ifdef SDRAM_DEBUG
- serial_puts ("setup SDRAM Controller.. ");
-#endif
- mtdcr (SDRAM0_CFGDATA, tmp);
- mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
- tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000;
- mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
- mtdcr (SDRAM0_CFGDATA, tmp);
- udelay (600);
-#ifdef SDRAM_DEBUG
- serial_puts ("fill the memory..\n");
-#endif
- serial_puts (".");
- /* now, fill all the memory */
- tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz);
- p = (unsigned long) 0;
- while ((unsigned long) p < tmp) {
- *p++ = 0L;
- if (!((unsigned long) p % 0x00800000)) /* every 8MByte */
- serial_puts (".");
- }
- /* enable bank 0 */
- serial_puts (".");
-#ifdef SDRAM_DEBUG
- serial_puts ("enable ECC\n");
-#endif
- udelay (400);
- mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
- tmp = mfdcr (SDRAM0_CFGDATA);
- tmp |= 0x00800000; /* enable bank 0 */
- mtdcr (SDRAM0_CFGDATA, tmp);
- udelay (400);
- } else
-#endif
- {
- /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
- tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80C00000;
- mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
- mtdcr (SDRAM0_CFGDATA, tmp);
- udelay (400);
- }
- serial_puts ("\n");
- return (0);
-}
-
-int board_early_init_f (void)
-{
- init_sdram ();
-
- /*-------------------------------------------------------------------------+
- | Interrupt controller setup for the PIP405 board.
- | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
- | IRQ 16 405GP internally generated; active low; level sensitive
- | IRQ 17-24 RESERVED
- | IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive
- | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
- | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
- | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
- | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
- | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
- | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
- | Note for MIP405 board:
- | An interrupt taken for the SouthBridge (IRQ 25) indicates that
- | the Interrupt Controller in the South Bridge has caused the
- | interrupt. The IC must be read to determine which device
- | caused the interrupt.
- |
- +-------------------------------------------------------------------------*/
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr (UIC0ER, 0x00000000); /* disable all ints */
- mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */
- mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
- mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
- return 0;
-}
-
-int board_early_init_r(void)
-{
- int mode;
-
- /*
- * since we are relocated, we can finally enable i-cache
- * and set up the flash CS correctly
- */
- icache_enable();
- setup_cs_reloc();
- /* get and display boot mode */
- mode = get_boot_mode();
- if (mode & BOOT_PCI)
- printf("PCI Boot %s Map\n", (mode & BOOT_MPS) ?
- "MPS" : "Flash");
- else
- printf("%s Boot\n", (mode & BOOT_MPS) ?
- "MPS" : "Flash");
-
- return 0;
-}
-
-/*
- * Get some PLD Registers
- */
-
-unsigned short get_pld_parvers (void)
-{
- unsigned short result;
- unsigned char rc;
-
- rc = in8 (PLD_PART_REG);
- result = (unsigned short) rc << 8;
- rc = in8 (PLD_VERS_REG);
- result |= rc;
- return result;
-}
-
-
-void user_led0 (unsigned char on)
-{
- if (on)
- out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4));
- else
- out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb));
-}
-
-
-void ide_set_reset (int idereset)
-{
- /* if reset = 1 IDE reset will be asserted */
- if (idereset)
- out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1));
- else {
- udelay (10000);
- out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe));
- }
-}
-
-
-/* ------------------------------------------------------------------------- */
-
-void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var)
-{
-#if !defined(CONFIG_TARGET_MIP405T)
- unsigned char bc,rc,tmp;
- int i;
-
- bc = in8 (PLD_BOARD_CFG_REG);
- tmp = ~bc;
- tmp &= 0xf;
- rc = 0;
- for (i = 0; i < 4; i++) {
- rc <<= 1;
- rc += (tmp & 0x1);
- tmp >>= 1;
- }
- rc++;
- if(( (((bc>>4) & 0xf)==0x2) /* Rev C PCB or */
- || (((bc>>4) & 0xf)==0x1)) /* Rev B PCB with */
- && (rc==0x1)) /* Population Option 1 is a -3 */
- rc=3;
- *pcbrev=(bc >> 4) & 0xf;
- *var=rc;
-#else
- unsigned char bc;
- bc = in8 (PLD_BOARD_CFG_REG);
- *pcbrev=(bc >> 4) & 0xf;
- *var=16-(bc & 0xf);
-#endif
-}
-
-/*
- * Check Board Identity:
- */
-/* serial String: "MIP405_1000" OR "MIP405T_1000" */
-#if !defined(CONFIG_TARGET_MIP405T)
-#define BOARD_NAME "MIP405"
-#else
-#define BOARD_NAME "MIP405T"
-#endif
-
-int checkboard (void)
-{
- char s[50];
- unsigned char bc, var;
- int i;
- backup_t *b = (backup_t *) s;
-
- puts ("Board: ");
- get_pcbrev_var(&bc,&var);
- i = getenv_f("serial#", (char *)s, 32);
- if ((i == 0) || strncmp ((char *)s, BOARD_NAME,sizeof(BOARD_NAME))) {
- get_backup_values (b);
- if (strncmp (b->signature, "MPL\0", 4) != 0) {
- puts ("### No HW ID - assuming " BOARD_NAME);
- printf ("-%d Rev %c", var, 'A' + bc);
- } else {
- b->serial_name[sizeof(BOARD_NAME)-1] = 0;
- printf ("%s-%d Rev %c SN: %s", b->serial_name, var,
- 'A' + bc, &b->serial_name[sizeof(BOARD_NAME)]);
- }
- } else {
- s[sizeof(BOARD_NAME)-1] = 0;
- printf ("%s-%d Rev %c SN: %s", s, var,'A' + bc,
- &s[sizeof(BOARD_NAME)]);
- }
- bc = in8 (PLD_EXT_CONF_REG);
- printf (" Boot Config: 0x%x\n", bc);
- return (0);
-}
-
-
-/* ------------------------------------------------------------------------- */
-/* ------------------------------------------------------------------------- */
-/*
- dram_init() reads EEPROM via I2c. EEPROM contains all of
- the necessary info for SDRAM controller configuration
-*/
-/* ------------------------------------------------------------------------- */
-/* ------------------------------------------------------------------------- */
-static int test_dram (unsigned long ramsize);
-
-int dram_init(void)
-{
-
- unsigned long bank_reg[4], tmp, bank_size;
- int i;
- unsigned long TotalSize;
-
- /* since the DRAM controller is allready set up, calculate the size with the
- bank registers */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
- bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
- bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
- bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
- bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
- TotalSize = 0;
- for (i = 0; i < 4; i++) {
- if ((bank_reg[i] & 0x1) == 0x1) {
- tmp = (bank_reg[i] >> 17) & 0x7;
- bank_size = 4 << tmp;
- TotalSize += bank_size;
- }
- }
- mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
- tmp = mfdcr (SDRAM0_CFGDATA);
-
- if (!tmp)
- printf ("No ");
- printf ("ECC ");
-
- test_dram (TotalSize * MEGA_BYTE);
- gd->ram_size = TotalSize * MEGA_BYTE;
-
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-
-static int test_dram (unsigned long ramsize)
-{
-#ifdef SDRAM_DEBUG
- mem_test (0L, ramsize, 1);
-#endif
- /* not yet implemented */
- return (1);
-}
-
-/* used to check if the time in RTC is valid */
-static unsigned long start;
-static struct rtc_time tm;
-
-int misc_init_r (void)
-{
- /* adjust flash start and size as well as the offset */
- gd->bd->bi_flashstart=0-flash_info[0].size;
- gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN;
- gd->bd->bi_flashoffset=0;
-
- /* check, if RTC is running */
- rtc_get (&tm);
- start=get_timer(0);
- /* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
- if (mfdcr(CPC0_PSR) & PSR_ROM_LOC)
- mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
-
- return (0);
-}
-
-
-void print_mip405_rev (void)
-{
- unsigned char part, vers, pcbrev, var;
-
- get_pcbrev_var(&pcbrev,&var);
- part = in8 (PLD_PART_REG);
- vers = in8 (PLD_VERS_REG);
- printf ("Rev: " BOARD_NAME "-%d Rev %c PLD %d Vers %d\n",
- var, pcbrev + 'A', part & 0x7F, vers);
-}
-
-
-extern int mk_date (char *, struct rtc_time *);
-
-int last_stage_init (void)
-{
- unsigned long stop;
- struct rtc_time newtm;
- char *s;
-
- /* write correct LED configuration */
- if (miiphy_write("ppc_4xx_eth0", 0x1, 0x14, 0x2402) != 0) {
- printf ("Error writing to the PHY\n");
- }
- /* since LED/CFG2 is not connected on the -2,
- * write to correct capability information */
- if (miiphy_write("ppc_4xx_eth0", 0x1, 0x4, 0x01E1) != 0) {
- printf ("Error writing to the PHY\n");
- }
- print_mip405_rev ();
- stdio_print_current_devices ();
- check_env ();
- /* check if RTC time is valid */
- stop=get_timer(start);
- while(stop<1200) { /* we wait 1.2 sec to check if the RTC is running */
- udelay(1000);
- stop=get_timer(start);
- }
- rtc_get (&newtm);
- if(tm.tm_sec==newtm.tm_sec) {
- s=getenv("defaultdate");
- if(!s)
- mk_date ("010112001970", &newtm);
- else
- if(mk_date (s, &newtm)!=0) {
- printf("RTC: Bad date format in defaultdate\n");
- return 0;
- }
- rtc_reset ();
- rtc_set(&newtm);
- }
- return 0;
-}
-
-/***************************************************************************
- * some helping routines
- */
-
-int overwrite_console (void)
-{
- /* return true if console should be overwritten */
- return ((in8(PLD_EXT_CONF_REG) & 0x1) == 0);
-}
-
-
-/************************************************************************
-* Print MIP405 Info
-************************************************************************/
-void print_mip405_info (void)
-{
- unsigned char part, vers, cfg, irq_reg, com_mode, ext;
-
- part = in8 (PLD_PART_REG);
- vers = in8 (PLD_VERS_REG);
- cfg = in8 (PLD_BOARD_CFG_REG);
- irq_reg = in8 (PLD_IRQ_REG);
- com_mode = in8 (PLD_COM_MODE_REG);
- ext = in8 (PLD_EXT_CONF_REG);
-
- printf ("PLD Part %d version %d\n", part & 0x7F, vers);
- printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A');
- printf ("Population Options %d %d %d %d\n", (cfg) & 0x1,
- (cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1);
- printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off");
- printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3);
-#if !defined(CONFIG_TARGET_MIP405T)
- printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
- (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
- (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
- (ext >> 6) & 0x1, (ext >> 7) & 0x1);
- printf ("SER1 uses handshakes %s\n",
- (ext & 0x80) ? "DTR/DSR" : "RTS/CTS");
-#else
- printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
- (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
- (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
- (ext >> 6) & 0x1,(ext >> 7) & 0x1);
-#endif
- printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted");
- printf ("IRQs:\n");
- printf (" PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active");
-#if !defined(CONFIG_TARGET_MIP405T)
- printf (" UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active");
- printf (" UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active");
-#endif
- printf (" PIIX SMI: %s\n", (irq_reg & 0x10) ? "inactive" : "active");
- printf (" PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active");
- printf (" PIIX NMI: %s\n", (irq_reg & 0x4) ? "inactive" : "active");
-}
diff --git a/board/mpl/mip405/mip405.h b/board/mpl/mip405/mip405.h
deleted file mode 100644
index b1f69aa..0000000
--- a/board/mpl/mip405/mip405.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
- /****************************************************************************
- * Global routines used for MIP405
- *****************************************************************************/
-#ifndef __ASSEMBLY__
-/*int switch_cs(unsigned char boot);*/
-
-extern int mem_test(unsigned long start, unsigned long ramsize,int mode);
-
-void user_led0(unsigned char on);
-
-
-#endif
-/* timings */
-/* PLD (CS7) */
-#define PLD_BME 0 /* Burst disable */
-#define PLD_TWE 5 /* 5 * 30ns 120ns Waitstates (access=TWT+1+TH) */
-#define PLD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define PLD_OEN 1 /* Cycles from CS low to OE low */
-#define PLD_WBN 1 /* Cycles from CS low to WE low */
-#define PLD_WBF 1 /* Cycles from WE high to CS high */
-#define PLD_TH 2 /* Number of hold cycles after transfer */
-#define PLD_RE 0 /* Ready disabled */
-#define PLD_SOR 1 /* Sample on Ready disabled */
-#define PLD_BEM 0 /* Byte Write only active on Write cycles */
-#define PLD_PEN 0 /* Parity disable */
-#define PLD_AP ((PLD_BME << 31) + (PLD_TWE << 23) + (PLD_CSN << 18) + (PLD_OEN << 16) + (PLD_WBN << 14) + \
- (PLD_WBF << 12) + (PLD_TH << 9) + (PLD_RE << 8) + (PLD_SOR << 7) + (PLD_BEM << 6) + (PLD_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define PLD_BS 0 /* 1 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define PLD_BU 3 /* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define PLD_BW 0 /* 16Bit */
-#define PLD_CR ((PER_PLD_ADDR & 0xfff00000) + (PLD_BS << 17) + (PLD_BU << 15) + (PLD_BW << 13))
-
-
-/* timings */
-
-#define PER_BOARD_ADDR (PER_UART1_ADDR+(1024*1024))
-/* Dummy CS to get the board revision */
-#define BOARD_BME 0 /* Burst disable */
-#define BOARD_TWE 255 /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
-#define BOARD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define BOARD_OEN 1 /* Cycles from CS low to OE low */
-#define BOARD_WBN 1 /* Cycles from CS low to WE low */
-#define BOARD_WBF 1 /* Cycles from WE high to CS high */
-#define BOARD_TH 2 /* Number of hold cycles after transfer */
-#define BOARD_RE 0 /* Ready disabled */
-#define BOARD_SOR 1 /* Sample on Ready disabled */
-#define BOARD_BEM 0 /* Byte Write only active on Write cycles */
-#define BOARD_PEN 0 /* Parity disable */
-#define BOARD_AP ((BOARD_BME << 31) + (BOARD_TWE << 23) + (BOARD_CSN << 18) + (BOARD_OEN << 16) + (BOARD_WBN << 14) + \
- (BOARD_WBF << 12) + (BOARD_TH << 9) + (BOARD_RE << 8) + (BOARD_SOR << 7) + (BOARD_BEM << 6) + (BOARD_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define BOARD_BS 0 /* 1 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define BOARD_BU 3 /* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define BOARD_BW 0 /* 16Bit */
-#define BOARD_CR ((PER_BOARD_ADDR & 0xfff00000) + (BOARD_BS << 17) + (BOARD_BU << 15) + (BOARD_BW << 13))
-
-
-/* UART0 CS2 */
-#define UART0_BME 0 /* Burst disable */
-#define UART0_TWE 7 /* 7 * 30ns 210ns Waitstates (access=TWT+1+TH) */
-#define UART0_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define UART0_OEN 1 /* Cycles from CS low to OE low */
-#define UART0_WBN 1 /* Cycles from CS low to WE low */
-#define UART0_WBF 1 /* Cycles from WE high to CS high */
-#define UART0_TH 2 /* Number of hold cycles after transfer */
-#define UART0_RE 0 /* Ready disabled */
-#define UART0_SOR 1 /* Sample on Ready disabled */
-#define UART0_BEM 0 /* Byte Write only active on Write cycles */
-#define UART0_PEN 0 /* Parity disable */
-#define UART0_AP ((UART0_BME << 31) + (UART0_TWE << 23) + (UART0_CSN << 18) + (UART0_OEN << 16) + (UART0_WBN << 14) + \
- (UART0_WBF << 12) + (UART0_TH << 9) + (UART0_RE << 8) + (UART0_SOR << 7) + (UART0_BEM << 6) + (UART0_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define UART0_BS 0 /* 1 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define UART0_BU 3 /* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define UART0_BW 0 /* 8Bit */
-#define UART0_CR ((PER_UART0_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13))
-
-/* UART1 CS3 */
-#define UART1_AP UART0_AP /* same timing as UART0 */
-#define UART1_CR ((PER_UART1_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13))
-
-
-/* Flash CS0 or CS 1 */
-/* 0x7F8FFE80 slowest timing at all... */
-#define FLASH_BME_B 1 /* Burst enable */
-#define FLASH_FWT_B 0x6 /* 6 * 30ns 210ns First Wait Access */
-#define FLASH_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */
-#define FLASH_BME 0 /* Burst disable */
-#define FLASH_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
-#define FLASH_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define FLASH_OEN 1 /* Cycles from CS low to OE low */
-#define FLASH_WBN 1 /* Cycles from CS low to WE low */
-#define FLASH_WBF 1 /* Cycles from WE high to CS high */
-#define FLASH_TH 2 /* Number of hold cycles after transfer */
-#define FLASH_RE 0 /* Ready disabled */
-#define FLASH_SOR 1 /* Sample on Ready disabled */
-#define FLASH_BEM 0 /* Byte Write only active on Write cycles */
-#define FLASH_PEN 0 /* Parity disable */
-/* Access Parameter Register for non Boot */
-#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
- (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
-/* Access Parameter Register for Boot */
-#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
- (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define FLASH_BS FLASH_SIZE_PRELIM /* 4 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define FLASH_BU 3 /* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define FLASH_BW 1 /* 16Bit */
-/* CR register for Boot */
-#define FLASH_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
-/* CR register for non Boot */
-#define FLASH_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
-
-/* MPS CS1 or CS0 */
-/* Boot CS: */
-#define MPS_BME_B 1 /* Burst enable */
-#define MPS_FWT_B 0x6/* 6 * 30ns 210ns First Wait Access */
-#define MPS_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */
-#define MPS_BME 0 /* Burst disable */
-#define MPS_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
-#define MPS_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define MPS_OEN 1 /* Cycles from CS low to OE low */
-#define MPS_WBN 1 /* Cycles from CS low to WE low */
-#define MPS_WBF 1 /* Cycles from WE high to CS high */
-#define MPS_TH 2 /* Number of hold cycles after transfer */
-#define MPS_RE 0 /* Ready disabled */
-#define MPS_SOR 1 /* Sample on Ready disabled */
-#define MPS_BEM 0 /* Byte Write only active on Write cycles */
-#define MPS_PEN 0 /* Parity disable */
-/* Access Parameter Register for non Boot */
-#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
- (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
-/* Access Parameter Register for Boot */
-#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
- (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define MPS_BS 2 /* 4 MByte */
-#define MPS_BS_B FLASH_SIZE_PRELIM /* 1 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define MPS_BU 3 /* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define MPS_BW 0 /* 8Bit */
-/* CR register for Boot */
-#define MPS_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS_B << 17) + (MPS_BU << 15) + (MPS_BW << 13))
-/* CR register for non Boot */
-#define MPS_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
diff --git a/board/mpl/pip405/Kconfig b/board/mpl/pip405/Kconfig
deleted file mode 100644
index e7ae6af..0000000
--- a/board/mpl/pip405/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_PIP405
-
-config SYS_BOARD
- default "pip405"
-
-config SYS_VENDOR
- default "mpl"
-
-config SYS_CONFIG_NAME
- default "PIP405"
-
-config ISO_STRING
- string
- default "MEV-10066-001"
-endif
diff --git a/board/mpl/pip405/MAINTAINERS b/board/mpl/pip405/MAINTAINERS
deleted file mode 100644
index 9b3b974..0000000
--- a/board/mpl/pip405/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PIP405 BOARD
-M: Denis Peter <d.peter@mpl.ch>
-S: Maintained
-F: board/mpl/pip405/
-F: include/configs/PIP405.h
-F: configs/PIP405_defconfig
diff --git a/board/mpl/pip405/Makefile b/board/mpl/pip405/Makefile
deleted file mode 100644
index 0a3d059..0000000
--- a/board/mpl/pip405/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = pip405.o cmd_pip405.o \
- ../common/pci.o \
- ../common/isa.o \
- ../common/kbd.o \
- ../common/usb_uhci.o \
- ../common/common_util.o
-obj-y += init.o
diff --git a/board/mpl/pip405/README b/board/mpl/pip405/README
deleted file mode 100644
index f039817..0000000
--- a/board/mpl/pip405/README
+++ /dev/null
@@ -1,371 +0,0 @@
-U-Boot Changes due to PIP405 Port:
-===================================
-
-Changed files:
-==============
-- MAKEALL added PIP405
-- makefile added PIP405
-- common/Makefile added Floppy disk and SCSI support
-- common/board.c added PIP405, SCSI support, get_PCI_freq()
-- common/bootm.c added IH_OS_U_BOOT, IH_TYPE_FIRMWARE
-- common/cmd_i2c.c added "defined(CONFIG_PIP405)"
-- common/cmd_ide.c changed div. functions to work with block device
- description
- added ATAPI support
-- common/command.c added SCSI and Floppy support
-- common/console.c replaced // with /* comments
- added console settings from environment
-- common/devices.c added ISA keyboard init
-- common/main.c corrected the read of bootdelay
-- arch/powerpc/cpu/ppc4xx/405gp_pci.c excluded file from PIP405
-- arch/powerpc/cpu/ppc4xx/i2c.c added 16bit read write I2C support
- added page write
-- arch/powerpc/cpu/ppc4xx/speed.c added get_PCI_freq
-- arch/powerpc/cpu/ppc4xx/start.S added CONFIG_IDENT_STRING
-- disk/Makefile added part_iso for CD support
-- disk/part.c changed to work with block device description
- added ISO CD support
- added dev_print (was ide_print in cmd_ide.c)
-- disk/part_dos.c changed to work with block device description
-- disk/part_mac.c changed to work with block device description
-- include/ata.h added ATAPI commands
-- include/cmd_bsp.h added PIP405 commands definitions
-- include/cmd_condefs.h added Floppy and SCSI support
-- include/cmd_disk.h changed to work with block device description
-- include/config_LANTEC.h excluded CONFIG_CMD_FDC and CONFIG_SCSI
-- include/config_hymod.h excluded CONFIG_CMD_FDC and CONFIG_SCSI
-- include/flash.h added INTEL_ID_28F320C3T 0x88C488C4
-- include/i2c.h added "defined(CONFIG_PIP405)"
-- include/image.h added IH_OS_U_BOOT, IH_TYPE_FIRMWARE
-- include/u-boot.h moved partitions functions definitions to part.h
- added "defined(CONFIG_PIP405)"
- added get_PCI_freq() definition
-- rtc/Makefile added MC146818 RTC support
-- tools/mkimage.c added IH_OS_U_BOOT, IH_TYPE_FIRMWARE
-
-Added files:
-============
-- board/pip405 directory for PIP405
-- board/pip405/cmd_pip405.c board specific commands
-- board/pip405/config.mk config make
-- board/pip405/flash.c flash support
-- board/pip405/init.s start-up
-- board/pip405/kbd.c keyboard support
-- board/pip405/kbd.h keyboard support
-- board/pip405/Makefile Makefile
-- board/pip405/pci_piix4.h southbridge definitions
-- board/pip405/pci_pip405.c PCI support for PIP405
-- board/pip405/pci_pip405.h PCI support for PIP405
-- board/pip405/pip405.c PIP405 board init
-- board/pip405/pip405.h PIP405 board init
-- board/pip405/pip405_isa.c ISA support
-- board/pip405/pip405_isa.h ISA support
-- board/pip405/u-boot.lds Linker description
-- board/pip405/u-boot.lds.debugLinker description debug
-- board/pip405/sym53c8xx.c SYM53C810A support
-- board/pip405/sym53c8xx_defs.h SYM53C810A definitions
-- board/pip405/vga_table.h definitions of tables for VGA
-- board/pip405/video.c CT69000 support
-- board/pip405/video.h CT69000 support
-- common/cmd_fdc.c Floppy disk support
-- common/cmd_scsi.c SCSI support
-- disk/part_iso.c ISO CD ROM support
-- disk/part_iso.h ISO CD ROM support
-- include/cmd_fdc.h command forFloppy disk support
-- include/cmd_scsi.h command for SCSI support
-- include/part.h partitions functions definitions
- (was part of u-boot.h)
-- include/scsi.h SCSI support
-- rtc/mc146818.c MC146818 RTC support
-
-
-New Config Switches:
-====================
-For detailed description, refer to the corresponding paragraph in the
-section "Changes".
-
-New Commands:
--------------
-CONFIG_SCSI SCSI Support
-CONFIG_CMF_FDC Floppy disk support
-
-IDE additions:
---------------
-CONFIG_IDE_RESET_ROUTINE defines that instead of a reset Pin,
- the routine ide_set_reset(int idereset) is used.
-ATAPI support (experimental)
-----------------------------
-CONFIG_ATAPI enables ATAPI Support
-
-SCSI support (experimental) only SYM53C8xx supported
-----------------------------------------------------
-CONFIG_SCSI_SYM53C8XX type of SCSI controller
-CONFIG_SYS_SCSI_MAX_LUN 8 number of supported LUNs
-CONFIG_SYS_SCSI_MAX_SCSI_ID 7 maximum SCSI ID (0..6)
-CONFIG_SYS_SCSI_MAX_DEVICE CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN
- maximum of Target devices (multiple LUN support
- for boot)
-
-ISO (CD-Boot) partition support (Experimental)
-----------------------------------------------
-CONFIG_ISO_PARTITION CD-boot support
-
-RTC
-----
-CONFIG_RTC_MC146818 MC146818 RTC support
-
-Video:
-------
-CONFIG_VIDEO_CT69000 Enable Chips & Technologies 69000 Video chip
- CONFIG_VIDEO must be defined also
-
-External peripheral base address:
----------------------------------
-CONFIG_SYS_ISA_IO_BASE_ADDRESS address of all ISA-bus related parts
- _must_ be defined for ISA-bus parts
-
-Identify:
----------
-CONFIG_IDENT_STRING added to the U_BOOT_VERSION String
-
-Environment / Console:
-----------------------
-
-CONFIG_SYS_CONSOLE_IS_IN_ENV if defined, stdin, stdout and stderr used from
- the values stored in the evironment.
-
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE if defined, console_overwrite() decides if the
- values stored in the environment or the standard
- serial in/out put should be assigned to the console.
-
-CONFIG_SYS_CONSOLE_ENV_OVERWRITE if defined, the start-up console switching
- are stored in the environment.
-
-PIP405 specific:
-----------------
-CONFIG_PORT_ADDR address used to read boot configuration
-MULTI_PURPOSE_SOCKET_ADDR address of the multi purpose socked
-SDRAM_EEPROM_WRITE_ADDRESS addresses of the serial presence detect
-SDRAM_EEPROM_READ_ADDRESS EEPROM on the SDRAM module.
-
-
-Changes:
-========
-
-Added Devices:
-==============
-
-Floppy support:
----------------
-Support of a standard floppy disk controller at address CONFIG_SYS_ISA_IO_BASE_ADDRESS
-+ 0x3F0. Enabled with define CONFIG_CMD_FDC. Reads a unformated floppy disk
-with a image header (see: mkimage). No interrupts and no DMA are used for this.
-Added files:
-- common/cmd_fdc.c
-- include/cmd_fdc.h
-
-SCSI support:
--------------
-Support for Symbios SYM53C810A chip. Implemented as follows:
-- without disconnect
-- only asynchrounous
-- multiple LUN support (caution, needs a lot of RAM. define CONFIG_SYS_SCSI_MAX_LUN 1 to
- save RAM)
-- multiple SCSI ID support
-- no write support
-- analyses the MAC, DOS and ISO pratition similar to the IDE support
-- allows booting from SCSI devices similar to the IDE support.
-The device numbers are not assigned like they are within the IDE support. The first
-device found will get the number 0, the next 1 etc. If all SCSI IDs (0..6) and all
-LUNs (8) are enabled, 56 boot devices are possible. This uses a lot of RAM since the
-device descriptors are not yet dynamically allocated. 56 boot devices are overkill
-anyway. Please refer to the section "Todo" chapter "block device support enhancement".
-The SYM53C810A uses 1 Interrupt and must be able of mastering the PCI bus.
-Added files:
-- common/cmd_scsi.c
-- common/board.c
-- include/cmd_scsi.h
-- include/scsi.h
-- board/pip405/sym53c8xx.c
-- board/pip405/sym53c8xx_defs.h
-
-ATAPI support (IDE changes):
-----------------------------
-Added ATAPI support (with CONFIG_ATAPI) in the file cmd_ide.c.
-To support a hardreset, when the IDE reset pin is not connected to the
-CONFIG_SYS_PC_IDE_RESET pin, the switch CONFIG_IDE_RESET_ROUTINE has been added. When
-this switch is enabled the routine void ide_set_reset(int idereset) must be
-within the board specific files.
-Only read from ATAPI devices are supported.
-Found out that the function trim_trail cuts off the last character if the whole
-string is filled. Added function cpy_ident instead, which trims also leading
-spaces and copies the string in the buffer.
-Changed files:
-- common/cmd_ide.c
-- include/ata.h
-
-ISO partition support:
-----------------------
-Added CD boot support for El-Torito bootable ISO CDs. The bootfile image must contain
-the U-Boot image header. Since CDs do not have "partitions", the boot partition is 0.
-The bootcatalog feature has not been tested so far. CD Boot is supported for ATAPI
-("diskboot") and SCSI ("scsiboot") devices.
-Added files:
-- disk/iso_part.c
-- disk/iso_part.h
-
-Block device changes:
----------------------
-To allow the use of dos_part.c, mac_part.c and iso_part.c, the parameter
-blk_desc will be used when accessing the functions in these files. The block
-device descriptor (blk_desc) contains a pointer to the read routine of the
-device, which will be used to read blocks from the device.
-Renamed function ide_print to dev_print and moved it to the file disk/part.c to use
-it for IDE ATAPI and SCSI devices.
-Please refer to the section "Todo" chapter "block device support enhancement".
-Added files:
-- include/part.h
-changed files:
-- disk/dos_part.c
-- disk/dos_part.h
-- disk/mac_part.c
-- disk/mac_part.h
-- disk/part.c
-- common/cmd_ide.c
-- include/u-boot.h
-
-
-MC146818 RTC support:
----------------------
-Added support for MC146818 RTC with defining CONFIG_RTC_MC146818. The ISA bus IO
-base address must be defined with CONFIG_SYS_ISA_IO_BASE_ADDRESS.
-Added files:
-- rtc/mc146818.c
-
-Standard ISA bus Keyboard support:
-----------------------------------
-Added support for the standard PC kyeboard controller. For the PIP405 the superIO
-controller must be set up previously. The keyboard uses the standard ISA IRQ, so
-the ISA PIC must also be set up.
-Added files:
-- board/pip405/kbd.c
-- board/pip405/kbd.h
-- board/pip405/pip405_isa.c
-- board/pip405/pip405_isa.h
-
-Chips and Technologie 69000 VGA controller support:
----------------------------------------------------
-Added support for the CT69000 VGA controller.
-Added files:
-- board/pip405/video.c
-- board/pip405/video.h
-- board/pip405/vga_table.h
-
-
-Changed Items:
-==============
-
-Identify:
----------
-Added the config variable CONFIG_IDENT_STRING which will be added to the
-"U_BOOT_VERSION __TIME__ DATE___ " String, to allows to identify intermidiate
-and custom versions.
-Changed files:
-- arch/powerpc/cpu/ppc4xx/start.s
-
-Firmware Image:
----------------
-Added IH_OS_U_BOOT and IH_TYPE_FIRMWARE to the image definitions to allows the
-U-Boot update with prior CRC check.
-Changed files:
-- include/image.h
-- tools/mkimage.c
-- common/cmd_bootm.c
-
-Correct PCI Frequency for PPC405:
----------------------------------
-Added function (in arch/powerpc/cpu/ppc4xx/speed.c) to get the PCI frequency for PPC405 CPU.
-The PCI Frequency will now be set correct in the board description in common/board.c.
-(was set to the busfreq before).
-Changed files:
-- arch/powerpc/cpu/ppc4xx/speed.c
-- common/board.c
-
-I2C Stuff:
-----------
-Added defined(CONFIG_PIP405) at several points in common/cmd_i2c.c.
-Added 16bit read/write support for I2C (PPC405), and page write to
-I2C EEPROM if defined CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE.
-Changed files:
-- arch/powerpc/cpu/ppc4xx/i2c.c
-- common/cmd_i2c.c
-
-Environment / Console:
-----------------------
-Although in README.console described, the U-Boot has not assinged the values
-found in the environment to the console. Corrected this behavior, but only if
-CONFIG_SYS_CONSOLE_IS_IN_ENV is defined.
-If CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE is defined, console_overwrite() decides if the
-values stored in the environment or the standard serial in/output should be
-assigned to the console. This is useful if the environment values are not correct.
-If CONFIG_SYS_CONSOLE_ENV_OVERWRITE is defined the devices assigned to the console at
-start-up time will be written to the environment. This means that if the
-environment values are overwritten by the overwrite_console() routine, they will be
-stored in the environment.
-Changed files:
-- common/console.c
-
-Correct bootdelay intepretation:
---------------------------------
-Changed bootdelay read from the environment from simple_strtoul (unsigned) to
-simple_strtol (signed), to be able to get a bootdelay of -1.
-Changed files:
-- common/main.c
-
-Todo:
-=====
-
-Block device support enhancement:
----------------------------------
-Consider to unify the block device handling. Instead of using diskboot for IDE,
-scsiboot for SCSI and fdcboot for floppy disks, it would make sense to use only
-one command ("devboot" ???) with a parameter of the desired device ("hda1", "sda1",
-"fd0" ???) to boot from. The other ide commands can be handled in the same way
-("dev hda read.." instead of "ide read.." or "dev sda read.." instead of
-"scsi read..."). Todo this, a common way of assign a block device to its name
-(first found ide device = hda, second found hdb etc., or hda is device 0 on bus 0,
-hdb is device 1 on bus 0 etc.) as well as the names (hdx for ide, sdx for scsi, fx for
-floppy ???) must be defined.
-Maybe there are better ideas to do this.
-
-Console assingment:
--------------------
-Consider to initialize and assign the console stdin, stdout and stderr as soon as
-possible to see the boot messages also on an other console than serial.
-
-
-Todo for PIP405:
-================
-
-LCD support for VGA:
---------------------
-Add LCD support for the CT69000
-
-Default environment:
---------------------
-Consider to write a default environment to the OTP part of the EEPROM and use it
-if the normal environment is not valid. Useful for serial# and ethaddr values.
-
-Watchdog:
----------
-Implement Watchdog.
-
-Files clean-up:
----------------
-Following files needs to be cleaned up:
-- cmd_pip405.c
-- flash.c
-- pci_pip405.c
-- pip405.c
-- pip405_isa.c
-Consider to split up the files in their functions.
diff --git a/board/mpl/pip405/cmd_pip405.c b/board/mpl/pip405/cmd_pip405.c
deleted file mode 100644
index 43b182e..0000000
--- a/board/mpl/pip405/cmd_pip405.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * hacked for PIP405
- */
-
-#include <common.h>
-#include <command.h>
-#include "pip405.h"
-#include "../common/common_util.h"
-
-
-extern void print_pip405_info(void);
-extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
-
-/* ------------------------------------------------------------------------- */
-
-int do_pip405(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-
- ulong led_on,led_nr;
-
- if (strcmp(argv[1], "info") == 0)
- {
- print_pip405_info();
- return 0;
- }
- if (strcmp(argv[1], "led") == 0)
- {
- led_nr = (ulong)simple_strtoul(argv[2], NULL, 10);
- led_on = (ulong)simple_strtoul(argv[3], NULL, 10);
- if(!led_nr)
- user_led0(led_on);
- else
- user_led1(led_on);
- return 0;
- }
-
- return (do_mplcommon(cmdtp, flag, argc, argv));
-}
-U_BOOT_CMD(
- pip405, 6, 1, do_pip405,
- "PIP405 specific Cmds",
- "flash mem [SrcAddr] - updates U-Boot with image in memory\n"
- "pip405 flash floppy [SrcAddr] - updates U-Boot with image from floppy\n"
- "pip405 flash mps - updates U-Boot with image from MPS"
-);
-
-/* ------------------------------------------------------------------------- */
diff --git a/board/mpl/pip405/init.S b/board/mpl/pip405/init.S
deleted file mode 100644
index 292393e..0000000
--- a/board/mpl/pip405/init.S
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * SPDX-License-Identifier: GPL-2.0 IBM-pibs
- */
-/*-----------------------------------------------------------------------------
- * Function: ext_bus_cntlr_init
- * Description: Initializes the External Bus Controller for the external
- * peripherals. IMPORTANT: For pass1 this code must run from
- * cache since you can not reliably change a peripheral banks
- * timing register (pbxap) while running code from that bank.
- * For ex., since we are running from ROM on bank 0, we can NOT
- * execute the code that modifies bank 0 timings from ROM, so
- * we run it from cache.
- * Bank 0 - Flash or Multi Purpose Socket
- * Bank 1 - Multi Purpose Socket or Flash
- * Bank 2 - not used
- * Bank 3 - not used
- * Bank 4 - not used
- * Bank 5 - not used
- * Bank 6 - used to switch on the 12V for the Multipurpose socket
- * Bank 7 - Config Register
- *-----------------------------------------------------------------------------*/
-
-#include <configs/PIP405.h>
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <asm/ppc4xx.h>
-#include "pip405.h"
-
- .globl ext_bus_cntlr_init
- ext_bus_cntlr_init:
- mflr r4 /* save link register */
- mfdcr r3,CPC0_PSR /* get strapping reg */
- andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */
- bnelr /* jump back if PCI boot */
-
- bl ..getAddr
-..getAddr:
- mflr r3 /* get address of ..getAddr */
- mtlr r4 /* restore link register */
- addi r4,0,14 /* set ctr to 14; used to prefetch */
- mtctr r4 /* 14 cache lines to fit this function */
- /* in cache (gives us 8x14=112 instrctns) */
-..ebcloop:
- icbt r0,r3 /* prefetch cache line for addr in r3 */
- addi r3,r3,32 /* move to next cache line */
- bdnz ..ebcloop /* continue for 14 cache lines */
-
- /*-------------------------------------------------------------------
- * Delay to ensure all accesses to ROM are complete before changing
- * bank 0 timings.
- *------------------------------------------------------------------- */
- addis r3,0,0x0
- ori r3,r3,0xA000
- mtctr r3
-..spinlp:
- bdnz ..spinlp /* spin loop */
-
- /*-----------------------------------------------------------------------
- * decide boot up mode
- *----------------------------------------------------------------------- */
- addi r4,0,PB0CR
- mtdcr EBC0_CFGADDR,r4
- mfdcr r4,EBC0_CFGDATA
-
- andi. r0, r4, 0x2000 /* mask out irrelevant bits */
- beq 0f /* jump if 8 bit bus width */
-
- /* setup 16 bit things
- *-----------------------------------------------------------------------
- * Memory Bank 0 (16 Bit Flash) initialization
- *---------------------------------------------------------------------- */
-
- addi r4,0,PB1AP
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,(FLASH_AP_B)@h
- ori r4,r4,(FLASH_AP_B)@l
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB0CR
- mtdcr EBC0_CFGADDR,r4
- /* BS=0x010(4MB),BU=0x3(R/W), */
- addis r4,0,(FLASH_CR_B)@h
- ori r4,r4,(FLASH_CR_B)@l
- mtdcr EBC0_CFGDATA,r4
- b 1f
-
-0:
- /* 8Bit boot mode: */
- /*-----------------------------------------------------------------------
- * Memory Bank 0 Multi Purpose Socket initialization
- *----------------------------------------------------------------------- */
- /* 0x7F8FFE80 slowest boot */
- addi r4,0,PB1AP
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,(MPS_AP_B)@h
- ori r4,r4,(MPS_AP_B)@l
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB0CR
- mtdcr EBC0_CFGADDR,r4
- /* BS=0x010(4MB),BU=0x3(R/W), */
- addis r4,0,(MPS_CR_B)@h
- ori r4,r4,(MPS_CR_B)@l
- mtdcr EBC0_CFGDATA,r4
-
-
-1:
- /*-----------------------------------------------------------------------
- * Memory Bank 2-3-4-5-6 (not used) initialization
- *-----------------------------------------------------------------------*/
- addi r4,0,PB1CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB2CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB3CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB4CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB5CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB6CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
-
- addi r4,0,PB7CR
- mtdcr EBC0_CFGADDR,r4
- addis r4,0,0x0000
- ori r4,r4,0x0000
- mtdcr EBC0_CFGDATA,r4
- nop /* pass2 DCR errata #8 */
- blr
-
-#if defined(CONFIG_BOOT_PCI)
- .section .bootpg,"ax"
- .globl _start_pci
-/*******************************************
- */
-
-_start_pci:
- /* first handle errata #68 / PCI_18 */
- iccci r0, r0 /* invalidate I-cache */
- lis r31, 0
- mticcr r31 /* ICCR = 0 (all uncachable) */
- isync
-
- mfccr0 r28 /* set CCR0[24] = 1 */
- ori r28, r28, 0x0080
- mtccr0 r28
-
- /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
- lis r28, 0xEF40
- addi r28, r28, 0x0004
- stw r31, 0x0C(r28) /* clear PMM0PCIHA */
- lis r29, 0xFFF8 /* open 512 kByte */
- addi r29, r29, 0x0001/* and enable this region */
- stwbrx r29, r0, r28 /* write PMM0MA */
-
- lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */
- addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */
-
- lis r31, 0x8000 /* set en bit bus 0 */
- ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
- stwbrx r31, r0, r28 /* write it */
-
- lwbrx r31, r0, r29 /* load XBCS register */
- oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
- stwbrx r31, r0, r29 /* write back XBCS register */
-
- nop
- nop
- b _start /* normal start */
-#endif
diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c
deleted file mode 100644
index 408518d..0000000
--- a/board/mpl/pip405/pip405.c
+++ /dev/null
@@ -1,958 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * TODO: clean-up
- */
-
-#include <common.h>
-#include "pip405.h"
-#include <asm/processor.h>
-#include <i2c.h>
-#include <stdio_dev.h>
-#include "../common/isa.h"
-#include "../common/common_util.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#undef SDRAM_DEBUG
-
-/* stdlib.h causes some compatibility problems; should fixe these! -- wd */
-#ifndef __ldiv_t_defined
-typedef struct {
- long int quot; /* Quotient */
- long int rem; /* Remainder */
-} ldiv_t;
-extern ldiv_t ldiv (long int __numer, long int __denom);
-
-# define __ldiv_t_defined 1
-#endif
-
-
-typedef enum {
- SDRAM_NO_ERR,
- SDRAM_SPD_COMM_ERR,
- SDRAM_SPD_CHKSUM_ERR,
- SDRAM_UNSUPPORTED_ERR,
- SDRAM_UNKNOWN_ERR
-} SDRAM_ERR;
-
-typedef struct {
- const unsigned char mode;
- const unsigned char row;
- const unsigned char col;
- const unsigned char bank;
-} SDRAM_SETUP;
-
-static const SDRAM_SETUP sdram_setup_table[] = {
- {1, 11, 9, 2},
- {1, 11, 10, 2},
- {2, 12, 9, 4},
- {2, 12, 10, 4},
- {3, 13, 9, 4},
- {3, 13, 10, 4},
- {3, 13, 11, 4},
- {4, 12, 8, 2},
- {4, 12, 8, 4},
- {5, 11, 8, 2},
- {5, 11, 8, 4},
- {6, 13, 8, 2},
- {6, 13, 8, 4},
- {7, 13, 9, 2},
- {7, 13, 10, 2},
- {0, 0, 0, 0}
-};
-
-static const unsigned char cal_indextable[] = {
- 9, 23, 25
-};
-
-
-/*
- * translate ns.ns/10 coding of SPD timing values
- * into 10 ps unit values
- */
-
-unsigned short NS10to10PS (unsigned char spd_byte, unsigned char spd_version)
-{
- unsigned short ns, ns10;
-
- /* isolate upper nibble */
- ns = (spd_byte >> 4) & 0x0F;
- /* isolate lower nibble */
- ns10 = (spd_byte & 0x0F);
-
- return (ns * 100 + ns10 * 10);
-}
-
-/*
- * translate ns.ns/4 coding of SPD timing values
- * into 10 ps unit values
- */
-
-unsigned short NS4to10PS (unsigned char spd_byte, unsigned char spd_version)
-{
- unsigned short ns, ns4;
-
- /* isolate upper 6 bits */
- ns = (spd_byte >> 2) & 0x3F;
- /* isloate lower 2 bits */
- ns4 = (spd_byte & 0x03);
-
- return (ns * 100 + ns4 * 25);
-}
-
-/*
- * translate ns coding of SPD timing values
- * into 10 ps unit values
- */
-
-unsigned short NSto10PS (unsigned char spd_byte)
-{
- return (spd_byte * 100);
-}
-
-void SDRAM_err (const char *s)
-{
-#ifndef SDRAM_DEBUG
- (void) get_clocks ();
- gd->baudrate = 9600;
- serial_init ();
-#endif
- serial_puts ("\n");
- serial_puts (s);
- serial_puts ("\n enable SDRAM_DEBUG for more info\n");
- for (;;);
-}
-
-
-#ifdef SDRAM_DEBUG
-
-void write_hex (unsigned char i)
-{
- char cc;
-
- cc = i >> 4;
- cc &= 0xf;
- if (cc > 9)
- serial_putc (cc + 55);
- else
- serial_putc (cc + 48);
- cc = i & 0xf;
- if (cc > 9)
- serial_putc (cc + 55);
- else
- serial_putc (cc + 48);
-}
-
-void write_4hex (unsigned long val)
-{
- write_hex ((unsigned char) (val >> 24));
- write_hex ((unsigned char) (val >> 16));
- write_hex ((unsigned char) (val >> 8));
- write_hex ((unsigned char) val);
-}
-
-#endif
-
-int board_early_init_f (void)
-{
- unsigned char datain[128];
- unsigned long sdram_size = 0;
- SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table;
- unsigned long memclk;
- unsigned long tmemclk = 0;
- unsigned long tmp, bank, baseaddr, bank_size;
- unsigned short i;
- unsigned char rows, cols, banks, sdram_banks, density;
- unsigned char supported_cal, trp_clocks, trcd_clocks, tras_clocks,
- trc_clocks;
- unsigned char cal_index, cal_val, spd_version, spd_chksum;
- unsigned char buf[8];
-#ifdef SDRAM_DEBUG
- unsigned char tctp_clocks;
-#endif
-
- /* set up the config port */
- mtdcr (EBC0_CFGADDR, PB7AP);
- mtdcr (EBC0_CFGDATA, CONFIG_PORT_AP);
- mtdcr (EBC0_CFGADDR, PB7CR);
- mtdcr (EBC0_CFGDATA, CONFIG_PORT_CR);
-
- memclk = get_bus_freq (tmemclk);
- tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */
-
-#ifdef SDRAM_DEBUG
- (void) get_clocks ();
- gd->baudrate = 9600;
- serial_init ();
- serial_puts ("\nstart SDRAM Setup\n");
-#endif
-
- /* Read Serial Presence Detect Information */
- i2c_set_bus_num(0);
- for (i = 0; i < 128; i++)
- datain[i] = 127;
- i2c_read(SPD_EEPROM_ADDRESS,0,1,datain,128);
-#ifdef SDRAM_DEBUG
- serial_puts ("\ni2c_read returns ");
- write_hex (i);
- serial_puts ("\n");
-#endif
-
-#ifdef SDRAM_DEBUG
- for (i = 0; i < 128; i++) {
- write_hex (datain[i]);
- serial_puts (" ");
- if (((i + 1) % 16) == 0)
- serial_puts ("\n");
- }
- serial_puts ("\n");
-#endif
- spd_chksum = 0;
- for (i = 0; i < 63; i++) {
- spd_chksum += datain[i];
- } /* endfor */
- if (datain[63] != spd_chksum) {
-#ifdef SDRAM_DEBUG
- serial_puts ("SPD chksum: 0x");
- write_hex (datain[63]);
- serial_puts (" != calc. chksum: 0x");
- write_hex (spd_chksum);
- serial_puts ("\n");
-#endif
- SDRAM_err ("SPD checksum Error");
- }
- /* SPD seems to be ok, use it */
-
- /* get SPD version */
- spd_version = datain[62];
-
- /* do some sanity checks on the kind of RAM */
- if ((datain[0] < 0x80) || /* less than 128 valid bytes in SPD */
- (datain[2] != 0x04) || /* if not SDRAM */
- (!((datain[6] == 0x40) || (datain[6] == 0x48))) || /* or not (64 Bit or 72 Bit) */
- (datain[7] != 0x00) || (datain[8] != 0x01) || /* or not LVTTL signal levels */
- (datain[126] == 0x66)) /* or a 66MHz modules */
- SDRAM_err ("unsupported SDRAM");
-#ifdef SDRAM_DEBUG
- serial_puts ("SDRAM sanity ok\n");
-#endif
-
- /* get number of rows/cols/banks out of byte 3+4+5 */
- rows = datain[3];
- cols = datain[4];
- banks = datain[5];
-
- /* get number of SDRAM banks out of byte 17 and
- supported CAS latencies out of byte 18 */
- sdram_banks = datain[17];
- supported_cal = datain[18] & ~0x81;
-
- while (t->mode != 0) {
- if ((t->row == rows) && (t->col == cols)
- && (t->bank == sdram_banks))
- break;
- t++;
- } /* endwhile */
-
-#ifdef SDRAM_DEBUG
- serial_puts ("rows: ");
- write_hex (rows);
- serial_puts (" cols: ");
- write_hex (cols);
- serial_puts (" banks: ");
- write_hex (banks);
- serial_puts (" mode: ");
- write_hex (t->mode);
- serial_puts ("\n");
-#endif
- if (t->mode == 0)
- SDRAM_err ("unsupported SDRAM");
- /* get tRP, tRCD, tRAS and density from byte 27+29+30+31 */
-#ifdef SDRAM_DEBUG
- serial_puts ("tRP: ");
- write_hex (datain[27]);
- serial_puts ("\ntRCD: ");
- write_hex (datain[29]);
- serial_puts ("\ntRAS: ");
- write_hex (datain[30]);
- serial_puts ("\n");
-#endif
-
- trp_clocks = (NSto10PS (datain[27]) + (tmemclk - 1)) / tmemclk;
- trcd_clocks = (NSto10PS (datain[29]) + (tmemclk - 1)) / tmemclk;
- tras_clocks = (NSto10PS (datain[30]) + (tmemclk - 1)) / tmemclk;
- density = datain[31];
-
- /* trc_clocks is sum of trp_clocks + tras_clocks */
- trc_clocks = trp_clocks + tras_clocks;
-
-#ifdef SDRAM_DEBUG
- /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
- tctp_clocks =
- ((NSto10PS (datain[30]) - NSto10PS (datain[29])) +
- (tmemclk - 1)) / tmemclk;
-
- serial_puts ("c_RP: ");
- write_hex (trp_clocks);
- serial_puts ("\nc_RCD: ");
- write_hex (trcd_clocks);
- serial_puts ("\nc_RAS: ");
- write_hex (tras_clocks);
- serial_puts ("\nc_RC: (RP+RAS): ");
- write_hex (trc_clocks);
- serial_puts ("\nc_CTP: ((RP+RAS)-RP-RCD): ");
- write_hex (tctp_clocks);
- serial_puts ("\nt_CTP: RAS - RCD: ");
- write_hex ((unsigned
- char) ((NSto10PS (datain[30]) -
- NSto10PS (datain[29])) >> 8));
- write_hex ((unsigned char) (NSto10PS (datain[30]) - NSto10PS (datain[29])));
- serial_puts ("\ntmemclk: ");
- write_hex ((unsigned char) (tmemclk >> 8));
- write_hex ((unsigned char) (tmemclk));
- serial_puts ("\n");
-#endif
-
-
- cal_val = 255;
- for (i = 6, cal_index = 0; (i > 0) && (cal_index < 3); i--) {
- /* is this CAS latency supported ? */
- if ((supported_cal >> i) & 0x01) {
- buf[0] = datain[cal_indextable[cal_index]];
- if (cal_index < 2) {
- if (NS10to10PS (buf[0], spd_version) <= tmemclk)
- cal_val = i;
- } else {
- /* SPD bytes 25+26 have another format */
- if (NS4to10PS (buf[0], spd_version) <= tmemclk)
- cal_val = i;
- } /* endif */
- cal_index++;
- } /* endif */
- } /* endfor */
-#ifdef SDRAM_DEBUG
- serial_puts ("CAL: ");
- write_hex (cal_val + 1);
- serial_puts ("\n");
-#endif
-
- if (cal_val == 255)
- SDRAM_err ("unsupported SDRAM");
-
- /* get SDRAM timing register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
- tmp = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
- /* insert CASL value */
-/* tmp |= ((unsigned long)cal_val) << 23; */
- tmp |= ((unsigned long) cal_val) << 23;
- /* insert PTA value */
- tmp |= ((unsigned long) (trp_clocks - 1)) << 18;
- /* insert CTP value */
-/* tmp |= ((unsigned long)(trc_clocks - trp_clocks - trcd_clocks - 1)) << 16; */
- tmp |= ((unsigned long) (trc_clocks - trp_clocks - trcd_clocks)) << 16;
- /* insert LDF (always 01) */
- tmp |= ((unsigned long) 0x01) << 14;
- /* insert RFTA value */
- tmp |= ((unsigned long) (trc_clocks - 4)) << 2;
- /* insert RCD value */
- tmp |= ((unsigned long) (trcd_clocks - 1)) << 0;
-
-#ifdef SDRAM_DEBUG
- serial_puts ("sdtr: ");
- write_4hex (tmp);
- serial_puts ("\n");
-#endif
-
- /* write SDRAM timing register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
- mtdcr (SDRAM0_CFGDATA, tmp);
- baseaddr = CONFIG_SYS_SDRAM_BASE;
- bank_size = (((unsigned long) density) << 22) / 2;
- /* insert AM value */
- tmp = ((unsigned long) t->mode - 1) << 13;
- /* insert SZ value; */
- switch (bank_size) {
- case 0x00400000:
- tmp |= ((unsigned long) 0x00) << 17;
- break;
- case 0x00800000:
- tmp |= ((unsigned long) 0x01) << 17;
- break;
- case 0x01000000:
- tmp |= ((unsigned long) 0x02) << 17;
- break;
- case 0x02000000:
- tmp |= ((unsigned long) 0x03) << 17;
- break;
- case 0x04000000:
- tmp |= ((unsigned long) 0x04) << 17;
- break;
- case 0x08000000:
- tmp |= ((unsigned long) 0x05) << 17;
- break;
- case 0x10000000:
- tmp |= ((unsigned long) 0x06) << 17;
- break;
- default:
- SDRAM_err ("unsupported SDRAM");
- } /* endswitch */
- /* get SDRAM bank 0 register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
- bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
- bank |= (baseaddr | tmp | 0x01);
-#ifdef SDRAM_DEBUG
- serial_puts ("bank0: baseaddr: ");
- write_4hex (baseaddr);
- serial_puts (" banksize: ");
- write_4hex (bank_size);
- serial_puts (" mb0cf: ");
- write_4hex (bank);
- serial_puts ("\n");
-#endif
- baseaddr += bank_size;
- sdram_size += bank_size;
-
- /* write SDRAM bank 0 register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
- mtdcr (SDRAM0_CFGDATA, bank);
-
- /* get SDRAM bank 1 register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
- bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
- sdram_size = 0;
-
-#ifdef SDRAM_DEBUG
- serial_puts ("bank1: baseaddr: ");
- write_4hex (baseaddr);
- serial_puts (" banksize: ");
- write_4hex (bank_size);
-#endif
- if (banks == 2) {
- bank |= (baseaddr | tmp | 0x01);
- baseaddr += bank_size;
- sdram_size += bank_size;
- } /* endif */
-#ifdef SDRAM_DEBUG
- serial_puts (" mb1cf: ");
- write_4hex (bank);
- serial_puts ("\n");
-#endif
- /* write SDRAM bank 1 register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
- mtdcr (SDRAM0_CFGDATA, bank);
-
- /* get SDRAM bank 2 register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
- bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
-
- bank |= (baseaddr | tmp | 0x01);
-
-#ifdef SDRAM_DEBUG
- serial_puts ("bank2: baseaddr: ");
- write_4hex (baseaddr);
- serial_puts (" banksize: ");
- write_4hex (bank_size);
- serial_puts (" mb2cf: ");
- write_4hex (bank);
- serial_puts ("\n");
-#endif
-
- baseaddr += bank_size;
- sdram_size += bank_size;
-
- /* write SDRAM bank 2 register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
- mtdcr (SDRAM0_CFGDATA, bank);
-
- /* get SDRAM bank 3 register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
- bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
-
-#ifdef SDRAM_DEBUG
- serial_puts ("bank3: baseaddr: ");
- write_4hex (baseaddr);
- serial_puts (" banksize: ");
- write_4hex (bank_size);
-#endif
-
- if (banks == 2) {
- bank |= (baseaddr | tmp | 0x01);
- baseaddr += bank_size;
- sdram_size += bank_size;
- }
- /* endif */
-#ifdef SDRAM_DEBUG
- serial_puts (" mb3cf: ");
- write_4hex (bank);
- serial_puts ("\n");
-#endif
-
- /* write SDRAM bank 3 register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
- mtdcr (SDRAM0_CFGDATA, bank);
-
-
- /* get SDRAM refresh interval register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
- tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
-
- if (tmemclk < NSto10PS (16))
- tmp |= 0x05F00000;
- else
- tmp |= 0x03F80000;
-
- /* write SDRAM refresh interval register */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
- mtdcr (SDRAM0_CFGDATA, tmp);
-
- /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
- tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80E00000;
- mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
- mtdcr (SDRAM0_CFGDATA, tmp);
-
-
- /*-------------------------------------------------------------------------+
- | Interrupt controller setup for the PIP405 board.
- | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
- | IRQ 16 405GP internally generated; active low; level sensitive
- | IRQ 17-24 RESERVED
- | IRQ 25 (EXT IRQ 0) SouthBridg; active low; level sensitive
- | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
- | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
- | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
- | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
- | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
- | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
- | Note for PIP405 board:
- | An interrupt taken for the SouthBridge (IRQ 25) indicates that
- | the Interrupt Controller in the South Bridge has caused the
- | interrupt. The IC must be read to determine which device
- | caused the interrupt.
- |
- +-------------------------------------------------------------------------*/
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr (UIC0ER, 0x00000000); /* disable all ints */
- mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */
- mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
- mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- int mode;
-
- /*
- * since we are relocated, we can finally enable i-cache
- * and set up the flash CS correctly
- */
- icache_enable();
- setup_cs_reloc();
- /* get and display boot mode */
- mode = get_boot_mode();
- if (mode & BOOT_PCI)
- printf("PCI Boot %s Map\n", (mode & BOOT_MPS) ?
- "MPS" : "Flash");
- else
- printf("%s Boot\n", (mode & BOOT_MPS) ?
- "MPS" : "Flash");
-
- return 0;
-}
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- char s[50];
- unsigned char bc;
- int i;
- backup_t *b = (backup_t *) s;
-
- puts ("Board: ");
-
- i = getenv_f("serial#", (char *)s, 32);
- if ((i == 0) || strncmp ((char *)s, "PIP405", 6)) {
- get_backup_values (b);
- if (strncmp (b->signature, "MPL\0", 4) != 0) {
- puts ("### No HW ID - assuming PIP405");
- } else {
- b->serial_name[6] = 0;
- printf ("%s SN: %s", b->serial_name,
- &b->serial_name[7]);
- }
- } else {
- s[6] = 0;
- printf ("%s SN: %s", s, &s[7]);
- }
- bc = in8 (CONFIG_PORT_ADDR);
- printf (" Boot Config: 0x%x\n", bc);
- return (0);
-}
-
-
-/* ------------------------------------------------------------------------- */
-/* ------------------------------------------------------------------------- */
-/*
- dram_init() reads EEPROM via I2c. EEPROM contains all of
- the necessary info for SDRAM controller configuration
-*/
-/* ------------------------------------------------------------------------- */
-/* ------------------------------------------------------------------------- */
-static int test_dram (unsigned long ramsize);
-
-int dram_init(void)
-{
- unsigned long bank_reg[4], tmp, bank_size;
- int i, ds;
- unsigned long TotalSize;
-
- ds = 0;
- /* since the DRAM controller is allready set up,
- * calculate the size with the bank registers
- */
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
- bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
- bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
- bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
- mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
- bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
- TotalSize = 0;
- for (i = 0; i < 4; i++) {
- if ((bank_reg[i] & 0x1) == 0x1) {
- tmp = (bank_reg[i] >> 17) & 0x7;
- bank_size = 4 << tmp;
- TotalSize += bank_size;
- } else
- ds = 1;
- }
- if (ds == 1)
- printf ("single-sided DIMM ");
- else
- printf ("double-sided DIMM ");
- test_dram (TotalSize * 1024 * 1024);
- /* bank 2 (SDRAM Clock 2) is not usable if 133MHz SDRAM IF */
- (void) get_clocks();
- if (gd->cpu_clk > 220000000)
- TotalSize /= 2;
- gd->ram_size = TotalSize * 1024 * 1024;
-
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-
-static int test_dram (unsigned long ramsize)
-{
- /* not yet implemented */
- return (1);
-}
-
-int misc_init_r (void)
-{
- /* adjust flash start and size as well as the offset */
- gd->bd->bi_flashstart=0-flash_info[0].size;
- gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN;
- gd->bd->bi_flashoffset=0;
-
- /* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
- if (mfdcr(CPC0_PSR) & PSR_ROM_LOC)
- mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
-
- return (0);
-}
-
-/***************************************************************************
- * some helping routines
- */
-
-int overwrite_console (void)
-{
- /* return true if console should be overwritten */
- return in8(CONFIG_PORT_ADDR) & 0x1;
-}
-
-
-extern int isa_init (void);
-
-
-void print_pip405_rev (void)
-{
- unsigned char part, vers, cfg;
-
- part = in8 (PLD_PART_REG);
- vers = in8 (PLD_VERS_REG);
- cfg = in8 (PLD_BOARD_CFG_REG);
- printf ("Rev: PIP405-%d Rev %c PLD%d %d PLD%d %d\n",
- 16 - ((cfg >> 4) & 0xf), (cfg & 0xf) + 'A', part & 0xf,
- vers & 0xf, (part >> 4) & 0xf, (vers >> 4) & 0xf);
-}
-
-extern void check_env(void);
-
-
-int last_stage_init (void)
-{
- print_pip405_rev ();
- isa_init ();
- stdio_print_current_devices ();
- check_env();
- return 0;
-}
-
-/************************************************************************
-* Print PIP405 Info
-************************************************************************/
-void print_pip405_info (void)
-{
- unsigned char part, vers, cfg, ledu, sysman, flashcom, can, serpwr,
- compwr, nicvga, scsirst;
-
- part = in8 (PLD_PART_REG);
- vers = in8 (PLD_VERS_REG);
- cfg = in8 (PLD_BOARD_CFG_REG);
- ledu = in8 (PLD_LED_USER_REG);
- sysman = in8 (PLD_SYS_MAN_REG);
- flashcom = in8 (PLD_FLASH_COM_REG);
- can = in8 (PLD_CAN_REG);
- serpwr = in8 (PLD_SER_PWR_REG);
- compwr = in8 (PLD_COM_PWR_REG);
- nicvga = in8 (PLD_NIC_VGA_REG);
- scsirst = in8 (PLD_SCSI_RST_REG);
- printf ("PLD Part %d version %d\n",
- part & 0xf, vers & 0xf);
- printf ("PLD Part %d version %d\n",
- (part >> 4) & 0xf, (vers >> 4) & 0xf);
- printf ("Board Revision %c\n", (cfg & 0xf) + 'A');
- printf ("Population Options %d %d %d %d\n",
- (cfg >> 4) & 0x1, (cfg >> 5) & 0x1,
- (cfg >> 6) & 0x1, (cfg >> 7) & 0x1);
- printf ("User LED0 %s User LED1 %s\n",
- ((ledu & 0x1) == 0x1) ? "on" : "off",
- ((ledu & 0x2) == 0x2) ? "on" : "off");
- printf ("Additionally Options %d %d\n",
- (ledu >> 2) & 0x1, (ledu >> 3) & 0x1);
- printf ("User Config Switch %d %d %d %d\n",
- (ledu >> 4) & 0x1, (ledu >> 5) & 0x1,
- (ledu >> 6) & 0x1, (ledu >> 7) & 0x1);
- switch (sysman & 0x3) {
- case 0:
- printf ("PCI Clocks are running\n");
- break;
- case 1:
- printf ("PCI Clocks are stopped in POS State\n");
- break;
- case 2:
- printf ("PCI Clocks are stopped when PCI_STP# is asserted\n");
- break;
- case 3:
- printf ("PCI Clocks are stopped\n");
- break;
- }
- switch ((sysman >> 2) & 0x3) {
- case 0:
- printf ("Main Clocks are running\n");
- break;
- case 1:
- printf ("Main Clocks are stopped in POS State\n");
- break;
- case 2:
- case 3:
- printf ("PCI Clocks are stopped\n");
- break;
- }
- printf ("INIT asserts %sINT2# (SMI)\n",
- ((sysman & 0x10) == 0x10) ? "" : "not ");
- printf ("INIT asserts %sINT1# (NMI)\n",
- ((sysman & 0x20) == 0x20) ? "" : "not ");
- printf ("INIT occurred %d\n", (sysman >> 6) & 0x1);
- printf ("SER1 is routed to %s\n",
- ((flashcom & 0x1) == 0x1) ? "RS485" : "RS232");
- printf ("COM2 is routed to %s\n",
- ((flashcom & 0x2) == 0x2) ? "RS485" : "RS232");
- printf ("RS485 is configured as %s duplex\n",
- ((flashcom & 0x4) == 0x4) ? "full" : "half");
- printf ("RS485 is connected to %s\n",
- ((flashcom & 0x8) == 0x8) ? "COM1" : "COM2");
- printf ("SER1 uses handshakes %s\n",
- ((flashcom & 0x10) == 0x10) ? "DTR/DSR" : "RTS/CTS");
- printf ("Bootflash is %swriteprotected\n",
- ((flashcom & 0x20) == 0x20) ? "not " : "");
- printf ("Bootflash VPP is %s\n",
- ((flashcom & 0x40) == 0x40) ? "on" : "off");
- printf ("Bootsector is %swriteprotected\n",
- ((flashcom & 0x80) == 0x80) ? "not " : "");
- switch ((can) & 0x3) {
- case 0:
- printf ("CAN Controller is on address 0x1000..0x10FF\n");
- break;
- case 1:
- printf ("CAN Controller is on address 0x8000..0x80FF\n");
- break;
- case 2:
- printf ("CAN Controller is on address 0xE000..0xE0FF\n");
- break;
- case 3:
- printf ("CAN Controller is disabled\n");
- break;
- }
- switch ((can >> 2) & 0x3) {
- case 0:
- printf ("CAN Controller Reset is ISA Reset\n");
- break;
- case 1:
- printf ("CAN Controller Reset is ISA Reset and POS State\n");
- break;
- case 2:
- case 3:
- printf ("CAN Controller is in reset\n");
- break;
- }
- if (((can >> 4) < 3) || ((can >> 4) == 8) || ((can >> 4) == 13))
- printf ("CAN Interrupt is disabled\n");
- else
- printf ("CAN Interrupt is ISA INT%d\n", (can >> 4) & 0xf);
- switch (serpwr & 0x3) {
- case 0:
- printf ("SER0 Drivers are enabled\n");
- break;
- case 1:
- printf ("SER0 Drivers are disabled in the POS state\n");
- break;
- case 2:
- case 3:
- printf ("SER0 Drivers are disabled\n");
- break;
- }
- switch ((serpwr >> 2) & 0x3) {
- case 0:
- printf ("SER1 Drivers are enabled\n");
- break;
- case 1:
- printf ("SER1 Drivers are disabled in the POS state\n");
- break;
- case 2:
- case 3:
- printf ("SER1 Drivers are disabled\n");
- break;
- }
- switch (compwr & 0x3) {
- case 0:
- printf ("COM1 Drivers are enabled\n");
- break;
- case 1:
- printf ("COM1 Drivers are disabled in the POS state\n");
- break;
- case 2:
- case 3:
- printf ("COM1 Drivers are disabled\n");
- break;
- }
- switch ((compwr >> 2) & 0x3) {
- case 0:
- printf ("COM2 Drivers are enabled\n");
- break;
- case 1:
- printf ("COM2 Drivers are disabled in the POS state\n");
- break;
- case 2:
- case 3:
- printf ("COM2 Drivers are disabled\n");
- break;
- }
- switch ((nicvga) & 0x3) {
- case 0:
- printf ("PHY is running\n");
- break;
- case 1:
- printf ("PHY is in Power save mode in POS state\n");
- break;
- case 2:
- case 3:
- printf ("PHY is in Power save mode\n");
- break;
- }
- switch ((nicvga >> 2) & 0x3) {
- case 0:
- printf ("VGA is running\n");
- break;
- case 1:
- printf ("VGA is in Power save mode in POS state\n");
- break;
- case 2:
- case 3:
- printf ("VGA is in Power save mode\n");
- break;
- }
- printf ("PHY is %sreseted\n", ((nicvga & 0x10) == 0x10) ? "" : "not ");
- printf ("VGA is %sreseted\n", ((nicvga & 0x20) == 0x20) ? "" : "not ");
- printf ("Reserved Configuration is %d %d\n", (nicvga >> 6) & 0x1,
- (nicvga >> 7) & 0x1);
- switch ((scsirst) & 0x3) {
- case 0:
- printf ("SCSI Controller is running\n");
- break;
- case 1:
- printf ("SCSI Controller is in Power save mode in POS state\n");
- break;
- case 2:
- case 3:
- printf ("SCSI Controller is in Power save mode\n");
- break;
- }
- printf ("SCSI termination is %s\n",
- ((scsirst & 0x4) == 0x4) ? "disabled" : "enabled");
- printf ("SCSI Controller is %sreseted\n",
- ((scsirst & 0x10) == 0x10) ? "" : "not ");
- printf ("IDE disks are %sreseted\n",
- ((scsirst & 0x20) == 0x20) ? "" : "not ");
- printf ("ISA Bus is %sreseted\n",
- ((scsirst & 0x40) == 0x40) ? "" : "not ");
- printf ("Super IO is %sreseted\n",
- ((scsirst & 0x80) == 0x80) ? "" : "not ");
-}
-
-void user_led0 (unsigned char on)
-{
- if (on == true)
- out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x1));
- else
- out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfe));
-}
-
-void user_led1 (unsigned char on)
-{
- if (on == true)
- out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x2));
- else
- out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfd));
-}
-
-void ide_set_reset (int idereset)
-{
- /* if reset = 1 IDE reset will be asserted */
- unsigned char resreg;
-
- resreg = in8 (PLD_SCSI_RST_REG);
- if (idereset == 1)
- resreg |= 0x20;
- else {
- udelay(10000);
- resreg &= 0xdf;
- }
- out8 (PLD_SCSI_RST_REG, resreg);
-}
diff --git a/board/mpl/pip405/pip405.h b/board/mpl/pip405/pip405.h
deleted file mode 100644
index 1f07d79..0000000
--- a/board/mpl/pip405/pip405.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
- /****************************************************************************
- * Global routines used for PIP405
- *****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-extern int mem_test(unsigned long start, unsigned long ramsize,int mode);
-
-void print_pip405_info(void);
-
-void user_led0(unsigned char on);
-void user_led1(unsigned char on);
-
-
-#define PLD_BASE_ADDRESS CONFIG_SYS_ISA_IO_BASE_ADDRESS + 0x800
-#define PLD_PART_REG PLD_BASE_ADDRESS + 0
-#define PLD_VERS_REG PLD_BASE_ADDRESS + 1
-#define PLD_BOARD_CFG_REG PLD_BASE_ADDRESS + 2
-#define PLD_LED_USER_REG PLD_BASE_ADDRESS + 3
-#define PLD_SYS_MAN_REG PLD_BASE_ADDRESS + 4
-#define PLD_FLASH_COM_REG PLD_BASE_ADDRESS + 5
-#define PLD_CAN_REG PLD_BASE_ADDRESS + 6
-#define PLD_SER_PWR_REG PLD_BASE_ADDRESS + 7
-#define PLD_COM_PWR_REG PLD_BASE_ADDRESS + 8
-#define PLD_NIC_VGA_REG PLD_BASE_ADDRESS + 9
-#define PLD_SCSI_RST_REG PLD_BASE_ADDRESS + 0xA
-
-#define PIIX4_VENDOR_ID 0x8086
-#define PIIX4_IDE_DEV_ID 0x7111
-
-#endif
-
-/* timings */
-
-/* CS Config register (CS7) */
-#define CONFIG_PORT_BME 0 /* Burst disable */
-#define CONFIG_PORT_TWE 255 /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
-#define CONFIG_PORT_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define CONFIG_PORT_OEN 1 /* Cycles from CS low to OE low */
-#define CONFIG_PORT_WBN 1 /* Cycles from CS low to WE low */
-#define CONFIG_PORT_WBF 1 /* Cycles from WE high to CS high */
-#define CONFIG_PORT_TH 2 /* Number of hold cycles after transfer */
-#define CONFIG_PORT_RE 0 /* Ready disabled */
-#define CONFIG_PORT_SOR 1 /* Sample on Ready disabled */
-#define CONFIG_PORT_BEM 0 /* Byte Write only active on Write cycles */
-#define CONFIG_PORT_PEN 0 /* Parity disable */
-#define CONFIG_PORT_AP ((CONFIG_PORT_BME << 31) + (CONFIG_PORT_TWE << 23) + (CONFIG_PORT_CSN << 18) + (CONFIG_PORT_OEN << 16) + (CONFIG_PORT_WBN << 14) + \
- (CONFIG_PORT_WBF << 12) + (CONFIG_PORT_TH << 9) + (CONFIG_PORT_RE << 8) + (CONFIG_PORT_SOR << 7) + (CONFIG_PORT_BEM << 6) + (CONFIG_PORT_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define CONFIG_PORT_BS 0 /* 1 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define CONFIG_PORT_BU 3 /* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define CONFIG_PORT_BW 0 /* 16Bit */
-#define CONFIG_PORT_CR ((CONFIG_PORT_ADDR & 0xfff00000) + (CONFIG_PORT_BS << 17) + (CONFIG_PORT_BU << 15) + (CONFIG_PORT_BW << 13))
-
-/* Flash CS0 or CS 1 */
-/* 0x7F8FFE80 slowest timing at all... */
-#define FLASH_BME_B 1 /* Burst enable */
-#define FLASH_FWT_B 0x6 /* 6 * 30ns 210ns First Wait Access */
-#define FLASH_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */
-#define FLASH_BME 0 /* Burst disable */
-#define FLASH_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
-#define FLASH_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define FLASH_OEN 1 /* Cycles from CS low to OE low */
-#define FLASH_WBN 1 /* Cycles from CS low to WE low */
-#define FLASH_WBF 1 /* Cycles from WE high to CS high */
-#define FLASH_TH 2 /* Number of hold cycles after transfer */
-#define FLASH_RE 0 /* Ready disabled */
-#define FLASH_SOR 1 /* Sample on Ready disabled */
-#define FLASH_BEM 0 /* Byte Write only active on Write cycles */
-#define FLASH_PEN 0 /* Parity disable */
-/* Access Parameter Register for non Boot */
-#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
- (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
-/* Access Parameter Register for Boot */
-#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
- (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define FLASH_BS FLASH_SIZE_PRELIM /* 4 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define FLASH_BU 3 /* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define FLASH_BW 1 /* 16Bit */
-/* CR register for Boot */
-#define FLASH_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
-/* CR register for non Boot */
-#define FLASH_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
-
-/* MPS CS1 or CS0 */
-/* Boot CS: */
-#define MPS_BME_B 1 /* Burst enable */
-#define MPS_FWT_B 0x6/* 6 * 30ns 210ns First Wait Access */
-#define MPS_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */
-#define MPS_BME 0 /* Burst disable */
-#define MPS_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
-#define MPS_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define MPS_OEN 1 /* Cycles from CS low to OE low */
-#define MPS_WBN 1 /* Cycles from CS low to WE low */
-#define MPS_WBF 1 /* Cycles from WE high to CS high */
-#define MPS_TH 2 /* Number of hold cycles after transfer */
-#define MPS_RE 0 /* Ready disabled */
-#define MPS_SOR 1 /* Sample on Ready disabled */
-#define MPS_BEM 0 /* Byte Write only active on Write cycles */
-#define MPS_PEN 0 /* Parity disable */
-/* Access Parameter Register for non Boot */
-#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
- (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
-/* Access Parameter Register for Boot */
-#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
- (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define MPS_BS 2 /* 4 MByte */
-#define MPS_BS_B FLASH_SIZE_PRELIM /* 1 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define MPS_BU 3 /* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define MPS_BW 0 /* 8Bit */
-/* CR register for Boot */
-#define MPS_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
-/* CR register for non Boot */
-#define MPS_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
diff --git a/board/mpl/pip405/u-boot.lds.debug b/board/mpl/pip405/u-boot.lds.debug
deleted file mode 100644
index 890f592..0000000
--- a/board/mpl/pip405/u-boot.lds.debug
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
-
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}