diff options
Diffstat (limited to 'board/scalys/grapeboard/eth.c')
-rw-r--r-- | board/scalys/grapeboard/eth.c | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/board/scalys/grapeboard/eth.c b/board/scalys/grapeboard/eth.c new file mode 100644 index 0000000..e02611a --- /dev/null +++ b/board/scalys/grapeboard/eth.c @@ -0,0 +1,77 @@ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <netdev.h> +#include <fm_eth.h> +#include <fsl_mdio.h> +#include <malloc.h> +#include <fsl_dtsec.h> +#include <asm/arch/soc.h> +#include <asm/arch-fsl-layerscape/config.h> +#include <asm/arch/fsl_serdes.h> + +#include <pfe_eth/pfe_eth.h> +#include <asm/arch-fsl-layerscape/immap_lsch2.h> +#include <i2c.h> + +#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO" +#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1" + + +void reset_phy(void) +{ + /* No PHY reset control from LS1012A */ +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FSL_PFE + struct mii_dev *bus; + struct mdio_info mac1_mdio_info; + struct mdio_info mac2_mdio_info; + + reset_phy(); + + init_pfe_scfg_dcfg_regs(); + + /* Initialize SGMIIA on MDIO1 */ + mac1_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR; + mac1_mdio_info.name = DEFAULT_PFE_MDIO_NAME; + + bus = ls1012a_mdio_init(&mac1_mdio_info); + if (!bus) { + printf("Failed to register mdio 1\n"); + return -1; + } + + /* Initialize SGMIIB on MDIO2 */ + mac2_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR; + mac2_mdio_info.name = DEFAULT_PFE_MDIO1_NAME; + + bus = ls1012a_mdio_init(&mac2_mdio_info); + if (!bus) { + printf("Failed to register mdio 2\n"); + return -1; + } + + /* Initialize PHYs on MDIO1 */ + ls1012a_set_mdio(0, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME)); + ls1012a_set_phy_address_mode(0, EMAC1_PHY_ADDR, PHY_INTERFACE_MODE_SGMII); + + ls1012a_set_mdio(1, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME)); + ls1012a_set_phy_address_mode(1, EMAC2_PHY_ADDR, PHY_INTERFACE_MODE_SGMII); + + /* Initialize TI83867CS PHY LEDs */ + miiphy_write(DEFAULT_PFE_MDIO_NAME,EMAC1_PHY_ADDR,0x18,0x61B6); + miiphy_write(DEFAULT_PFE_MDIO_NAME,EMAC2_PHY_ADDR,0x18,0x61B6); + + cpu_eth_init(bis); +#endif + return pci_eth_init(bis); +} |