diff options
Diffstat (limited to 'board/scalys/grapeboard')
| -rw-r--r-- | board/scalys/grapeboard/Kconfig | 59 | ||||
| -rw-r--r-- | board/scalys/grapeboard/Makefile | 13 | ||||
| -rw-r--r-- | board/scalys/grapeboard/PBL_0x33_0x05_750_250_1000.bin | bin | 0 -> 160 bytes | |||
| -rw-r--r-- | board/scalys/grapeboard/PBL_0x33_0x08_750_250_1000.bin | bin | 0 -> 160 bytes | |||
| -rw-r--r-- | board/scalys/grapeboard/PBL_0x35_0x08_750_250_1000.bin | bin | 0 -> 160 bytes | |||
| -rw-r--r-- | board/scalys/grapeboard/eth.c | 77 | ||||
| -rw-r--r-- | board/scalys/grapeboard/grapeboard.c | 219 | ||||
| -rw-r--r-- | board/scalys/grapeboard/ns_access.c | 73 | ||||
| -rw-r--r-- | board/scalys/grapeboard/usb_grapeboard.c | 103 | ||||
| -rw-r--r-- | board/scalys/grapeboard/usb_grapeboard.h | 14 |
10 files changed, 558 insertions, 0 deletions
diff --git a/board/scalys/grapeboard/Kconfig b/board/scalys/grapeboard/Kconfig new file mode 100644 index 0000000..b038577 --- /dev/null +++ b/board/scalys/grapeboard/Kconfig @@ -0,0 +1,59 @@ +if TARGET_GRAPEBOARD + +config SYS_BOARD + default "grapeboard" + +config SYS_VENDOR + default "scalys" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "grapeboard" + +menu "Grapeboard configuration options" + depends on TARGET_GRAPEBOARD + +choice + prompt "SERDES configuration for PCIE or SATA" + default SERDES_D_TO_SATA + +config SERDES_D_TO_PCIE + bool + prompt "Support PCIe" + +config SERDES_D_TO_SATA + bool + prompt "Support SATA (Eth1 disabled)" + +endchoice + +choice + prompt "U-boot environment configuration" + default STANDARD_UBOOT_CONFIG + +config STANDARD_UBOOT_CONFIG + bool + prompt "Standard flash target" + +config RESCUE_UBOOT_CONFIG + bool + prompt "Rescue flash target" + +endchoice + +config PBL_BINARY + bool + +config PBL_IMAGE + string + +config U_BOOT_PAD_TO + string + +endmenu + + + +endif diff --git a/board/scalys/grapeboard/Makefile b/board/scalys/grapeboard/Makefile new file mode 100644 index 0000000..ad75e40 --- /dev/null +++ b/board/scalys/grapeboard/Makefile @@ -0,0 +1,13 @@ +# +# Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += grapeboard.o +obj-y += eth.o +obj-y += usb_grapeboard.o + +obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ns_access.o + + diff --git a/board/scalys/grapeboard/PBL_0x33_0x05_750_250_1000.bin b/board/scalys/grapeboard/PBL_0x33_0x05_750_250_1000.bin Binary files differnew file mode 100644 index 0000000..43cfa77 --- /dev/null +++ b/board/scalys/grapeboard/PBL_0x33_0x05_750_250_1000.bin diff --git a/board/scalys/grapeboard/PBL_0x33_0x08_750_250_1000.bin b/board/scalys/grapeboard/PBL_0x33_0x08_750_250_1000.bin Binary files differnew file mode 100644 index 0000000..049d7bb --- /dev/null +++ b/board/scalys/grapeboard/PBL_0x33_0x08_750_250_1000.bin diff --git a/board/scalys/grapeboard/PBL_0x35_0x08_750_250_1000.bin b/board/scalys/grapeboard/PBL_0x35_0x08_750_250_1000.bin Binary files differnew file mode 100644 index 0000000..ad85162 --- /dev/null +++ b/board/scalys/grapeboard/PBL_0x35_0x08_750_250_1000.bin diff --git a/board/scalys/grapeboard/eth.c b/board/scalys/grapeboard/eth.c new file mode 100644 index 0000000..e02611a --- /dev/null +++ b/board/scalys/grapeboard/eth.c @@ -0,0 +1,77 @@ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <netdev.h> +#include <fm_eth.h> +#include <fsl_mdio.h> +#include <malloc.h> +#include <fsl_dtsec.h> +#include <asm/arch/soc.h> +#include <asm/arch-fsl-layerscape/config.h> +#include <asm/arch/fsl_serdes.h> + +#include <pfe_eth/pfe_eth.h> +#include <asm/arch-fsl-layerscape/immap_lsch2.h> +#include <i2c.h> + +#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO" +#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1" + + +void reset_phy(void) +{ + /* No PHY reset control from LS1012A */ +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FSL_PFE + struct mii_dev *bus; + struct mdio_info mac1_mdio_info; + struct mdio_info mac2_mdio_info; + + reset_phy(); + + init_pfe_scfg_dcfg_regs(); + + /* Initialize SGMIIA on MDIO1 */ + mac1_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR; + mac1_mdio_info.name = DEFAULT_PFE_MDIO_NAME; + + bus = ls1012a_mdio_init(&mac1_mdio_info); + if (!bus) { + printf("Failed to register mdio 1\n"); + return -1; + } + + /* Initialize SGMIIB on MDIO2 */ + mac2_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR; + mac2_mdio_info.name = DEFAULT_PFE_MDIO1_NAME; + + bus = ls1012a_mdio_init(&mac2_mdio_info); + if (!bus) { + printf("Failed to register mdio 2\n"); + return -1; + } + + /* Initialize PHYs on MDIO1 */ + ls1012a_set_mdio(0, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME)); + ls1012a_set_phy_address_mode(0, EMAC1_PHY_ADDR, PHY_INTERFACE_MODE_SGMII); + + ls1012a_set_mdio(1, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME)); + ls1012a_set_phy_address_mode(1, EMAC2_PHY_ADDR, PHY_INTERFACE_MODE_SGMII); + + /* Initialize TI83867CS PHY LEDs */ + miiphy_write(DEFAULT_PFE_MDIO_NAME,EMAC1_PHY_ADDR,0x18,0x61B6); + miiphy_write(DEFAULT_PFE_MDIO_NAME,EMAC2_PHY_ADDR,0x18,0x61B6); + + cpu_eth_init(bis); +#endif + return pci_eth_init(bis); +} diff --git a/board/scalys/grapeboard/grapeboard.c b/board/scalys/grapeboard/grapeboard.c new file mode 100644 index 0000000..60d2a14 --- /dev/null +++ b/board/scalys/grapeboard/grapeboard.c @@ -0,0 +1,219 @@ +/* + * Copyright 2017 Scalys B.V. + * opensource@scalys.com + * + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/fsl_serdes.h> +#ifdef CONFIG_FSL_LS_PPA +#include <asm/arch/ppa.h> +#endif +#include <asm/arch/mmu.h> +#include <asm/arch/soc.h> +#include <hwconfig.h> +#include <ahci.h> +#include <mmc.h> +#include <scsi.h> +#include <fsl_esdhc.h> +#include <environment.h> +#include <fsl_mmdc.h> +#include <netdev.h> +#include <fsl_sec.h> +#include <fsl_csu.h> +#include "usb_grapeboard.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* GPIO1 registers */ +#define CONFIG_SYS_GPIO1 0x2300000 +#define CONFIG_SYS_GPIO2 0x2310000 +#define GPIO_MASK(shift) (0x80000000 >> shift) + +/* ===================================================== + * Grapeboard ExPI mapping (* pin name at ls1012a side) + * Note: The secondary options require modified RCW. + * ===================================================== + * 3V3 -| 1 2|- 5V0 + * I2C_SDA -| 3 4|- 5V0 + * I2C_SCL -| 5 6|- GND + * CLK0_25MHZ -| 7 8|- UART_TXD + * GND -| 9 10|- UART_RXD + * GPIO1_27* -|11 12|- GPIO2_04* + * GPIO2_05* -|13 14|- GND + * GPIO2_06* -|15 16|- GPIO2_07* + * 3V3 -|17 18|- GPIO2_09* + * SPI_MOSI/GPIO1_24* -|19 20|- GND + * SPI_MISO/GPIO1_28* -|21 22|- GPIO2_10* + * SPI_CLK/GPIO1_29* -|23 24|- SPI_CE0/GPIO1_25* + * GND -|25 26|- SPI_CE1/GPIO1_26* + */ + +/* ExPI gpios */ +#define gpio1_27 GPIO_MASK(27) /* ExPI pin 11 */ +#define gpio2_04 GPIO_MASK(4) /* ExPI pin 12 */ +#define gpio2_05 GPIO_MASK(5) /* ExPI pin 13 */ +#define gpio2_06 GPIO_MASK(6) /* ExPI pin 15 */ +#define gpio2_07 GPIO_MASK(7) /* ExPI pin 16 */ +#define gpio2_09 GPIO_MASK(9) /* ExPI pin 18 */ +#define gpio2_10 GPIO_MASK(10) /* ExPI pin 22 */ + +/* M2 gpios */ +#define gpio1_22 GPIO_MASK(22) +#define gpio2_00 GPIO_MASK(0) +#define gpio2_01 GPIO_MASK(1) +#define gpio2_02 GPIO_MASK(2) +#define M2_CFG1 GPIO_MASK(11) /* gpio2_11 */ +#define M2_CFG0 GPIO_MASK(12) /* gpio2_12 */ +#define M2_CFG2 GPIO_MASK(13) /* gpio2_13 */ +#define M2_CFG3 GPIO_MASK(14) /* gpio2_14 */ + +/* Other gpios */ +#define QSPI_MUX_N_MASK (0x80000000 >> 3) /* gpio2_03 */ + +int checkboard(void) +{ + struct ccsr_gpio *pgpio = (void *)(CONFIG_SYS_GPIO2); + int m2_config = 0; + + puts("Board: Grape board\n"); + /* set QSPI chip select muxing to 0 */ + + setbits_be32(&pgpio->gpdir, QSPI_MUX_N_MASK); + clrbits_be32(&pgpio->gpdat, QSPI_MUX_N_MASK); + + usb_hub_init(); + + + /* M.2 init: read input values of M.2 config signals */ + clrbits_be32(&pgpio->gpdir, (M2_CFG0 | M2_CFG1 | M2_CFG2 | M2_CFG3)); + m2_config = (in_be32(&pgpio->gpdat) & (M2_CFG0 | M2_CFG1 | M2_CFG2 | M2_CFG3)); + + switch(m2_config >> 17) { + case 0: + printf("M.2: SATA SSD module found on M.2 port\n"); +#ifdef CONFIG_SERDES_D_TO_PCIE + printf("Warning: SERDES has not been configured in RCW for SATA!\n"); +#endif + break; + case 1: + printf("M.2: PCIe SSD module found on M.2 port\n"); +#ifdef CONFIG_SERDES_D_TO_SATA + printf("Warning: SERDES has not been configured in RCW for PCIe!\n"); +#endif + break; + case 0xf: + printf("M.2: No module detected on M.2 port\n"); + break; + default: + printf("M.2: A module has been detected on M.2 port(TODO: add module type)\n"); + break; + } + + return 0; +} + +int dram_init(void) +{ + static const struct fsl_mmdc_info mparam = { + 0x05180000, /* mdctl */ + 0x00030035, /* mdpdc */ + 0x12554000, /* mdotc */ + 0xbabf7954, /* mdcfg0 */ + 0xdb328f64, /* mdcfg1 */ + 0x01ff00db, /* mdcfg2 */ + 0x00001680, /* mdmisc */ + 0x0f3c8000, /* mdref */ + 0x00002000, /* mdrwd */ + 0x00bf1023, /* mdor */ + 0x0000003f, /* mdasp */ + 0x0000022a, /* mpodtctrl */ + 0xa1390003, /* mpzqhwctrl */ + }; + + mmdc_init(&mparam); + + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) + /* This will break-before-make MMU for DDR */ + update_early_mmu_table(); +#endif + + return 0; +} + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +int board_init(void) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + + CONFIG_SYS_CCI400_OFFSET); + /* + * Set CCI-400 control override register to enable barrier + * transaction + */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 + erratum_a010315(); +#endif + +#ifdef CONFIG_ENV_IS_NOWHERE + gd->env_addr = (ulong)&default_environment[0]; +#endif + +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif + return 0; +} + +int esdhc_status_fixup(void *blob, const char *compat) +{ + /*char esdhc0_path[] = "/soc/esdhc@1560000";*/ + + return 0; +} + +void scsi_init(void) +{ +#if defined(CONFIG_SCSI_AHCI_PLAT) && defined(CONFIG_SERDES_D_TO_SATA) + struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; + + /* Disable SATA ECC */ + out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000); + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); + + ahci_init((void __iomem *)CONFIG_SYS_SATA); + scsi_scan(0); +#else + printf("Disabled\n"); +#endif +} + + +int ft_board_setup(void *blob, bd_t *bd) +{ + arch_fixup_fdt(blob); + + ft_cpu_setup(blob, bd); + + return 0; +} diff --git a/board/scalys/grapeboard/ns_access.c b/board/scalys/grapeboard/ns_access.c new file mode 100644 index 0000000..0c3a54c --- /dev/null +++ b/board/scalys/grapeboard/ns_access.c @@ -0,0 +1,73 @@ +/* + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <fsl_csu.h> +#include <asm/arch/ns_access.h> +#include <asm/arch/fsl_serdes.h> + +void set_devices_ns_access(unsigned long index, u16 val) +{ + u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR; + u32 *reg; + uint32_t tmp; + + reg = base + index / 2; + tmp = in_be32(reg); + if (index % 2 == 0) { + tmp &= 0x0000ffff; + tmp |= val << 16; + } else { + tmp &= 0xffff0000; + tmp |= val; + } + + out_be32(reg, tmp); +} + +static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num) +{ + int i; + + for (i = 0; i < num; i++) + set_devices_ns_access(ns_dev[i].ind, ns_dev[i].val); +} + +void enable_layerscape_ns_access(void) +{ +#ifdef CONFIG_ARM64 + if (current_el() == 3) +#endif + enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); +} + +void set_pcie_ns_access(int pcie, u16 val) +{ + switch (pcie) { +#ifdef CONFIG_PCIE1 + case PCIE1: + set_devices_ns_access(CSU_CSLX_PCIE1, val); + set_devices_ns_access(CSU_CSLX_PCIE1_IO, val); + return; +#endif +#ifdef CONFIG_PCIE2 + case PCIE2: + set_devices_ns_access(CSU_CSLX_PCIE2, val); + set_devices_ns_access(CSU_CSLX_PCIE2_IO, val); + return; +#endif +#ifdef CONFIG_PCIE3 + case PCIE3: + set_devices_ns_access(CSU_CSLX_PCIE3, val); + set_devices_ns_access(CSU_CSLX_PCIE3_IO, val); + return; +#endif + default: + debug("The PCIE%d doesn't exist!\n", pcie); + return; + } +} diff --git a/board/scalys/grapeboard/usb_grapeboard.c b/board/scalys/grapeboard/usb_grapeboard.c new file mode 100644 index 0000000..176c4be --- /dev/null +++ b/board/scalys/grapeboard/usb_grapeboard.c @@ -0,0 +1,103 @@ +/* + * Copyright 2017 Scalys B.V. + * opensource@scalys.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <asm/io.h> + +#define MIN(X,Y) ((X) < (Y) ? (X) : (Y)) + +#define I2C_ADDRESS_USB_HUB 0x60 +#define MAX_I2C_ATTEMPTS 10 + +#define HX3_SETTINGS_SIZE 192 + +/* Cypress HX3 hub settings blob */ +const uint8_t hx3_settings[5 + HX3_SETTINGS_SIZE] = { + 'C', 'Y', /* Cypress magic signature */ + 0x30, /* I2C speed : 100kHz */ + 0xd4, /* Image type: Only settings, no firmware */ + HX3_SETTINGS_SIZE, /* payload size (192) */ + 0xb4, 0x04, /* VID */ + 0x04, 0x65, /* PID */ + 0x0a, 0x50, /* DID */ + 0x00, /* Reserved */ + 0x0f, /* 4 SuperSpeed ports, no shared link */ + 0x32, /* bPwrOn2PwrGood : 100 ms */ + 0x7f, /* 4 Downstream ports : DS4 is non-removable (MCU) */ + 0xe1, /* LEDs disabled, Ganged power switching */ + 0xa0, /* suspend indicator disabled, power switch control is active high */ + 0x04, /* BC v1.2 disabled, apple charging 1A, ghost charging disabled */ + 0x00, /* port charging, cdp & dcp disabled */ + 0xd8, /* US is embedded port, overcurrent input is active high */ + 0x00, /* reserved */ + 0x08, /* USB String descriptors enabled */ + 0x00, 0x00, + 0x12, 0x00, 0x2c, + 0x66, 0x66, /* USB3.0 TX driver de-emphasis */ + 0x69, 0x29, 0x29, 0x29, 0x29, /* TX amplitude */ + 0x00, /* Reserved */ + 0x06, 0x65, /* USB 2.0 PID */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* Reserved */ + 0x04, 0x03, 0x09, 0x04, /* LangID = 0x0409 US English */ + 0x18, 0x03, /* Manufacturer string descriptor */ + 0x32, 0x00, 0x30, 0x00, 0x31, 0x00, 0x37, 0x00, + 0x20, 0x00, 0x53, 0x00, 0x63, 0x00, 0x61, 0x00, + 0x6c, 0x00, 0x79, 0x00, 0x73, 0x00, + 0x2c, 0x03, /* Product string descriptor */ + 0x47, 0x00, 0x72, 0x00, 0x61, 0x00, 0x70, 0x00, + 0x65, 0x00, 0x62, 0x00, 0x6f, 0x00, 0x61, 0x00, + 0x72, 0x00, 0x64, 0x00, 0x20, 0x00, 0x43, 0x00, + 0x59, 0x00, 0x2d, 0x00, 0x48, 0x00, 0x58, 0x00, + 0x33, 0x00, 0x20, 0x00, 0x48, 0x00, 0x55, 0x00, + 0x42, 0x00, + 0x1a, 0x03, /* Serial string descriptor */ + 0x47, 0x00, 0x72, 0x00, 0x61, 0x00, 0x70, 0x00, + 0x65, 0x00, 0x62, 0x00, 0x6f, 0x00, 0x61, 0x00, + 0x72, 0x00, 0x64, 0x00, 0x20, 0x00, 0x31, 0x00, + 0x39, 0x00, 0x41, 0x00, + 0x00 +}; + +int usb_hub_init(void) { + int length, index = 0, i2c_attempts = 0; + const int settings_size = sizeof(hx3_settings); + uint8_t *data = (uint8_t *)hx3_settings; + + /* + * Configure USB hub slave + * + * The Hx3 starts in an i2c slave bootloader mode until sufficient and correct data is written to it over I2C. + * If transferred data is incorrect then the device will hang until it has been reset. + */ + puts("USB: configuring hub...."); + + while(index <= settings_size - 1){ + length = MIN(64, (settings_size - index)); + + if(i2c_write(I2C_ADDRESS_USB_HUB, index, 2, data, length)) { + if(i2c_attempts < 1) + printf("\nI2C error during configuring USB hub slave. retrying...\n"); + if(++i2c_attempts >= MAX_I2C_ATTEMPTS){ + printf("ERROR: Maximum USB hub configuration attempts reached. Exiting now\n"); + return 1; + } + continue; + } + i2c_attempts = 0; /* reset error count */ + index += length; + data += length; + } + + puts("Done!\n"); + return 0; +} + +int usb_hub_reset(void) { + /* USB hub cannot be reset in software without resetting the ls1012a */ + return 1; +} diff --git a/board/scalys/grapeboard/usb_grapeboard.h b/board/scalys/grapeboard/usb_grapeboard.h new file mode 100644 index 0000000..b57f102 --- /dev/null +++ b/board/scalys/grapeboard/usb_grapeboard.h @@ -0,0 +1,14 @@ +/* + * Copyright 2017 Scalys B.V. + * opensource@scalys.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef USB_GRAPEBOARD_H_ +#define USB_GRAPEBOARD_H_ + +int usb_hub_init(void); +int usb_hub_reset(void); + +#endif /* USB_GRAPEBOARD_H_ */ |