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-rw-r--r--board/sunxi/Makefile1
-rw-r--r--board/sunxi/gmac.c32
2 files changed, 33 insertions, 0 deletions
diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile
index 18b1e11..cbf8f08 100644
--- a/board/sunxi/Makefile
+++ b/board/sunxi/Makefile
@@ -9,4 +9,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += board.o
+obj-$(CONFIG_SUNXI_GMAC) += gmac.o
obj-$(CONFIG_CUBIETRUCK) += dram_cubietruck.o
diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
new file mode 100644
index 0000000..e48328d
--- /dev/null
+++ b/board/sunxi/gmac.c
@@ -0,0 +1,32 @@
+#include <common.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+
+int sunxi_gmac_initialize(bd_t *bis)
+{
+ int pin;
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* Set up clock gating */
+ setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
+
+ /* Set MII clock */
+ setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
+ CCM_GMAC_CTRL_GPIT_RGMII);
+
+ /* Configure pin mux settings for GMAC */
+ for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
+ /* skip unused pins in RGMII mode */
+ if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
+ continue;
+ sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC);
+ sunxi_gpio_set_drv(pin, 3);
+ }
+
+ return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
+}