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-rw-r--r--board/xes/xpedite517x/ddr.c25
-rw-r--r--board/xes/xpedite520x/ddr.c17
-rw-r--r--board/xes/xpedite537x/ddr.c17
-rw-r--r--board/xes/xpedite550x/ddr.c15
4 files changed, 4 insertions, 70 deletions
diff --git a/board/xes/xpedite517x/ddr.c b/board/xes/xpedite517x/ddr.c
index 981bf41..3a6e297 100644
--- a/board/xes/xpedite517x/ddr.c
+++ b/board/xes/xpedite517x/ddr.c
@@ -26,35 +26,12 @@
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
-static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
{
i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
sizeof(ddr2_spd_eeprom_t));
}
-void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
- unsigned int ctrl_num)
-{
- unsigned int i;
- unsigned int i2c_address = 0;
-
- for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
- if (ctrl_num == 0) {
- i2c_address = SPD_EEPROM_ADDRESS1;
-#ifdef SPD_EEPROM_ADDRESS2
- } else if (ctrl_num == 1) {
- i2c_address = SPD_EEPROM_ADDRESS2;
-#endif
- } else {
- /* An inalid ctrl number was give, use default SPD */
- printf("ERROR: invalid DDR ctrl: %d\n", ctrl_num);
- i2c_address = SPD_EEPROM_ADDRESS1;
- }
-
- get_spd(&(ctrl_dimms_spd[i]), i2c_address);
- }
-}
-
/*
* There are four board-specific SDRAM timing parameters which must be
* calculated based on the particular PCB artwork. These are:
diff --git a/board/xes/xpedite520x/ddr.c b/board/xes/xpedite520x/ddr.c
index f8d945a..3671cb8 100644
--- a/board/xes/xpedite520x/ddr.c
+++ b/board/xes/xpedite520x/ddr.c
@@ -12,8 +12,7 @@
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
-static void
-get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
{
i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
@@ -27,20 +26,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
}
}
-void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
- unsigned int ctrl_num)
-{
- unsigned int i;
-
- if (ctrl_num) {
- printf("%s: invalid ctrl_num = %d\n", __func__, ctrl_num);
- return;
- }
-
- for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++)
- get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
-}
-
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
diff --git a/board/xes/xpedite537x/ddr.c b/board/xes/xpedite537x/ddr.c
index 307f875..d0662b0 100644
--- a/board/xes/xpedite537x/ddr.c
+++ b/board/xes/xpedite537x/ddr.c
@@ -27,27 +27,12 @@
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
-static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
{
i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
sizeof(ddr2_spd_eeprom_t));
}
-void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
- unsigned int ctrl_num)
-{
- unsigned int i;
- unsigned int i2c_address = 0;
-
- for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
- if (ctrl_num == 0)
- i2c_address = SPD_EEPROM_ADDRESS1;
- if (ctrl_num == 1)
- i2c_address = SPD_EEPROM_ADDRESS2;
- get_spd(&(ctrl_dimms_spd[i]), i2c_address);
- }
-}
-
/*
* There are four board-specific SDRAM timing parameters which must be
* calculated based on the particular PCB artwork. These are:
diff --git a/board/xes/xpedite550x/ddr.c b/board/xes/xpedite550x/ddr.c
index 9e69649..3b6e08b 100644
--- a/board/xes/xpedite550x/ddr.c
+++ b/board/xes/xpedite550x/ddr.c
@@ -27,25 +27,12 @@
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
-static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
+void get_spd(ddr3_spd_eeprom_t *spd, u8 i2c_address)
{
i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
sizeof(ddr3_spd_eeprom_t));
}
-void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
- unsigned int ctrl_num)
-{
- unsigned int i;
- unsigned int i2c_address = 0;
-
- for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
- if (ctrl_num == 0 && i == 0)
- i2c_address = SPD_EEPROM_ADDRESS1;
- get_spd(&(ctrl_dimms_spd[i]), i2c_address);
- }
-}
-
/*
* There are traditionally three board-specific SDRAM timing parameters
* which must be calculated based on the particular PCB artwork. These are: