diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/BuR/common/bur_common.h | 2 | ||||
| -rw-r--r-- | board/BuR/common/common.c | 2 | ||||
| -rw-r--r-- | board/BuR/kwb/MAINTAINERS | 2 | ||||
| -rw-r--r-- | board/BuR/kwb/Makefile | 2 | ||||
| -rw-r--r-- | board/BuR/kwb/board.c | 2 | ||||
| -rw-r--r-- | board/BuR/kwb/mux.c | 2 | ||||
| -rw-r--r-- | board/BuR/tseries/MAINTAINERS | 2 | ||||
| -rw-r--r-- | board/BuR/tseries/Makefile | 2 | ||||
| -rw-r--r-- | board/BuR/tseries/board.c | 2 | ||||
| -rw-r--r-- | board/BuR/tseries/mux.c | 2 | ||||
| -rw-r--r-- | board/renesas/alt/Kconfig | 9 | ||||
| -rw-r--r-- | board/renesas/alt/alt.c | 17 | ||||
| -rw-r--r-- | board/renesas/alt/qos.c | 76 | ||||
| -rw-r--r-- | board/renesas/gose/qos.c | 72 | ||||
| -rw-r--r-- | board/renesas/koelsch/qos.c | 104 | ||||
| -rw-r--r-- | board/renesas/lager/qos.c | 69 | ||||
| -rw-r--r-- | board/sunxi/Kconfig | 43 | ||||
| -rw-r--r-- | board/sunxi/MAINTAINERS | 2 | ||||
| -rw-r--r-- | board/sunxi/board.c | 21 |
19 files changed, 356 insertions, 77 deletions
diff --git a/board/BuR/common/bur_common.h b/board/BuR/common/bur_common.h index e4896fb..ded69e7 100644 --- a/board/BuR/common/bur_common.h +++ b/board/BuR/common/bur_common.h @@ -3,7 +3,7 @@ * * common board information header for B&R boards * - * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> + * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com * * SPDX-License-Identifier: GPL-2.0+ diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index 5b356fb..7830d1a 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -3,7 +3,7 @@ * * common board functions for B&R boards * - * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> + * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com * * SPDX-License-Identifier: GPL-2.0+ diff --git a/board/BuR/kwb/MAINTAINERS b/board/BuR/kwb/MAINTAINERS index c28fb49..ca7d329 100644 --- a/board/BuR/kwb/MAINTAINERS +++ b/board/BuR/kwb/MAINTAINERS @@ -1,5 +1,5 @@ KWB BOARD -M: Hannes Petermaier <hannes.petermaier@br-automation.com> +M: Hannes Schmelzer <hannes.schmelzer@br-automation.com> S: Maintained F: board/BuR/kwb/ F: include/configs/kwb.h diff --git a/board/BuR/kwb/Makefile b/board/BuR/kwb/Makefile index 7b04b26..782664c 100644 --- a/board/BuR/kwb/Makefile +++ b/board/BuR/kwb/Makefile @@ -1,7 +1,7 @@ # # Makefile # -# Copyright (C) 2014 Hannes Petermaier <oe5hpm@oevsv.at> - +# Copyright (C) 2014 Hannes Schmelzer <oe5hpm@oevsv.at> - # Bernecker & Rainer Industrielektronik GmbH - http://www.br-automation.com/ # # SPDX-License-Identifier: GPL-2.0+ diff --git a/board/BuR/kwb/board.c b/board/BuR/kwb/board.c index 01dd1d9..640aca4 100644 --- a/board/BuR/kwb/board.c +++ b/board/BuR/kwb/board.c @@ -3,7 +3,7 @@ * * Board functions for B&R KWB Board * - * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> + * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com * * SPDX-License-Identifier: GPL-2.0+ diff --git a/board/BuR/kwb/mux.c b/board/BuR/kwb/mux.c index 2b1d8d3..40224f7 100644 --- a/board/BuR/kwb/mux.c +++ b/board/BuR/kwb/mux.c @@ -3,7 +3,7 @@ * * Pinmux Setting for B&R LEIT Board(s) * - * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> + * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com * * SPDX-License-Identifier: GPL-2.0+ diff --git a/board/BuR/tseries/MAINTAINERS b/board/BuR/tseries/MAINTAINERS index e57326a..e2e67e6 100644 --- a/board/BuR/tseries/MAINTAINERS +++ b/board/BuR/tseries/MAINTAINERS @@ -1,5 +1,5 @@ TSERIES BOARD -M: Hannes Petermaier <hannes.petermaier@br-automation.com> +M: Hannes Schmelzer <hannes.schmelzer@br-automation.com> S: Maintained F: board/BuR/tseries/ F: include/configs/tseries.h diff --git a/board/BuR/tseries/Makefile b/board/BuR/tseries/Makefile index ec0d27a..43945d2 100644 --- a/board/BuR/tseries/Makefile +++ b/board/BuR/tseries/Makefile @@ -1,7 +1,7 @@ # # Makefile # -# Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> +# Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> # Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com # # SPDX-License-Identifier: GPL-2.0+ diff --git a/board/BuR/tseries/board.c b/board/BuR/tseries/board.c index d1d698e..bc119e6 100644 --- a/board/BuR/tseries/board.c +++ b/board/BuR/tseries/board.c @@ -3,7 +3,7 @@ * * Board functions for B&R LEIT Board * - * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> + * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com * * SPDX-License-Identifier: GPL-2.0+ diff --git a/board/BuR/tseries/mux.c b/board/BuR/tseries/mux.c index c5dc4b7..349788a 100644 --- a/board/BuR/tseries/mux.c +++ b/board/BuR/tseries/mux.c @@ -3,7 +3,7 @@ * * Pinmux Setting for B&R LEIT Board(s) * - * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> + * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com * * SPDX-License-Identifier: GPL-2.0+ diff --git a/board/renesas/alt/Kconfig b/board/renesas/alt/Kconfig index 957962d..39d53c1 100644 --- a/board/renesas/alt/Kconfig +++ b/board/renesas/alt/Kconfig @@ -9,4 +9,13 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "alt" +config R8A7794_ETHERNET_B + bool "Use ethernet B function" + depends on TARGET_ALT + default n + help + ALT board can use default ethernet and etnernet B function. + This config set pin function of ethenet B. You also needt to change + DIP switch of board in order to use this function. + endif diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c index f0010db..3501a17 100644 --- a/board/renesas/alt/alt.c +++ b/board/renesas/alt/alt.c @@ -1,7 +1,7 @@ /* * board/renesas/alt/alt.c * - * Copyright (C) 2014 Renesas Electronics Corporation + * Copyright (C) 2014, 2015 Renesas Electronics Corporation * * SPDX-License-Identifier: GPL-2.0 */ @@ -94,6 +94,20 @@ int board_init(void) r8a7794_pinmux_init(); /* Ether Enable */ +#if defined(CONFIG_R8A7794_ETHERNET_B) + gpio_request(GPIO_FN_ETH_CRS_DV_B, NULL); + gpio_request(GPIO_FN_ETH_RX_ER_B, NULL); + gpio_request(GPIO_FN_ETH_RXD0_B, NULL); + gpio_request(GPIO_FN_ETH_RXD1_B, NULL); + gpio_request(GPIO_FN_ETH_LINK_B, NULL); + gpio_request(GPIO_FN_ETH_REFCLK_B, NULL); + gpio_request(GPIO_FN_ETH_MDIO_B, NULL); + gpio_request(GPIO_FN_ETH_TXD1_B, NULL); + gpio_request(GPIO_FN_ETH_TX_EN_B, NULL); + gpio_request(GPIO_FN_ETH_MAGIC_B, NULL); + gpio_request(GPIO_FN_ETH_TXD0_B, NULL); + gpio_request(GPIO_FN_ETH_MDC_B, NULL); +#else gpio_request(GPIO_FN_ETH_CRS_DV, NULL); gpio_request(GPIO_FN_ETH_RX_ER, NULL); gpio_request(GPIO_FN_ETH_RXD0, NULL); @@ -106,6 +120,7 @@ int board_init(void) gpio_request(GPIO_FN_ETH_MAGIC, NULL); gpio_request(GPIO_FN_ETH_TXD0, NULL); gpio_request(GPIO_FN_ETH_MDC, NULL); +#endif gpio_request(GPIO_FN_IRQ8, NULL); /* PHY reset */ diff --git a/board/renesas/alt/qos.c b/board/renesas/alt/qos.c index f0b349f..b6324c8 100644 --- a/board/renesas/alt/qos.c +++ b/board/renesas/alt/qos.c @@ -14,7 +14,7 @@ #include <asm/arch/rmobile.h> #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) -/* QoS version 0.11 */ +/* QoS version 0.311 for ES1 and version 0.321 for ES2 */ enum { DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, @@ -62,6 +62,24 @@ static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = { [DBSC3_15] = DBSC3_0_QOS_W15_BASE, }; +#if defined(CONFIG_QOS_PRI_MEDIA) +#define is_qos_pri_media() 1 +#else +#define is_qos_pri_media() 0 +#endif + +#if defined(CONFIG_QOS_PRI_NORMAL) +#define is_qos_pri_normal() 1 +#else +#define is_qos_pri_normal() 0 +#endif + +#if defined(CONFIG_QOS_PRI_GFX) +#define is_qos_pri_gfx() 1 +#else +#define is_qos_pri_gfx() 0 +#endif + void qos_init(void) { int i; @@ -77,30 +95,57 @@ void qos_init(void) /* S3C -QoS */ s3c = (struct rcar_s3c *)S3C_BASE; - writel(0x1F0D0B0A, &s3c->s3crorr); - writel(0x1F0D0B09, &s3c->s3cworr); - + if (is_qos_pri_media()) { + writel(0x1F0B0604, &s3c->s3crorr); + writel(0x1F0E0705, &s3c->s3cworr); + } else if (is_qos_pri_normal()) { + writel(0x1F0B0908, &s3c->s3crorr); + writel(0x1F0E0A08, &s3c->s3cworr); + } else if (is_qos_pri_media()) { + writel(0x1F0B0B0B, &s3c->s3crorr); + writel(0x1F0E0C0C, &s3c->s3cworr); + } /* QoS Control Registers */ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE; writel(0x00890089, &s3c_qos->s3cqos0); writel(0x20960010, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); - writel(0x20AA2200, &s3c_qos->s3cqos3); + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos3); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos3); + else if (is_qos_pri_media()) + writel(0x20AA2100, &s3c_qos->s3cqos3); writel(0x00002032, &s3c_qos->s3cqos4); writel(0x20960010, &s3c_qos->s3cqos5); writel(0x20302030, &s3c_qos->s3cqos6); - writel(0x20AA2200, &s3c_qos->s3cqos7); + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos7); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos7); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos7); writel(0x00002032, &s3c_qos->s3cqos8); s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; writel(0x00890089, &s3c_qos->s3cqos0); writel(0x20960010, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); - writel(0x20AA2200, &s3c_qos->s3cqos3); + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos3); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos3); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos3); writel(0x00002032, &s3c_qos->s3cqos4); writel(0x20960010, &s3c_qos->s3cqos5); writel(0x20302030, &s3c_qos->s3cqos6); - writel(0x20AA2200, &s3c_qos->s3cqos7); + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos7); + else if (is_qos_pri_media()) + writel(0x20AA2200, &s3c_qos->s3cqos7); + else if (is_qos_pri_media()) + writel(0x20AA2100, &s3c_qos->s3cqos7); writel(0x00002032, &s3c_qos->s3cqos8); s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; @@ -115,7 +160,7 @@ void qos_init(void) writel(0x00002032, &s3c_qos->s3cqos8); s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; - writel(0x00820082, &s3c_qos->s3cqos0); + writel(0x00820092, &s3c_qos->s3cqos0); writel(0x20960020, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); writel(0x20AA20FA, &s3c_qos->s3cqos3); @@ -157,8 +202,13 @@ void qos_init(void) } /* CCI-400 -QoS */ - writel(0x20000800, CCI_400_MAXOT_1); - writel(0x20000800, CCI_400_MAXOT_2); + if (IS_R8A7794_ES2()) { + writel(0x20001000, CCI_400_MAXOT_1); + writel(0x20001000, CCI_400_MAXOT_2); + } else { + writel(0x20000800, CCI_400_MAXOT_1); + writel(0x20000800, CCI_400_MAXOT_2); + } writel(0x0000000C, CCI_400_QOSCNTL_1); writel(0x0000000C, CCI_400_QOSCNTL_2); @@ -166,7 +216,7 @@ void qos_init(void) /* Transaction Control (MXI) */ mxi = (struct rcar_mxi *)MXI_BASE; writel(0x00000013, &mxi->mxrtcr); - writel(0x00000013, &mxi->mxwtcr); + writel(0x00000016, &mxi->mxwtcr); writel(0x00780080, &mxi->mxsaar0); writel(0x02000800, &mxi->mxsaar1); @@ -449,7 +499,7 @@ void qos_init(void) /* QoS Register (RT-AXI) */ axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; - writel(0x00000000, &axi_qos->qosconf); + writel(0x00000001, &axi_qos->qosconf); writel(0x00002053, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); writel(0x00002030, &axi_qos->qosctset2); diff --git a/board/renesas/gose/qos.c b/board/renesas/gose/qos.c index 64e52cf..413ad11 100644 --- a/board/renesas/gose/qos.c +++ b/board/renesas/gose/qos.c @@ -14,7 +14,7 @@ #include <asm/arch/rmobile.h> #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) -/* QoS version 0.20 */ +/* QoS version 0.311 */ enum { DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09, @@ -61,6 +61,24 @@ static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = { [DBSC3_15] = DBSC3_0_QOS_W15_BASE, }; +#if defined(CONFIG_QOS_PRI_MEDIA) +#define is_qos_pri_media() 1 +#else +#define is_qos_pri_media() 0 +#endif + +#if defined(CONFIG_QOS_PRI_NORMAL) +#define is_qos_pri_normal() 1 +#else +#define is_qos_pri_normal() 0 +#endif + +#if defined(CONFIG_QOS_PRI_GFX) +#define is_qos_pri_gfx() 1 +#else +#define is_qos_pri_gfx() 0 +#endif + void qos_init(void) { int i; @@ -77,34 +95,62 @@ void qos_init(void) /* S3C -QoS */ s3c = (struct rcar_s3c *)S3C_BASE; writel(0x00000000, &s3c->s3cadsplcr); - writel(0x1F0B0908, &s3c->s3crorr); - writel(0x1F0C0A08, &s3c->s3cworr); - + if (is_qos_pri_media()) { + writel(0x1F0B0604, &s3c->s3crorr); + writel(0x1F0E0705, &s3c->s3cworr); + } else if (is_qos_pri_normal()) { + writel(0x1F0B0908, &s3c->s3crorr); + writel(0x1F0C0A08, &s3c->s3cworr); + } else if (is_qos_pri_gfx()) { + writel(0x1F0B0B0B, &s3c->s3crorr); + writel(0x1F0E0C0C, &s3c->s3cworr); + } /* QoS Control Registers */ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE; writel(0x00890089, &s3c_qos->s3cqos0); writel(0x20960010, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); - writel(0x20AA2200, &s3c_qos->s3cqos3); + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos3); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos3); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos3); writel(0x00002032, &s3c_qos->s3cqos4); writel(0x20960010, &s3c_qos->s3cqos5); writel(0x20302030, &s3c_qos->s3cqos6); - writel(0x20AA2200, &s3c_qos->s3cqos7); + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos7); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos7); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos7); writel(0x00002032, &s3c_qos->s3cqos8); s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; writel(0x00890089, &s3c_qos->s3cqos0); writel(0x20960010, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); - writel(0x20AA2200, &s3c_qos->s3cqos3); + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos3); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos3); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos3); writel(0x00002032, &s3c_qos->s3cqos4); writel(0x20960010, &s3c_qos->s3cqos5); writel(0x20302030, &s3c_qos->s3cqos6); - writel(0x20AA2200, &s3c_qos->s3cqos7); + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos7); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos7); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos4); writel(0x00002032, &s3c_qos->s3cqos8); s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; - writel(0x00820082, &s3c_qos->s3cqos0); + writel(0x00820092, &s3c_qos->s3cqos0); writel(0x20960020, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); writel(0x20AA20DC, &s3c_qos->s3cqos3); @@ -115,7 +161,7 @@ void qos_init(void) writel(0x00002032, &s3c_qos->s3cqos8); s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; - writel(0x00820082, &s3c_qos->s3cqos0); + writel(0x00820092, &s3c_qos->s3cqos0); writel(0x20960020, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); writel(0x20AA20FA, &s3c_qos->s3cqos3); @@ -166,11 +212,13 @@ void qos_init(void) /* Transaction Control (MXI) */ mxi = (struct rcar_mxi *)MXI_BASE; writel(0x00000013, &mxi->mxrtcr); - writel(0x00000013, &mxi->mxwtcr); + writel(0x00000016, &mxi->mxwtcr); writel(0x00200000, &mxi->mxs3cracr); writel(0x00200000, &mxi->mxs3cwacr); writel(0x00200000, &mxi->mxaxiracr); writel(0x00200000, &mxi->mxaxiwacr); + writel(0x00780080, &mxi->mxsaar0); + writel(0x02000800, &mxi->mxsaar1); /* QoS Control (MXI) */ mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE; @@ -554,7 +602,7 @@ void qos_init(void) /* QoS Register (RT-AXI) */ axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; - writel(0x00000000, &axi_qos->qosconf); + writel(0x00000001, &axi_qos->qosconf); writel(0x00002053, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); writel(0x00002030, &axi_qos->qosctset2); diff --git a/board/renesas/koelsch/qos.c b/board/renesas/koelsch/qos.c index d293e3d..8cb2b48 100644 --- a/board/renesas/koelsch/qos.c +++ b/board/renesas/koelsch/qos.c @@ -13,7 +13,7 @@ #include <asm/io.h> #include <asm/arch/rmobile.h> -/* QoS version 0.240 for ES1 and version 0.334 for ES2 */ +/* QoS version 0.240 for ES1 and version 0.411 for ES2 */ #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) enum { DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, @@ -99,6 +99,24 @@ static u32 dbsc3_1_w_qos_addr[DBSC3_NR] = { [DBSC3_15] = DBSC3_1_QOS_W15_BASE, }; +#if defined(CONFIG_QOS_PRI_MEDIA) +#define is_qos_pri_media() 1 +#else +#define is_qos_pri_media() 0 +#endif + +#if defined(CONFIG_QOS_PRI_NORMAL) +#define is_qos_pri_normal() 1 +#else +#define is_qos_pri_normal() 0 +#endif + +#if defined(CONFIG_QOS_PRI_GFX) +#define is_qos_pri_gfx() 1 +#else +#define is_qos_pri_gfx() 0 +#endif + void qos_init(void) { int i; @@ -124,8 +142,17 @@ void qos_init(void) /* writel(0x00DF1B0C, &s3c->s3cadsplcr); */ /* Ssplit All mode */ /* writel(0x00FF1B0C, &s3c->s3cadsplcr); */ - writel(0x1F0B0908, &s3c->s3crorr); - writel(0x1F0C0A08, &s3c->s3cworr); + + if (is_qos_pri_media()) { + writel(0x1F0B0604, &s3c->s3crorr); + writel(0x1F0E0705, &s3c->s3cworr); + } else if (is_qos_pri_normal()) { + writel(0x1F0B0908, &s3c->s3crorr); + writel(0x1F0E0A08, &s3c->s3cworr); + } else if (is_qos_pri_gfx()) { + writel(0x1F0B0B0B, &s3c->s3crorr); + writel(0x1F0E0C0C, &s3c->s3cworr); + } } else { writel(0x00FF1B1D, &s3c->s3cadsplcr); writel(0x1F0D0C0C, &s3c->s3crorr); @@ -136,26 +163,67 @@ void qos_init(void) writel(0x00890089, &s3c_qos->s3cqos0); writel(0x20960010, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); - writel(0x20AA2200, &s3c_qos->s3cqos3); + + if (IS_R8A7791_ES2()) { + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos3); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos3); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos3); + } else { + writel(0x20AA2200, &s3c_qos->s3cqos3); + } writel(0x00002032, &s3c_qos->s3cqos4); writel(0x20960010, &s3c_qos->s3cqos5); writel(0x20302030, &s3c_qos->s3cqos6); - writel(0x20AA2200, &s3c_qos->s3cqos7); + + if (IS_R8A7791_ES2()) { + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos7); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos7); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos7); + } else { + writel(0x20AA2200, &s3c_qos->s3cqos7); + } writel(0x00002032, &s3c_qos->s3cqos8); s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; writel(0x00890089, &s3c_qos->s3cqos0); writel(0x20960010, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); - writel(0x20AA2200, &s3c_qos->s3cqos3); + if (IS_R8A7791_ES2()) { + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos3); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos3); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos3); + } else { + writel(0x20AA2200, &s3c_qos->s3cqos3); + } writel(0x00002032, &s3c_qos->s3cqos4); writel(0x20960010, &s3c_qos->s3cqos5); writel(0x20302030, &s3c_qos->s3cqos6); - writel(0x20AA2200, &s3c_qos->s3cqos7); + if (IS_R8A7791_ES2()) { + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos7); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos7); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos7); + } else { + writel(0x20AA2200, &s3c_qos->s3cqos7); + } writel(0x00002032, &s3c_qos->s3cqos8); s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; - writel(0x00820082, &s3c_qos->s3cqos0); + if (IS_R8A7791_ES2()) + writel(0x80928092, &s3c_qos->s3cqos0); + else + writel(0x00820082, &s3c_qos->s3cqos0); writel(0x20960020, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); writel(0x20AA20DC, &s3c_qos->s3cqos3); @@ -166,7 +234,10 @@ void qos_init(void) writel(0x00002032, &s3c_qos->s3cqos8); s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; - writel(0x00820082, &s3c_qos->s3cqos0); + if (IS_R8A7791_ES2()) + writel(0x80928092, &s3c_qos->s3cqos0); + else + writel(0x00820082, &s3c_qos->s3cqos0); writel(0x20960020, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); writel(0x20AA20FA, &s3c_qos->s3cqos3); @@ -245,9 +316,15 @@ void qos_init(void) /* MXI -QoS */ /* Transaction Control (MXI) */ - mxi = (struct rcar_mxi *)MXI_BASE; + mxi = (struct rcar_mxi *)XI_BASE; writel(0x00000013, &mxi->mxrtcr); - writel(0x00000013, &mxi->mxwtcr); + if (IS_R8A7791_ES2()) { + writel(0x00000016, &mxi->mxwtcr); + writel(0x00780080, &mxi->mxsaar0); + writel(0x02000800, &mxi->mxsaar1); + } else { + writel(0x00000013, &mxi->mxwtcr); + } /* QoS Control (MXI) */ mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE; @@ -632,7 +709,10 @@ void qos_init(void) /* QoS Register (RT-AXI) */ axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; - writel(0x00000000, &axi_qos->qosconf); + if (IS_R8A7791_ES2()) + writel(0x00000001, &axi_qos->qosconf); + else + writel(0x00000000, &axi_qos->qosconf); writel(0x00002053, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); writel(0x00002030, &axi_qos->qosctset2); diff --git a/board/renesas/lager/qos.c b/board/renesas/lager/qos.c index dec37d2..ae15551 100644 --- a/board/renesas/lager/qos.c +++ b/board/renesas/lager/qos.c @@ -12,7 +12,7 @@ #include <asm/io.h> #include <asm/arch/rmobile.h> -/* QoS version 0.955 for ES1 and version 0.963 for ES2 */ +/* QoS version 0.955 for ES1 and version 0.973 for ES2 */ #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) enum { DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, @@ -1133,6 +1133,24 @@ static void qos_init_es1(void) writel(0x00000000, &axi_qos->qosqon); } +#if defined(CONFIG_QOS_PRI_MEDIA) +#define is_qos_pri_media() 1 +#else +#define is_qos_pri_media() 0 +#endif + +#if defined(CONFIG_QOS_PRI_NORMAL) +#define is_qos_pri_normal() 1 +#else +#define is_qos_pri_normal() 0 +#endif + +#if defined(CONFIG_QOS_PRI_GFX) +#define is_qos_pri_gfx() 1 +#else +#define is_qos_pri_gfx() 0 +#endif + /* QoS version 0.963 for ES2 */ static void qos_init_es2(void) { @@ -1150,30 +1168,57 @@ static void qos_init_es2(void) /* S3C -QoS */ s3c = (struct rcar_s3c *)S3C_BASE; writel(0x80000000, &s3c->s3cadsplcr); - writel(0x1F060504, &s3c->s3crorr); - writel(0x1F060503, &s3c->s3cworr); - + if (is_qos_pri_media()) { + writel(0x1F060302, &s3c->s3crorr); + writel(0x07070302, &s3c->s3cworr); + } else if (is_qos_pri_normal()) { + writel(0x1F060504, &s3c->s3crorr); + writel(0x07070503, &s3c->s3cworr); + } else if (is_qos_pri_gfx()) { + writel(0x1F060606, &s3c->s3crorr); + writel(0x07070606, &s3c->s3cworr); + } /* QoS Control Registers */ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE; writel(0x00890089, &s3c_qos->s3cqos0); writel(0x20960010, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); - writel(0x20AA2200, &s3c_qos->s3cqos3); + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos3); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos3); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos3); writel(0x00002032, &s3c_qos->s3cqos4); writel(0x20960010, &s3c_qos->s3cqos5); writel(0x20302030, &s3c_qos->s3cqos6); - writel(0x20AA2200, &s3c_qos->s3cqos7); + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos7); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos7); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos7); writel(0x00002032, &s3c_qos->s3cqos8); s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; writel(0x00890089, &s3c_qos->s3cqos0); writel(0x20960010, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); - writel(0x20AA2200, &s3c_qos->s3cqos3); + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos3); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos3); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos3); writel(0x00002032, &s3c_qos->s3cqos4); writel(0x20960010, &s3c_qos->s3cqos5); writel(0x20302030, &s3c_qos->s3cqos6); - writel(0x20AA2200, &s3c_qos->s3cqos7); + if (is_qos_pri_media()) + writel(0x20AA2300, &s3c_qos->s3cqos7); + else if (is_qos_pri_normal()) + writel(0x20AA2200, &s3c_qos->s3cqos7); + else if (is_qos_pri_gfx()) + writel(0x20AA2100, &s3c_qos->s3cqos7); writel(0x00002032, &s3c_qos->s3cqos8); s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; @@ -1188,7 +1233,7 @@ static void qos_init_es2(void) writel(0x00002032, &s3c_qos->s3cqos8); s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; - writel(0x00820082, &s3c_qos->s3cqos0); + writel(0x00828092, &s3c_qos->s3cqos0); writel(0x20960020, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); writel(0x20AA20FA, &s3c_qos->s3cqos3); @@ -1198,7 +1243,7 @@ static void qos_init_es2(void) writel(0x20AA20FA, &s3c_qos->s3cqos7); writel(0x00002032, &s3c_qos->s3cqos8); - writel(0x00200808, &s3c->s3carcr11); + writel(0x00310808, &s3c->s3carcr11); /* DBSC -QoS */ /* DBSC0 - Read */ @@ -1235,7 +1280,7 @@ static void qos_init_es2(void) /* Transaction Control (MXI) */ mxi = (struct rcar_mxi *)MXI_BASE; writel(0x00000013, &mxi->mxrtcr); - writel(0x00000013, &mxi->mxwtcr); + writel(0x00000016, &mxi->mxwtcr); writel(0x00B800C0, &mxi->mxsaar0); writel(0x02000800, &mxi->mxsaar1); @@ -1622,7 +1667,7 @@ static void qos_init_es2(void) /* QoS Register (RT-AXI) */ axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; - writel(0x00000000, &axi_qos->qosconf); + writel(0x00000001, &axi_qos->qosconf); writel(0x00002053, &axi_qos->qosctset0); writel(0x00002096, &axi_qos->qosctset1); writel(0x00002030, &axi_qos->qosctset2); diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index a5ffc67..e744d4a 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -35,8 +35,11 @@ config MACH_SUN5I config MACH_SUN6I bool "sun6i (Allwinner A31)" select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT select SUNXI_GEN_SUN6I select SUPPORT_SPL + select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT config MACH_SUN7I bool "sun7i (Allwinner A20)" @@ -50,14 +53,25 @@ config MACH_SUN7I config MACH_SUN8I_A23 bool "sun8i (Allwinner A23)" select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT select SUNXI_GEN_SUN6I select SUPPORT_SPL + select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT config MACH_SUN8I_A33 bool "sun8i (Allwinner A33)" select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT select SUNXI_GEN_SUN6I select SUPPORT_SPL + select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT + +config MACH_SUN9I + bool "sun9i (Allwinner A80)" + select CPU_V7 + select SUNXI_GEN_SUN6I endchoice @@ -187,6 +201,7 @@ config SYS_CONFIG_NAME default "sun6i" if MACH_SUN6I default "sun7i" if MACH_SUN7I default "sun8i" if MACH_SUN8I + default "sun9i" if MACH_SUN9I config SYS_BOARD default "sunxi" @@ -194,24 +209,8 @@ config SYS_BOARD config SYS_SOC default "sunxi" -config SPL_FEL - bool "SPL/FEL mode support" - depends on SPL - default n - help - This enables support for Fast Early Loader (FEL) mode. This - allows U-Boot to be loaded to the board over USB by the on-chip - boot rom. U-Boot should be sent in two parts: SPL first, with - 'fel write 0x2000 u-boot-spl.bin; fel exe 0x2000' then U-Boot with - 'fel write 0x4a000000 u-boot.bin; fel exe 0x4a000000'. This option - shrinks the amount of SRAM available to SPL, so only enable it if - you need FEL. Note that enabling this option only allows FEL to be - used; it is still possible to boot U-Boot from boot media. U-Boot - SPL detects when it is being loaded using FEL. - config UART0_PORT_F bool "UART0 on MicroSD breakout board" - depends on SPL_FEL default n ---help--- Repurpose the SD card slot for getting access to the UART0 serial @@ -281,6 +280,18 @@ config MMC_SUNXI_SLOT_EXTRA slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable support for this. +config SPL_NAND_SUPPORT + bool "SPL/NAND mode support" + depends on SPL + default n + ---help--- + This enables support for booting from NAND internal + memory. U-Boot SPL doesn't detect where is it load from, + therefore this option is needed to properly load image from + flash. Option also disables MMC functionality on U-Boot due to + initialization errors encountered, when both controllers are + enabled. + config USB0_VBUS_PIN string "Vbus enable pin for usb0 (otg)" default "" diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index a650554..22d560a 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -40,6 +40,8 @@ F: include/configs/sun8i.h F: configs/ga10h_v1_1_defconfig F: configs/Ippo_q8h_v1_2_defconfig F: configs/Ippo_q8h_v1_2_a33_1024x600_defconfig +F: include/configs/sun9i.h +F: configs/Merrii_A80_Optimus_defconfig A20-OLINUXINO-LIME BOARD M: FUKAUMI Naoki <naobsd@gmail.com> diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 5f79cc1..f27967b 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -22,6 +22,9 @@ #ifdef CONFIG_AXP221_POWER #include <axp221.h> #endif +#ifdef CONFIG_NAND_SUNXI +#include <nand.h> +#endif #include <asm/arch/clock.h> #include <asm/arch/cpu.h> #include <asm/arch/display.h> @@ -315,6 +318,21 @@ int board_mmc_init(bd_t *bis) } #endif +#ifdef CONFIG_NAND +void board_nand_init(void) +{ + unsigned int pin; + static u8 ports[] = CONFIG_NAND_SUNXI_GPC_PORTS; + + /* Configure AHB muxes to connect output pins with NAND controller */ + for (pin = 0; pin < 16; pin++) + sunxi_gpio_set_cfgpin(SUNXI_GPC(pin), SUNXI_GPC_NAND); + + for (pin = 0; pin < ARRAY_SIZE(ports); pin++) + sunxi_gpio_set_cfgpin(SUNXI_GPC(ports[pin]), SUNXI_GPC_NAND); +} +#endif + void i2c_init_board(void) { #ifdef CONFIG_I2C0_ENABLE @@ -530,10 +548,11 @@ int misc_init_r(void) } } +#ifndef CONFIG_MACH_SUN9I ret = sunxi_usb_phy_probe(); if (ret) return ret; - +#endif #if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET) musb_register(&musb_plat, NULL, (void *)SUNXI_USB0_BASE); #endif |