diff options
Diffstat (limited to 'board')
38 files changed, 2935 insertions, 349 deletions
diff --git a/board/MigoR/Makefile b/board/MigoR/Makefile new file mode 100644 index 0000000..5a9d651 --- /dev/null +++ b/board/MigoR/Makefile @@ -0,0 +1,48 @@ +# +# Copyright (C) 2007 +# Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +# +# Copyright (C) 2007 +# Kenati Technologies, Inc. +# +# board/MigoR/Makefile +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := migo_r.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/MigoR/config.mk b/board/MigoR/config.mk new file mode 100644 index 0000000..c68cb72 --- /dev/null +++ b/board/MigoR/config.mk @@ -0,0 +1,32 @@ +# +# Copyright (C) 2007 +# Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +# +# Copyright (C) 2007 +# Kenati Technologies, Inc. +# +# board/MigoR/config.mk +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +# +# TEXT_BASE refers to image _after_ relocation. +# +# NOTE: Must match value used in u-boot.lds (in this directory). +# + +TEXT_BASE = 0x8FFC0000 + diff --git a/board/MigoR/lowlevel_init.S b/board/MigoR/lowlevel_init.S new file mode 100644 index 0000000..7fd771d --- /dev/null +++ b/board/MigoR/lowlevel_init.S @@ -0,0 +1,269 @@ +/* + * Copyright (C) 2007 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * Copyright (C) 2007 + * Kenati Technologies, Inc. + * + * board/MigoR/lowlevel_init.S + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> + +#include <asm/processor.h> + +/* + * Board specific low level init code, called _very_ early in the + * startup sequence. Relocation to SDRAM has not happened yet, no + * stack is available, bss section has not been initialised, etc. + * + * (Note: As no stack is available, no subroutines can be called...). + */ + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + + mov.l CCR_A, r1 ! Address of Cache Control Register + mov.l CCR_D, r0 ! Instruction Cache Invalidate + mov.l r0, @r1 + + mov.l MMUCR_A, r1 ! Address of MMU Control Register + mov.l MMUCR_D, r0 ! TI == TLB Invalidate bit + mov.l r0, @r1 + + mov.l MSTPCR0_A, r1 ! Address of Power Control Register 0 + mov.l MSTPCR0_D, r0 ! + mov.l r0, @r1 + + mov.l MSTPCR2_A, r1 ! Address of Power Control Register 2 + mov.l MSTPCR2_D, r0 ! + mov.l r0, @r1 + + mov.l PFC_PULCR_A, r1 + mov.w PFC_PULCR_D, r0 + mov.w r0,@r1 + + mov.l PFC_DRVCR_A, r1 + mov.w PFC_DRVCR_D, r0 + mov.w r0, @r1 + + mov.l SBSCR_A, r1 ! + mov.w SBSCR_D, r0 ! + mov.w r0, @r1 + + mov.l PSCR_A, r1 ! + mov.w PSCR_D, r0 ! + mov.w r0, @r1 + + mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register) + mov.w RWTCSR_D_1, r0 ! 0xA507 -> timer_STOP/WDT_CLK=max + mov.w r0, @r1 + + mov.l RWTCNT_A, r1 ! 0xA4520000 (Watchdog Count Register) + mov.w RWTCNT_D, r0 ! 0x5A00 -> Clear + mov.w r0, @r1 + + mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register) + mov.w RWTCSR_D_2, r0 ! 0xA504 -> timer_STOP/CLK=500ms + mov.w r0, @r1 + + mov.l DLLFRQ_A, r1 ! 20080115 + mov.l DLLFRQ_D, r0 ! 20080115 + mov.l r0, @r1 + + mov.l FRQCR_A, r1 ! 0xA4150000 Frequency control register + mov.l FRQCR_D, r0 ! 20080115 + mov.l r0, @r1 + + mov.l CCR_A, r1 ! Address of Cache Control Register + mov.l CCR_D_2, r0 ! ?? + mov.l r0, @r1 + +bsc_init: + + mov.l CMNCR_A, r1 ! CMNCR address -> R1 + mov.l CMNCR_D, r0 ! CMNCR data -> R0 + mov.l r0, @r1 ! CMNCR set + + mov.l CS0BCR_A, r1 ! CS0BCR address -> R1 + mov.l CS0BCR_D, r0 ! CS0BCR data -> R0 + mov.l r0, @r1 ! CS0BCR set + + mov.l CS4BCR_A, r1 ! CS4BCR address -> R1 + mov.l CS4BCR_D, r0 ! CS4BCR data -> R0 + mov.l r0, @r1 ! CS4BCR set + + mov.l CS5ABCR_A, r1 ! CS5ABCR address -> R1 + mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0 + mov.l r0, @r1 ! CS5ABCR set + + mov.l CS5BBCR_A, r1 ! CS5BBCR address -> R1 + mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0 + mov.l r0, @r1 ! CS5BBCR set + + mov.l CS6ABCR_A, r1 ! CS6ABCR address -> R1 + mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0 + mov.l r0, @r1 ! CS6ABCR set + + mov.l CS0WCR_A, r1 ! CS0WCR address -> R1 + mov.l CS0WCR_D, r0 ! CS0WCR data -> R0 + mov.l r0, @r1 ! CS0WCR set + + mov.l CS4WCR_A, r1 ! CS4WCR address -> R1 + mov.l CS4WCR_D, r0 ! CS4WCR data -> R0 + mov.l r0, @r1 ! CS4WCR set + + mov.l CS5AWCR_A, r1 ! CS5AWCR address -> R1 + mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0 + mov.l r0, @r1 ! CS5AWCR set + + mov.l CS5BWCR_A, r1 ! CS5BWCR address -> R1 + mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0 + mov.l r0, @r1 ! CS5BWCR set + + mov.l CS6AWCR_A, r1 ! CS6AWCR address -> R1 + mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0 + mov.l r0, @r1 ! CS6AWCR set + + ! SDRAM initialization + mov.l SDCR_A, r1 ! SB_SDCR address -> R1 + mov.l SDCR_D, r0 ! SB_SDCR data -> R0 + mov.l r0, @r1 ! SB_SDCR set + + mov.l SDWCR_A, r1 ! SB_SDWCR address -> R1 + mov.l SDWCR_D, r0 ! SB_SDWCR data -> R0 + mov.l r0, @r1 ! SB_SDWCR set + + mov.l SDPCR_A, r1 ! SB_SDPCR address -> R1 + mov.l SDPCR_D, r0 ! SB_SDPCR data -> R0 + mov.l r0, @r1 ! SB_SDPCR set + + mov.l RTCOR_A, r1 ! SB_RTCOR address -> R1 + mov.l RTCOR_D, r0 ! SB_RTCOR data -> R0 + mov.l r0, @r1 ! SB_RTCOR set + + mov.l RTCNT_A, r1 ! SB_RTCNT address -> R1 + mov.l RTCNT_D, r0 ! SB_RTCNT data -> R0 + mov.l r0, @r1 + + mov.l RTCSR_A, r1 ! SB_RTCSR address -> R1 + mov.l RTCSR_D, r0 ! SB_RTCSR data -> R0 + mov.l r0, @r1 ! SB_RTCSR set + + mov.l RFCR_A, r1 ! SB_RFCR address -> R1 + mov.l RFCR_D, r0 ! SB_RFCR data -> R0 + mov.l r0, @r1 + + mov.l SDMR3_A, r1 ! SDMR3 address -> R1 + mov #0x00, r0 ! SDMR3 data -> R0 + mov.b r0, @r1 ! SDMR3 set + + ! BL bit off (init = ON) (?!?) + + stc sr, r0 ! BL bit off(init=ON) + mov.l SR_MASK_D, r1 + and r1, r0 + ldc r0, sr + + rts + mov #0, r0 + + + + .align 4 + +CCR_A: .long CCR +MMUCR_A: .long MMUCR +MSTPCR0_A: .long MSTPCR0 +MSTPCR2_A: .long MSTPCR2 +PFC_PULCR_A: .long PULCR +PFC_DRVCR_A: .long DRVCR +SBSCR_A: .long SBSCR +PSCR_A: .long PSCR +RWTCSR_A: .long RWTCSR +RWTCNT_A: .long RWTCNT +FRQCR_A: .long FRQCR +PLLCR_A: .long PLLCR +DLLFRQ_A: .long DLLFRQ + +CCR_D: .long 0x00000800 +CCR_D_2: .long 0x00000103 +MMUCR_D: .long 0x00000004 +MSTPCR0_D: .long 0x00001001 +MSTPCR2_D: .long 0xffffffff +PFC_PULCR_D: .long 0x6000 +PFC_DRVCR_D: .long 0x0464 +FRQCR_D: .long 0x07033639 +PLLCR_D: .long 0x00005000 +DLLFRQ_D: .long 0x000004F6 ! 20080115 + +CMNCR_A: .long CMNCR +CMNCR_D: .long 0x0000001B ! 20080115 +CS0BCR_A: .long CS0BCR ! Flash bank 1 +CS0BCR_D: .long 0x24920400 +CS4BCR_A: .long CS4BCR ! +CS4BCR_D: .long 0x10003400 ! 20080115 +CS5ABCR_A: .long CS5ABCR ! +CS5ABCR_D: .long 0x24920400 +CS5BBCR_A: .long CS5BBCR ! +CS5BBCR_D: .long 0x24920400 +CS6ABCR_A: .long CS6ABCR ! +CS6ABCR_D: .long 0x24920400 + +CS0WCR_A: .long CS0WCR +CS0WCR_D: .long 0x00000380 +CS4WCR_A: .long CS4WCR +CS4WCR_D: .long 0x00100A81 ! 20080115 +CS5AWCR_A: .long CS5AWCR +CS5AWCR_D: .long 0x00000300 +CS5BWCR_A: .long CS5BWCR +CS5BWCR_D: .long 0x00000300 +CS6AWCR_A: .long CS6AWCR +CS6AWCR_D: .long 0x00000300 + +SDCR_A: .long SBSC_SDCR +SDCR_D: .long 0x80160809 ! 20080115 +SDWCR_A: .long SBSC_SDWCR +SDWCR_D: .long 0x0014450C ! 20080115 +SDPCR_A: .long SBSC_SDPCR +SDPCR_D: .long 0x00000087 +RTCOR_A: .long SBSC_RTCOR +RTCNT_A: .long SBSC_RTCNT +RTCNT_D: .long 0xA55A0012 +RTCOR_D: .long 0xA55A001C ! 20080115 +RTCSR_A: .long SBSC_RTCSR +RFCR_A: .long SBSC_RFCR +RFCR_D: .long 0xA55A0221 +RTCSR_D: .long 0xA55A009a ! 20080115 +SDMR3_A: .long 0xFE581180 ! 20080115 + +SR_MASK_D: .long 0xEFFFFF0F + + .align 2 + +SBSCR_D: .word 0x0044 +PSCR_D: .word 0x0000 +RWTCSR_D_1: .word 0xA507 +RWTCSR_D_2: .word 0xA504 ! 20080115 +RWTCNT_D: .word 0x5A00 + diff --git a/board/MigoR/migo_r.c b/board/MigoR/migo_r.c new file mode 100644 index 0000000..53f4bb2 --- /dev/null +++ b/board/MigoR/migo_r.c @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2007 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * Copyright (C) 2007 + * Kenati Technologies, Inc. + * + * board/MigoR/migo_r.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/processor.h> + +int checkboard(void) +{ + puts("BOARD: Renesas MigoR\n"); + return 0; +} + +int board_init(void) +{ + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_memstart = CFG_SDRAM_BASE; + gd->bd->bi_memsize = CFG_SDRAM_SIZE; + printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + +void led_set_state (unsigned short value) +{ +} + diff --git a/board/MigoR/u-boot.lds b/board/MigoR/u-boot.lds new file mode 100644 index 0000000..1877b81 --- /dev/null +++ b/board/MigoR/u-boot.lds @@ -0,0 +1,106 @@ +/* + * Copyrigth (c) 2007 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + Base address of internal SDRAM is 0x0C000000. + Although size of SDRAM can be either 16 or 32 MBytes, + we assume 16 MBytes (ie ignore upper half if the full + 32 MBytes is present). + + NOTE: This address must match with the definition of + TEXT_BASE in config.mk (in this directory). + + */ + . = 0x8C000000 + (64*1024*1024) - (256*1024); + + PROVIDE (reloc_dst = .); + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + cpu/sh4/start.o (.text) + . = ALIGN(8192); + common/environment.o (.ppcenv) + . = ALIGN(8192); + common/environment.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(.rodata) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + PROVIDE (__u_boot_cmd_start = .); + .u_boot_cmd : + { + *(.u_boot_cmd) + . = ALIGN(4); + } + PROVIDE (__u_boot_cmd_end = .); + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (_end = .); +} + diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index 36779f5..9986e9a 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -32,13 +32,20 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ DECLARE_GLOBAL_DATA_PTR; +#define CFG_BCSR3_PCIE 0x10 + +#define BOARD_CANYONLANDS_PCIE 1 +#define BOARD_CANYONLANDS_SATA 2 +#define BOARD_GLACIER 3 + int board_early_init_f(void) { u32 sdr0_cust0; + u32 pvr = get_pvr(); - /*------------------------------------------------------------------+ + /* * Setup the interrupt controller polarities, triggers, etc. - *------------------------------------------------------------------*/ + */ mtdcr(uic0sr, 0xffffffff); /* clear all */ mtdcr(uic0er, 0x00000000); /* disable all */ mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ @@ -105,27 +112,69 @@ int board_early_init_f(void) mtdcr(AHB_TOP, 0x8000004B); mtdcr(AHB_BOT, 0x8000004B); - /* - * Configure USB-STP pins as alternate and not GPIO - * It seems to be neccessary to configure the STP pins as GPIO - * input at powerup (perhaps while USB reset is asserted). So - * we configure those pins to their "real" function now. - */ - gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); - gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); + if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) { + /* + * Configure USB-STP pins as alternate and not GPIO + * It seems to be neccessary to configure the STP pins as GPIO + * input at powerup (perhaps while USB reset is asserted). So + * we configure those pins to their "real" function now. + */ + gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); + gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); + } return 0; } -int checkboard (void) +static void canyonlands_sata_init(int board_type) +{ + u32 reg; + + if (board_type == BOARD_CANYONLANDS_SATA) { + /* Put SATA in reset */ + SDR_WRITE(SDR0_SRST1, 0x00020001); + + /* Set the phy for SATA, not PCI-E port 0 */ + reg = SDR_READ(PESDR0_PHY_CTL_RST); + SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001); + reg = SDR_READ(PESDR0_L0CLK); + SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007); + SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111); + SDR_WRITE(PESDR0_L0DRV, 0x00000104); + + /* Bring SATA out of reset */ + SDR_WRITE(SDR0_SRST1, 0x00000000); + } +} + +int checkboard(void) { char *s = getenv("serial#"); u32 pvr = get_pvr(); - if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA)) + if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA)) { printf("Board: Glacier - AMCC PPC460GT Evaluation Board"); - else + gd->board_type = BOARD_GLACIER; + } else { printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board"); + if (in_8((void *)(CFG_BCSR_BASE + 3)) & CFG_BCSR3_PCIE) + gd->board_type = BOARD_CANYONLANDS_PCIE; + else + gd->board_type = BOARD_CANYONLANDS_SATA; + } + + switch (gd->board_type) { + case BOARD_CANYONLANDS_PCIE: + case BOARD_GLACIER: + puts(", 2*PCIe"); + break; + + case BOARD_CANYONLANDS_SATA: + puts(", 1*PCIe/1*SATA"); + break; + } + + printf(", Rev. %X", in_8((void *)(CFG_BCSR_BASE + 0))); if (s != NULL) { puts(", serial# "); @@ -133,6 +182,8 @@ int checkboard (void) } putc('\n'); + canyonlands_sata_init(gd->board_type); + return (0); } @@ -198,37 +249,36 @@ int testdram(void) } #endif -/************************************************************************* +/* * pci_target_init * * The bootstrap configuration provides default settings for the pci * inbound map (PIM). But the bootstrap config choices are limited and * may not be sufficient for a given board. - * - ************************************************************************/ + */ #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { - /*-------------------------------------------------------------------+ + /* * Disable everything - *-------------------------------------------------------------------*/ + */ out_le32((void *)PCIX0_PIM0SA, 0); /* disable */ out_le32((void *)PCIX0_PIM1SA, 0); /* disable */ out_le32((void *)PCIX0_PIM2SA, 0); /* disable */ out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */ - /*-------------------------------------------------------------------+ + /* * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 * strapping options to not support sizes such as 128/256 MB. - *-------------------------------------------------------------------*/ + */ out_le32((void *)PCIX0_PIM0LAL, CFG_SDRAM_BASE); out_le32((void *)PCIX0_PIM0LAH, 0); out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1); out_le32((void *)PCIX0_BAR0, 0); - /*-------------------------------------------------------------------+ + /* * Program the board's subsystem id/vendor id - *-------------------------------------------------------------------*/ + */ out_le16((void *)PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID); out_le16((void *)PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID); @@ -265,13 +315,24 @@ void pcie_setup_hoses(int busno) int ret = 0; char *env; unsigned int delay; + int start; /* * assume we're called after the PCIX hose is initialized, which takes * bus ID 0 and therefore start numbering PCIe's from 1. */ bus = busno; - for (i = 0; i <= 1; i++) { + + /* + * Canyonlands with SATA enabled has only one PCIe slot + * (2nd one). + */ + if (gd->board_type == BOARD_CANYONLANDS_SATA) + start = 1; + else + start = 0; + + for (i = start; i <= 1; i++) { if (is_end_point(i)) ret = ppc4xx_init_pcie_endport(i); @@ -369,6 +430,7 @@ int misc_init_r(void) { u32 sdr0_srst1 = 0; u32 eth_cfg; + u32 pvr = get_pvr(); /* * Set EMAC mode/configuration (GMII, SGMII, RGMII...). @@ -382,7 +444,10 @@ int misc_init_r(void) /* Set the for 2 RGMII mode */ /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL; - eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL; + if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) + eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL; + else + eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL; mtsdr(SDR0_ETH_CFG, eth_cfg); /* @@ -407,7 +472,7 @@ void ft_board_setup(void *blob, bd_t *bd) /* Fixup NOR mapping */ val[0] = 0; /* chip select number */ val[1] = 0; /* always 0 */ - val[2] = gd->bd->bi_flashstart; + val[2] = CFG_FLASH_BASE_PHYS_L; /* we fixed up this address */ val[3] = gd->bd->bi_flashsize; rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", val, sizeof(val), 1); diff --git a/board/amcc/canyonlands/u-boot.lds b/board/amcc/canyonlands/u-boot.lds index 7496f48..3df6ad4 100644 --- a/board/amcc/canyonlands/u-boot.lds +++ b/board/amcc/canyonlands/u-boot.lds @@ -139,8 +139,6 @@ SECTIONS *(COMMON) } - ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); - _end = . ; PROVIDE (end = .); } diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c index ceb128c..3dbb2e1 100644 --- a/board/esd/du440/du440.c +++ b/board/esd/du440/du440.c @@ -67,12 +67,12 @@ int board_early_init_f(void) out_be32((void*)GPIO1_OR, 0x00000000); out_be32((void*)GPIO1_TCR, 0xc2000000 | CFG_GPIO1_IORSTN | + CFG_GPIO1_IORST2N | CFG_GPIO1_LEDUSR1 | CFG_GPIO1_LEDUSR2 | CFG_GPIO1_LEDPOST | CFG_GPIO1_LEDDU); out_be32((void*)GPIO1_ODR, CFG_GPIO1_LEDDU); - out_be32((void*)GPIO1_OSRL, 0x5c280000); out_be32((void*)GPIO1_OSRH, 0x00000000); out_be32((void*)GPIO1_TSRL, 0x0c000000); @@ -243,7 +243,8 @@ int misc_init_r(void) * release IO-RST# * We have to wait at least 560ms until we may call usbhub_init */ - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CFG_GPIO1_IORSTN); + out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | + CFG_GPIO1_IORSTN | CFG_GPIO1_IORST2N); /* * flash USR1/2 LEDs (600ms) diff --git a/board/esd/du440/du440.h b/board/esd/du440/du440.h index 5c362e4..83fdac7 100644 --- a/board/esd/du440/du440.h +++ b/board/esd/du440/du440.h @@ -24,6 +24,7 @@ #define CFG_GPIO1_DCF77 (0x80000000 >> (42-32)) /* GPIO1_42 */ #define CFG_GPIO1_IORSTN (0x80000000 >> (55-32)) /* GPIO1_55 */ +#define CFG_GPIO1_IORST2N (0x80000000 >> (47-32)) /* GPIO1_47 */ #define CFG_GPIO1_HWVER_MASK 0x000000f0 /* GPIO1_56-59 */ #define CFG_GPIO1_HWVER_SHIFT 4 diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c index 350af48..90d9309 100644 --- a/board/esd/pmc440/cmd_pmc440.c +++ b/board/esd/pmc440/cmd_pmc440.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Matthias Fuchs, esd Gmbh, matthias.fuchs@esd-electronics.com. * * See file CREDITS for list of people who contributed to this @@ -21,7 +21,6 @@ * MA 02111-1307 USA * */ - #include <common.h> #include <command.h> #include <asm/io.h> @@ -31,7 +30,8 @@ #include "pmc440.h" int is_monarch(void); -int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt); +int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, + uchar *buffer, unsigned cnt); int eeprom_write_enable(unsigned dev_addr, int state); DECLARE_GLOBAL_DATA_PTR; @@ -64,7 +64,6 @@ int fpga_interrupt(u32 arg) return rc; } - int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; @@ -100,7 +99,6 @@ U_BOOT_CMD( NULL ); - void dump_fifo(pmc440_fpga_t *fpga, int f, int *n) { u32 ctrl; @@ -117,7 +115,6 @@ void dump_fifo(pmc440_fpga_t *fpga, int f, int *n) } } - int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; @@ -200,7 +197,8 @@ int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) got_fifoirq = 0; /* unmask global fifo irq */ FPGA_OUT32(&fpga->hostctrl, - HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG); + HOSTCTRL_FIFOIE_GATE | + HOSTCTRL_FIFOIE_FLAG); } } @@ -237,7 +235,8 @@ int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) for (i=0; i<n; i++) FPGA_OUT32(&fpga->fifo[f].data, data); } else { - printf("writing %d x %08x to fifo port at address %08x\n", + printf("writing %d x %08x to fifo port at " + "address %08x\n", n, data, f); for (i=0; i<n; i++) out32(f, data); @@ -263,10 +262,10 @@ U_BOOT_CMD( " - without arguments: print all fifo's status\n" " - with 'wait' argument: interrupt driven read from all fifos\n" " - with 'read' argument: read current contents from all fifos\n" - " - with 'write' argument: write 'data' 'cnt' times to 'fifo' or 'address'\n" + " - with 'write' argument: write 'data' 'cnt' times to " + "'fifo' or 'address'\n" ); - int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { ulong sdsdp[5]; @@ -301,10 +300,12 @@ int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] sdsdp[2]=0x40082350; sdsdp[3]=0x0d050000; } else if (!strcmp(argv[1], "test")) { - /* TODO: this will replace the 667 MHz config above. + /* + * TODO: this will replace the 667 MHz config above. * But it needs some more testing on a real 667 MHz CPU. */ - printf("Bootstrapping for test (667MHz PLB=133PLB PLB/PCI=3)\n"); + printf("Bootstrapping for test" + " (667MHz PLB=133PLB PLB/PCI=3)\n"); sdsdp[0]=0x8778a256; sdsdp[1]=0x095fa030; sdsdp[2]=0x40082350; @@ -347,7 +348,6 @@ U_BOOT_CMD( "<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]" ); - #if defined(CONFIG_PRAM) #include <environment.h> extern env_t *env_ptr; @@ -394,7 +394,6 @@ U_BOOT_CMD( ); #endif /* CONFIG_PRAM */ - int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { if (argc > 1) { @@ -423,7 +422,6 @@ U_BOOT_CMD( NULL ); - int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; @@ -444,7 +442,8 @@ int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* deassert */ printf("PMC-RESETOUT# deasserted\n"); FPGA_OUT32(&fpga->hostctrl, - HOSTCTRL_PMCRSTOUT_GATE | HOSTCTRL_PMCRSTOUT_FLAG); + HOSTCTRL_PMCRSTOUT_GATE | + HOSTCTRL_PMCRSTOUT_FLAG); } } else { printf("PMC-RESETOUT# is %s\n", @@ -460,7 +459,6 @@ U_BOOT_CMD( NULL ); - int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { if (is_monarch()) { @@ -481,7 +479,9 @@ int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) in_be32((void*)GPIO1_TCR) & ~GPIO1_INTA_FAKE); } } else { - printf("inta# is %s\n", in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ? "active" : "inactive"); + printf("inta# is %s\n", + in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ? + "active" : "inactive"); } return 0; } @@ -491,7 +491,6 @@ U_BOOT_CMD( NULL ); - /* test-only */ int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { @@ -503,11 +502,17 @@ int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) pciaddr &= 0xf0000000; /* map PCI address at 0xc0000000 in PLB space */ - out32r(PCIX0_PMM1MA, 0x00000000); /* PMM1 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM1LA, 0xc0000000); /* PMM1 Local Address */ - out32r(PCIX0_PMM1PCILA, pciaddr); /* PMM1 PCI Low Address */ - out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM1 PCI High Address */ - out32r(PCIX0_PMM1MA, 0xf0000001); /* 256MB + No prefetching, and enable region */ + + /* PMM1 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM1MA, 0x00000000); + /* PMM1 Local Address */ + out32r(PCIX0_PMM1LA, 0xc0000000); + /* PMM1 PCI Low Address */ + out32r(PCIX0_PMM1PCILA, pciaddr); + /* PMM1 PCI High Address */ + out32r(PCIX0_PMM1PCIHA, 0x00000000); + /* 256MB + No prefetching, and enable region */ + out32r(PCIX0_PMM1MA, 0xf0000001); } else { printf("Usage:\npmm %s\n", cmdtp->help); } diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index edf3a14..5b811bb 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com. * Based on board/amcc/sequoia/sequoia.c * @@ -32,6 +32,7 @@ #include <ppc440.h> #include <asm/processor.h> #include <asm/io.h> +#include <asm/bitops.h> #include <command.h> #include <i2c.h> #ifdef CONFIG_RESET_PHY_R @@ -43,12 +44,12 @@ DECLARE_GLOBAL_DATA_PTR; -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ ulong flash_get_size(ulong base, int banknum); int pci_is_66mhz(void); -int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt); - +int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset, + uchar *buffer, unsigned cnt); struct serial_device *default_serial_console(void) { @@ -70,7 +71,8 @@ struct serial_device *default_serial_console(void) /* mark scratchreg valid */ scratchreg = (scratchreg & 0xffffff00) | 0x80; - i = bootstrap_eeprom_read(CFG_I2C_BOOT_EEPROM_ADDR, 0x10, buf, 4); + i = bootstrap_eeprom_read(CFG_I2C_BOOT_EEPROM_ADDR, + 0x10, buf, 4); if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) { scratchreg |= buf[2]; @@ -99,10 +101,10 @@ int board_early_init_f(void) mtdcr(ebccfga, xbcfg); mtdcr(ebccfgd, 0xf8400000); - /*-------------------------------------------------------------------- + /* * Setup the GPIO pins * TODO: setup GPIOs via CFG_4xx_GPIO_TABLE in board's config file - *-------------------------------------------------------------------*/ + */ out32(GPIO0_OR, 0x40000002); out32(GPIO0_TCR, 0x4c90011f); out32(GPIO0_OSRL, 0x28011400); @@ -141,9 +143,9 @@ int board_early_init_f(void) mtspr(dbcr0, 0x20000000); /* do chip reset */ } - /*-------------------------------------------------------------------- + /* * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ + */ mtdcr(uic0sr, 0xffffffff); /* clear all */ mtdcr(uic0er, 0x00000000); /* disable all */ mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ @@ -170,9 +172,11 @@ int board_early_init_f(void) /* select Ethernet pins */ mfsdr(SDR0_PFC1, sdr0_pfc1); - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4; + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | + SDR0_PFC1_SELECT_CONFIG_4; mfsdr(SDR0_PFC2, sdr0_pfc2); - sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4; + sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | + SDR0_PFC2_SELECT_CONFIG_4; /* enable 2nd IIC */ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL; @@ -192,9 +196,9 @@ int board_early_init_f(void) return 0; } -/*---------------------------------------------------------------------------+ - | misc_init_r. - +---------------------------------------------------------------------------*/ +/* + * misc_init_r. + */ int misc_init_r(void) { uint pbcr; @@ -221,32 +225,7 @@ int misc_init_r(void) mtdcr(ebccfga, pb0cr); #endif pbcr = mfdcr(ebccfgd); - switch (gd->bd->bi_flashsize) { - case 1 << 20: - size_val = 0; - break; - case 2 << 20: - size_val = 1; - break; - case 4 << 20: - size_val = 2; - break; - case 8 << 20: - size_val = 3; - break; - case 16 << 20: - size_val = 4; - break; - case 32 << 20: - size_val = 5; - break; - case 64 << 20: - size_val = 6; - break; - case 128 << 20: - size_val = 7; - break; - } + size_val = ffs(gd->bd->bi_flashsize) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) mtdcr(ebccfga, pb2cr); @@ -286,20 +265,22 @@ int misc_init_r(void) mfsdr(SDR0_USB2H0CR, usb2h0cr); usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; - /* An 8-bit/60MHz interface is the only possible alternative - when connecting the Device to the PHY */ + /* + * An 8-bit/60MHz interface is the only possible alternative + * when connecting the Device to the PHY + */ usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ + usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; @@ -309,7 +290,7 @@ int misc_init_r(void) mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); mtsdr(SDR0_USB2H0CR, usb2h0cr); - /*clear resets*/ + /* clear resets */ udelay(1000); mtsdr(SDR0_SRST1, 0x00000000); udelay(1000); @@ -317,18 +298,18 @@ int misc_init_r(void) printf("USB: Host\n"); - } else if ((strcmp(act, "dev") == 0) || (in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) { - /*-------------------PATCH-------------------------------*/ + } else if ((strcmp(act, "dev") == 0) || + (in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) { mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); udelay (1000); @@ -344,7 +325,6 @@ int misc_init_r(void) udelay (1000); mtsdr(SDR0_SRST1, 0x60306000); - /*-------------------PATCH-------------------------------*/ /* SDR Setting */ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); @@ -353,23 +333,23 @@ int misc_init_r(void) mfsdr(SDR0_PFC1, sdr0_pfc1); usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0*/ + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/ + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0*/ + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0*/ + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0*/ + usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; - sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1*/ + sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; mtsdr(SDR0_USB2H0CR, usb2h0cr); mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); @@ -453,43 +433,42 @@ void pmc440_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) } #endif -/************************************************************************* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. +/* + * pci_pre_init * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. * - ************************************************************************/ + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + */ #if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller *hose) { unsigned long addr; - /*-------------------------------------------------------------------------+ - | Set priority for all PLB3 devices to 0. - | Set PLB3 arbiter to fair mode. - +-------------------------------------------------------------------------*/ + /* + * Set priority for all PLB3 devices to 0. + * Set PLB3 arbiter to fair mode. + */ mfsdr(sdr_amp1, addr); mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); addr = mfdcr(plb3_acr); mtdcr(plb3_acr, addr | 0x80000000); - /*-------------------------------------------------------------------------+ - | Set priority for all PLB4 devices to 0. - +-------------------------------------------------------------------------*/ + /* + * Set priority for all PLB4 devices to 0. + */ mfsdr(sdr_amp0, addr); mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ mtdcr(plb4_acr, addr); - /*-------------------------------------------------------------------------+ - | Set Nebula PLB4 arbiter to fair mode. - +-------------------------------------------------------------------------*/ + /* + * Set Nebula PLB4 arbiter to fair mode. + */ /* Segment0 */ addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; @@ -512,64 +491,84 @@ int pci_pre_init(struct pci_controller *hose) } #endif /* defined(CONFIG_PCI) */ -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. +/* + * pci_target_init * - ************************************************************************/ + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + */ #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { - /*--------------------------------------------------------------------------+ + char *ptmla_str, *ptmms_str; + + /* * Set up Direct MMIO registers - *--------------------------------------------------------------------------*/ - /*--------------------------------------------------------------------------+ - | PowerPC440EPX PCI Master configuration. - | Map one 1Gig range of PLB/processor addresses to PCI memory space. - | PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF - | Use byte reversed out routines to handle endianess. - | Make this region non-prefetchable. - +--------------------------------------------------------------------------*/ - out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + */ + /* + * PowerPC440EPX PCI Master configuration. + * Map one 1Gig range of PLB/processor addresses to PCI memory space. + * PLB address 0x80000000-0xBFFFFFFF + * ==> PCI address 0x80000000-0xBFFFFFFF + * Use byte reversed out routines to handle endianess. + * Make this region non-prefetchable. + */ + out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ + /* - disabled b4 setting */ out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM0MA, 0xc0000001); /* 1G + No prefetching, and enable region */ + out32r(PCIX0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */ + /* and enable region */ if (!is_monarch()) { - /* BAR1: top 64MB of RAM */ - out32r(PCIX0_PTM1MS, 0xfc000001); /* Memory Size/Attribute */ - out32r(PCIX0_PTM1LA, 0x0c000000); /* Local Addr. Reg */ + ptmla_str = getenv("ptm1la"); + ptmms_str = getenv("ptm1ms"); + if(NULL != ptmla_str && NULL != ptmms_str ) { + out32r(PCIX0_PTM1MS, + simple_strtoul(ptmms_str, NULL, 16)); + out32r(PCIX0_PTM1LA, + simple_strtoul(ptmla_str, NULL, 16)); + } else { + /* BAR1: default top 64MB of RAM */ + out32r(PCIX0_PTM1MS, 0xfc000001); + out32r(PCIX0_PTM1LA, 0x0c000000); + } } else { - /* BAR1: complete 256MB RAM (TODO: make dynamic) */ - out32r(PCIX0_PTM1MS, 0xf0000001); /* Memory Size/Attribute */ - out32r(PCIX0_PTM1LA, 0x00000000); /* Local Addr. Reg */ + /* BAR1: default: complete 256MB RAM */ + out32r(PCIX0_PTM1MS, 0xf0000001); + out32r(PCIX0_PTM1LA, 0x00000000); } - /* BAR2: 16 MB FPGA registers */ - out32r(PCIX0_PTM2MS, 0xff000001); /* Memory Size/Attribute */ - out32r(PCIX0_PTM2LA, 0xef000000); /* Local Addr. Reg */ + ptmla_str = getenv("ptm2la"); /* Local Addr. Reg */ + ptmms_str = getenv("ptm2ms"); /* Memory Size/Attribute */ + if(NULL != ptmla_str && NULL != ptmms_str ) { + out32r(PCIX0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16)); + out32r(PCIX0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16)); + } else { + /* BAR2: default: 16 MB FPGA + registers */ + out32r(PCIX0_PTM2MS, 0xff000001); /* Memory Size/Attribute */ + out32r(PCIX0_PTM2LA, 0xef000000); /* Local Addr. Reg */ + } if (is_monarch()) { /* BAR2: map FPGA registers behind system memory at 1GB */ pci_write_config_dword(0, PCI_BASE_ADDRESS_2, 0x40000008); } - /*--------------------------------------------------------------------------+ + /* * Set up Configuration registers - *--------------------------------------------------------------------------*/ + */ /* Program the board's vendor id */ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, CFG_PCI_SUBSYS_VENDORID); -#if 0 /* disabled for PMC405 backward compatibility */ + /* disabled for PMC405 backward compatibility */ /* Configure command register as bus master */ - pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); -#endif + /* pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); */ + /* 240nS PCI clock */ pci_write_config_word(0, PCI_LATENCY_TIMER, 1); @@ -587,8 +586,10 @@ void pci_target_init(struct pci_controller *hose) CFG_PCI_CLASSCODE_NONMONARCH); /* PCI configuration done: release ERREADY */ - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_PPC_EREADY); - out_be32((void*)GPIO1_TCR, in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY); + out_be32((void*)GPIO1_OR, + in_be32((void*)GPIO1_OR) | GPIO1_PPC_EREADY); + out_be32((void*)GPIO1_TCR, + in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY); } else { /* Program the board's subsystem id/classcode */ pci_write_config_word(0, PCI_SUBSYSTEM_ID, @@ -599,20 +600,19 @@ void pci_target_init(struct pci_controller *hose) } #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ -/************************************************************************* - * pci_master_init - * - ************************************************************************/ +/* + * pci_master_init + */ #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) void pci_master_init(struct pci_controller *hose) { unsigned short temp_short; - /*--------------------------------------------------------------------------+ - | Write the PowerPC440 EP PCI Configuration regs. - | Enable PowerPC440 EP to be a master on the PCI bus (PMM). - | Enable PowerPC440 EP to act as a PCI memory target (PTM). - +--------------------------------------------------------------------------*/ + /* + * Write the PowerPC440 EP PCI Configuration regs. + * Enable PowerPC440 EP to be a master on the PCI bus (PMM). + * Enable PowerPC440 EP to act as a PCI memory target (PTM). + */ if (is_monarch()) { pci_read_config_word(0, PCI_COMMAND, &temp_short); pci_write_config_word(0, PCI_COMMAND, @@ -622,7 +622,6 @@ void pci_master_init(struct pci_controller *hose) } #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ - static void wait_for_pci_ready(void) { int i; @@ -649,22 +648,19 @@ static void wait_for_pci_ready(void) } } - -/************************************************************************* - * is_pci_host - * - * This routine is called to determine if a pci scan should be - * performed. With various hardware environments (especially cPCI and - * PPMC) it's insufficient to depend on the state of the arbiter enable - * bit in the strap register, or generic host/adapter assumptions. - * - * Rather than hard-code a bad assumption in the general 440 code, the - * 440 pci code requires the board to decide at runtime. +/* + * is_pci_host * - * Return 0 for adapter mode, non-zero for host (monarch) mode. + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. * - ************************************************************************/ + * Return 0 for adapter mode, non-zero for host (monarch) mode. + */ #if defined(CONFIG_PCI) int is_pci_host(struct pci_controller *hose) { @@ -681,6 +677,7 @@ int is_pci_host(struct pci_controller *hose) return 0; } #endif /* defined(CONFIG_PCI) */ + #if defined(CONFIG_POST) /* * Returns 1 if keys pressed to start the power-on long-running tests @@ -692,7 +689,6 @@ int post_hotkeys_pressed(void) } #endif /* CONFIG_POST */ - #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { @@ -713,17 +709,19 @@ void reset_phy(void) #endif #if defined(CFG_EEPROM_WREN) -/* Input: <dev_addr> I2C address of EEPROM device to enable. - * <state> -1: deliver current state +/* + * Input: <dev_addr> I2C address of EEPROM device to enable. + * <state> -1: deliver current state * 0: disable write * 1: enable write - * Returns: -1: wrong device address - * 0: dis-/en- able done + * Returns: -1: wrong device address + * 0: dis-/en- able done * 0/1: current state if <state> was -1. */ int eeprom_write_enable(unsigned dev_addr, int state) { - if ((CFG_I2C_EEPROM_ADDR != dev_addr) && (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr)) { + if ((CFG_I2C_EEPROM_ADDR != dev_addr) && + (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr)) { return -1; } else { switch (state) { @@ -747,9 +745,9 @@ int eeprom_write_enable(unsigned dev_addr, int state) } #endif /* #if defined(CFG_EEPROM_WREN) */ - #define CFG_BOOT_EEPROM_PAGE_WRITE_BITS 3 -int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt) +int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, + uchar *buffer, unsigned cnt) { unsigned end = offset + cnt; unsigned blk_off; @@ -758,7 +756,8 @@ int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, un #if defined(CFG_EEPROM_WREN) eeprom_write_enable(dev_addr, 1); #endif - /* Write data until done or would cross a write page boundary. + /* + * Write data until done or would cross a write page boundary. * We must write the address again when changing pages * because the address counter only increments within a page. */ @@ -780,7 +779,8 @@ int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, un #define BOOT_EEPROM_PAGE_SIZE (1 << CFG_BOOT_EEPROM_PAGE_WRITE_BITS) #define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1)) - maxlen = BOOT_EEPROM_PAGE_SIZE - BOOT_EEPROM_PAGE_OFFSET(blk_off); + maxlen = BOOT_EEPROM_PAGE_SIZE - + BOOT_EEPROM_PAGE_OFFSET(blk_off); if (maxlen > I2C_RXTX_LEN) maxlen = I2C_RXTX_LEN; @@ -803,14 +803,15 @@ int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, un return rcode; } - -int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt) +int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset, + uchar *buffer, unsigned cnt) { unsigned end = offset + cnt; unsigned blk_off; int rcode = 0; - /* Read data until done or would cross a page boundary. + /* + * Read data until done or would cross a page boundary. * We must write the address again when changing pages * because the next page may be in a different device. */ @@ -844,7 +845,6 @@ int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, un return rcode; } - #if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT) int usb_board_init(void) { @@ -854,7 +854,8 @@ int usb_board_init(void) if ((act == NULL || strcmp(act, "hostdev") == 0) && !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) /* enable power on USB socket */ - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N); + out_be32((void*)GPIO1_OR, + in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N); for (i=0; i<1000; i++) udelay(1000); diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c index 88d5e8f..afc0eee 100644 --- a/board/freescale/mpc8323erdb/mpc8323erdb.c +++ b/board/freescale/mpc8323erdb/mpc8323erdb.c @@ -185,3 +185,37 @@ void ft_board_setup(void *blob, bd_t *bd) #endif } #endif + +#if defined(CFG_I2C_MAC_OFFSET) +int mac_read_from_eeprom(void) +{ + uchar buf[28]; + char str[18]; + int i = 0; + unsigned int crc = 0; + unsigned char enetvar[32]; + + /* Read MAC addresses from EEPROM */ + if (eeprom_read(CFG_I2C_EEPROM_ADDR, CFG_I2C_MAC_OFFSET, buf, 28)) { + printf("\nEEPROM @ 0x%02x read FAILED!!!\n", + CFG_I2C_EEPROM_ADDR); + } else { + if (crc32(crc, buf, 24) == *(unsigned int *)&buf[24]) { + printf("Reading MAC from EEPROM\n"); + for (i = 0; i < 4; i++) { + if (memcmp(&buf[i * 6], "\0\0\0\0\0\0", 6)) { + sprintf(str, + "%02X:%02X:%02X:%02X:%02X:%02X", + buf[i * 6], buf[i * 6 + 1], + buf[i * 6 + 2], buf[i * 6 + 3], + buf[i * 6 + 4], buf[i * 6 + 5]); + sprintf((char *)enetvar, + i ? "eth%daddr" : "ethaddr", i); + setenv((char *)enetvar, str); + } + } + } + } + return 0; +} +#endif /* CONFIG_I2C_MAC_OFFSET */ diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index d90cdb3..2119320 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -98,11 +98,8 @@ int board_early_init_f(void) /* Enable flash write */ bcsr[0xa] &= ~0x04; - /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2 h/w bug workaround) */ - if (immr->sysconf.spridr == SPR_8360_REV20 || - immr->sysconf.spridr == SPR_8360E_REV20 || - immr->sysconf.spridr == SPR_8360_REV21 || - immr->sysconf.spridr == SPR_8360E_REV21) + /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */ + if (REVID_MAJOR(immr->sysconf.spridr) == 2) bcsr[0xe] = 0x30; /* Enable second UART */ @@ -308,8 +305,8 @@ void ft_board_setup(void *blob, bd_t *bd) * if on mpc8360ea rev. 2.1, * change both ucc phy-connection-types from rgmii-id to rgmii-rxid */ - if (immr->sysconf.spridr == SPR_8360_REV21 || - immr->sysconf.spridr == SPR_8360E_REV21) { + if ((REVID_MAJOR(immr->sysconf.spridr) == 2) && + (REVID_MINOR(immr->sysconf.spridr) == 1)) { int nodeoffset; const char *prop; int path; diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c index e57a53f..f7cd5fe 100644 --- a/board/freescale/mpc837xemds/mpc837xemds.c +++ b/board/freescale/mpc837xemds/mpc837xemds.c @@ -12,6 +12,8 @@ #include <common.h> #include <i2c.h> +#include <asm/io.h> +#include <asm/fsl_serdes.h> #include <spd_sdram.h> #if defined(CONFIG_OF_LIBFDT) #include <libfdt.h> @@ -29,6 +31,34 @@ int board_early_init_f(void) /* Clear all of the interrupt of BCSR */ bcsr[0xe] = 0xff; +#ifdef CONFIG_FSL_SERDES + immap_t *immr = (immap_t *)CFG_IMMR; + u32 spridr = in_be32(&immr->sysconf.spridr); + + /* we check only part num, and don't look for CPU revisions */ + switch (spridr) { + case SPR_8377: + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + break; + case SPR_8378: + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + break; + case SPR_8379: + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + break; + default: + printf("serdes not configured: unknown CPU part number: " + "%04x\n", spridr >> 16); + break; + } +#endif /* CONFIG_FSL_SERDES */ return 0; } diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index 83fb60d..e054f4e 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -140,24 +140,21 @@ int board_early_init_f(void) u32 spridr = in_be32(&immr->sysconf.spridr); /* we check only part num, and don't look for CPU revisions */ - switch (spridr >> 16) { - case SPR_8379E_REV10 >> 16: - case SPR_8379_REV10 >> 16: + switch (PARTID_NO_E(spridr)) { + case SPR_8377: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; - case SPR_8378E_REV10 >> 16: - case SPR_8378_REV10 >> 16: + case SPR_8378: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; - case SPR_8377E_REV10 >> 16: - case SPR_8377_REV10 >> 16: + case SPR_8379: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; default: diff --git a/board/korat/config.mk b/board/korat/config.mk index 39966e0..fa8374f 100644 --- a/board/korat/config.mk +++ b/board/korat/config.mk @@ -24,14 +24,24 @@ # Korat (PPC440EPx) board # -TEXT_BASE = 0xFFFA0000 - PLATFORM_CPPFLAGS += -DCONFIG_440=1 ifeq ($(debug),1) PLATFORM_CPPFLAGS += -DDEBUG endif +ifeq ($(emul),1) +PLATFORM_CPPFLAGS += -fno-schedule-insns -fno-schedule-insns2 +endif + ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8CFF0000 +endif + +ifeq ($(perm),1) +PLATFORM_CPPFLAGS += -DCONFIG_KORAT_PERMANENT +TEXT_BASE = 0xFFFA0000 +else +TEXT_BASE = 0xF7F60000 +LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-F7FC.lds endif diff --git a/board/korat/init.S b/board/korat/init.S index bd0e8b4..bf8b2c8 100644 --- a/board/korat/init.S +++ b/board/korat/init.S @@ -43,7 +43,7 @@ tlbtab: * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the * speed up boot process. It is patched after relocation to enable SA_I */ - tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) + tlbentry( 0xF0000000, SZ_256M, 0xF0000000, 1, AC_R|AC_W|AC_X|SA_G ) /* * TLB entries for SDRAM are not needed on this platform. They are @@ -52,24 +52,32 @@ tlbtab: #ifdef CFG_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) + tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, + AC_R|AC_W|AC_X|SA_G ) #endif /* TLB-entry for PCI Memory */ - tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE + 0x00000000, SZ_256M, + CFG_PCI_MEMBASE + 0x00000000, 1, AC_R|AC_W|SA_G|SA_I ) + + tlbentry( CFG_PCI_MEMBASE + 0x10000000, SZ_256M, + CFG_PCI_MEMBASE + 0x10000000, 1, AC_R|AC_W|SA_G|SA_I ) + + tlbentry( CFG_PCI_MEMBASE + 0x20000000, SZ_256M, + CFG_PCI_MEMBASE + 0x20000000, 1, AC_R|AC_W|SA_G|SA_I ) + + tlbentry( CFG_PCI_MEMBASE + 0x30000000, SZ_256M, + CFG_PCI_MEMBASE + 0x30000000, 1, AC_R|AC_W|SA_G|SA_I ) /* TLB-entry for EBC */ tlbentry( CFG_CPLD_BASE, SZ_1K, CFG_CPLD_BASE, 1, AC_R|AC_W|SA_G|SA_I ) /* TLB-entry for Internal Registers & OCM */ /* I wonder why this must be executable -- lrj@acm.org 2007-10-08 */ - tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_R|AC_W|AC_X|SA_I ) + tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_R|AC_W|AC_X|SA_I ) /*TLB-entry PCI registers*/ - tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|SA_G|SA_I ) /* TLB-entry for peripherals */ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|SA_G|SA_I) @@ -78,3 +86,10 @@ tlbtab: tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|SA_G|SA_I) tlbtab_end + +#if defined(CONFIG_KORAT_PERMANENT) + .globl korat_branch_absolute +korat_branch_absolute: + mtlr r3 + blr +#endif diff --git a/board/korat/korat.c b/board/korat/korat.c index 90fd0a7..a7b4b27 100644 --- a/board/korat/korat.c +++ b/board/korat/korat.c @@ -2,12 +2,12 @@ * (C) Copyright 2007-2008 * Larry Johnson, lrj@acm.org * - * (C) Copyright 2006-2008 + * (C) Copyright 2006-2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * (C) Copyright 2006 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -39,12 +39,45 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ ulong flash_get_size(ulong base, int banknum); +#if defined(CONFIG_KORAT_PERMANENT) +void korat_buzzer(int const on) +{ + if (on) { + out_8((u8 *) CFG_CPLD_BASE + 0x05, + in_8((u8 *) CFG_CPLD_BASE + 0x05) | 0x80); + } else { + out_8((u8 *) CFG_CPLD_BASE + 0x05, + in_8((u8 *) CFG_CPLD_BASE + 0x05) & ~0x80); + } +} +#endif + int board_early_init_f(void) { - u32 sdr0_pfc1, sdr0_pfc2; - u32 reg; + uint32_t sdr0_pfc1, sdr0_pfc2; + uint32_t reg; int eth; +#if defined(CONFIG_KORAT_PERMANENT) + unsigned mscount; + + extern void korat_branch_absolute(uint32_t addr); + + for (mscount = 0; mscount < CFG_KORAT_MAN_RESET_MS; ++mscount) { + udelay(1000); + if (gpio_read_in_bit(CFG_GPIO_RESET_PRESSED_)) { + /* This call does not return. */ + korat_branch_absolute( + CFG_FLASH1_TOP - 2 * CFG_ENV_SECT_SIZE - 4); + } + } + korat_buzzer(1); + while (!gpio_read_in_bit(CFG_GPIO_RESET_PRESSED_)) + udelay(1000); + + korat_buzzer(0); +#endif + mtdcr(ebccfga, xbcfg); mtdcr(ebccfgd, 0xb8400000); @@ -75,8 +108,11 @@ int board_early_init_f(void) mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ mtdcr(uic2sr, 0xffffffff); /* clear all */ - /* take sim card reader and CF controller out of reset */ - out_8((u8 *) CFG_CPLD_BASE + 0x04, 0x80); + /* + * Take sim card reader and CF controller out of reset. Also enable PHY + * auto-detect until board-specific PHY resets are available. + */ + out_8((u8 *) CFG_CPLD_BASE + 0x02, 0xC0); /* Configure the two Ethernet PHYs. For each PHY, configure for fiber * if the SFP module is present, and for copper if it is not present. @@ -85,8 +121,8 @@ int board_early_init_f(void) if (gpio_read_in_bit(CFG_GPIO_SFP0_PRESENT_ + eth)) { /* SFP module not present: configure PHY for copper. */ /* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */ - out_8((u8 *) CFG_CPLD_BASE + 0x06, - in_8((u8 *) CFG_CPLD_BASE + 0x06) | + out_8((u8 *) CFG_CPLD_BASE + 0x03, + in_8((u8 *) CFG_CPLD_BASE + 0x03) | 0x06 << (4 * eth)); } else { /* SFP module present: configure PHY for fiber and @@ -99,10 +135,18 @@ int board_early_init_f(void) gpio_write_bit(CFG_GPIO_PHY0_EN, 1); gpio_write_bit(CFG_GPIO_PHY1_EN, 1); - /* select Ethernet pins */ + /* Wait 1 ms, then enable Fiber signal detect to PHYs. */ + udelay(1000); + out_8((u8 *) CFG_CPLD_BASE + 0x03, + in_8((u8 *) CFG_CPLD_BASE + 0x03) | 0x88); + + /* select Ethernet (and optionally IIC1) pins */ mfsdr(SDR0_PFC1, sdr0_pfc1); sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4; +#ifdef CONFIG_I2C_MULTI_BUS + sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL); +#endif mfsdr(SDR0_PFC2, sdr0_pfc2); sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4; @@ -116,6 +160,58 @@ int board_early_init_f(void) return 0; } +/* + * The boot flash on CS0 normally has its write-enable pin disabled, and so will + * not respond to CFI commands. This routine therefore fills in the flash + * information for the boot flash. (The flash at CS1 operates normally.) + */ +ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) +{ + uint32_t addr; + int i; + + if (1 != banknum) + return 0; + + info->size = CFG_FLASH0_SIZE; + info->sector_count = CFG_FLASH0_SIZE / 0x20000; + info->flash_id = 0x01000000; + info->portwidth = 2; + info->chipwidth = 2; + info->buffer_size = 32; + info->erase_blk_tout = 16384; + info->write_tout = 2; + info->buffer_write_tout = 5; + info->vendor = 2; + info->cmd_reset = 0x00F0; + info->interface = 2; + info->legacy_unlock = 0; + info->manufacturer_id = 1; + info->device_id = 0x007E; + +#if CFG_FLASH0_SIZE == 0x01000000 + info->device_id2 = 0x2101; +#elif CFG_FLASH0_SIZE == 0x04000000 + info->device_id2 = 0x2301; +#else +#error Unable to set device_id2 for current CFG_FLASH0_SIZE +#endif + + info->ext_addr = 0x0040; + info->cfi_version = 0x3133; + info->cfi_offset = 0x0055; + info->addr_unlock1 = 0x00000555; + info->addr_unlock2 = 0x000002AA; + info->name = "CFI conformant"; + for (i = 0, addr = -info->size; + i < info->sector_count; + ++i, addr += 0x20000) { + info->start[i] = addr; + info->protect[i] = 0x00; + } + return 1; +} + static int man_data_read(unsigned int addr) { /* @@ -189,12 +285,20 @@ static void set_serial_number(void) * If the environmental variable "serial#" is not set, try to set it * from the manufacturer's information serial EEPROM. */ - char s[MAN_SERIAL_NO_LENGTH + 1]; + char s[MAN_INFO_LENGTH + MAN_MAC_ADDR_LENGTH + 2]; + + if (getenv("serial#")) + return; + + if (!man_data_read_field(s, MAN_INFO_FIELD, MAN_INFO_LENGTH)) + return; + + s[MAN_INFO_LENGTH] = '-'; + if (!man_data_read_field(s + MAN_INFO_LENGTH + 1, MAN_MAC_ADDR_FIELD, + MAN_MAC_ADDR_LENGTH)) + return; - if (0 == getenv("serial#") && - 0 != man_data_read_field(s, MAN_SERIAL_NO_FIELD, - MAN_SERIAL_NO_LENGTH)) - setenv("serial#", s); + setenv("serial#", s); } static void set_mac_addresses(void) @@ -204,45 +308,58 @@ static void set_mac_addresses(void) * set, try to set them from the manufacturer's information serial * EEPROM. */ - char s[MAN_MAC_ADDR_LENGTH + 1]; + +#if MAN_MAC_ADDR_LENGTH % 2 != 0 +#error MAN_MAC_ADDR_LENGTH must be an even number +#endif + + char s[(3 * MAN_MAC_ADDR_LENGTH) / 2]; + char *src; + char *dst; if (0 != getenv("ethaddr") && 0 != getenv("eth1addr")) return; - if (0 == man_data_read_field(s, MAN_MAC_ADDR_FIELD, - MAN_MAC_ADDR_LENGTH)) + if (0 == man_data_read_field(s + (MAN_MAC_ADDR_LENGTH / 2) - 1, + MAN_MAC_ADDR_FIELD, MAN_MAC_ADDR_LENGTH)) return; + for (src = s + (MAN_MAC_ADDR_LENGTH / 2) - 1, dst = s; src != dst;) { + *dst++ = *src++; + *dst++ = *src++; + *dst++ = ':'; + } if (0 == getenv("ethaddr")) setenv("ethaddr", s); if (0 == getenv("eth1addr")) { - ++s[MAN_MAC_ADDR_LENGTH - 1]; + ++s[((3 * MAN_MAC_ADDR_LENGTH) / 2) - 2]; setenv("eth1addr", s); } } int misc_init_r(void) { - uint pbcr; - int size_val = 0; - u32 reg; + uint32_t pbcr; + int size_val; + uint32_t reg; unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1; - char *act = getenv("usbact"); - - /* Re-do flash sizing to get full correct info */ + uint32_t const flash1_size = gd->bd->bi_flashsize - CFG_FLASH0_SIZE; + char const *const act = getenv("usbact"); - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + /* + * Re-do FLASH1 sizing and adjust flash start and offset. + */ + gd->bd->bi_flashstart = CFG_FLASH1_TOP - flash1_size; gd->bd->bi_flashoffset = 0; - mtdcr(ebccfga, pb0cr); + mtdcr(ebccfga, pb1cr); pbcr = mfdcr(ebccfgd); - size_val = ffs(gd->bd->bi_flashsize) - 21; + size_val = ffs(flash1_size) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtdcr(ebccfga, pb0cr); + mtdcr(ebccfga, pb1cr); mtdcr(ebccfgd, pbcr); /* @@ -250,14 +367,37 @@ int misc_init_r(void) */ flash_get_size(gd->bd->bi_flashstart, 0); - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, -CFG_MONITOR_LEN, 0xffffffff, - &flash_info[0]); + /* + * Re-do FLASH1 sizing and adjust flash offset to reserve space for + * environment + */ + gd->bd->bi_flashoffset = + CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - CFG_FLASH1_ADDR; + mtdcr(ebccfga, pb1cr); + pbcr = mfdcr(ebccfgd); + size_val = ffs(gd->bd->bi_flashsize - CFG_FLASH0_SIZE) - 21; + pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); + mtdcr(ebccfga, pb1cr); + mtdcr(ebccfgd, pbcr); + + /* Monitor protection ON by default */ +#if defined(CONFIG_KORAT_PERMANENT) + (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + flash_info + 1); +#else + (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + flash_info); +#endif /* Env protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + flash_info); (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + 2 * CFG_ENV_SECT_SIZE - 1, - &flash_info[0]); + CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + flash_info); /* * USB suff... @@ -393,6 +533,8 @@ int misc_init_r(void) set_serial_number(); set_mac_addresses(); + gpio_write_bit(CFG_GPIO_ATMEGA_RESET_, 1); + return 0; } @@ -402,10 +544,10 @@ int checkboard(void) u8 const rev = in_8((u8 *) CFG_CPLD_BASE + 0); printf("Board: Korat, Rev. %X", rev); - if (s != NULL) + if (s) printf(", serial# %s", s); - printf(", Ethernet PHY 0: "); + printf(".\n Ethernet PHY 0: "); if (gpio_read_out_bit(CFG_GPIO_PHY0_FIBER_SEL)) printf("fiber"); else @@ -418,7 +560,10 @@ int checkboard(void) printf("copper"); printf(".\n"); - return (0); +#if defined(CONFIG_KORAT_PERMANENT) + printf(" Executing permanent copy of U-Boot.\n"); +#endif + return 0; } #if defined(CFG_DRAM_TEST) @@ -529,23 +674,26 @@ void pci_target_init(struct pci_controller *hose) /* * PowerPC440EPX PCI Master configuration. * Map one 1Gig range of PLB/processor addresses to PCI memory space. - * PLB address 0xA0000000-0xDFFFFFFF - * ==> PCI address 0xA0000000-0xDFFFFFFF + * PLB address 0x80000000-0xBFFFFFFF + * ==> PCI address 0x80000000-0xBFFFFFFF * Use byte reversed out routines to handle endianess. * Make this region non-prefetchable. */ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0PCILA, + CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */ /* and enable region */ out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ - out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM1LA, + CFG_PCI_MEMBASE + 0x20000000); /* PMM0 Local Address */ + out32r(PCIX0_PMM1PCILA, + CFG_PCI_MEMBASE + 0x20000000); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */ /* and enable region */ diff --git a/board/korat/u-boot-F7FC.lds b/board/korat/u-boot-F7FC.lds new file mode 100644 index 0000000..cceb4f5 --- /dev/null +++ b/board/korat/u-boot-F7FC.lds @@ -0,0 +1,143 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xF7FBFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xF7FBF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index affaeff..7c3cf49 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -6,7 +6,7 @@ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com * - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * This program is free software; you can redistribute it and/or @@ -35,6 +35,7 @@ #include <asm/mmu.h> #include <asm/io.h> #include <ppc440.h> +#include <watchdog.h> /* * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory @@ -99,87 +100,37 @@ static void wait_ddr_idle(void) */ } -static void blank_string(int size) -{ - int i; - - for (i=0; i<size; i++) - putc('\b'); - for (i=0; i<size; i++) - putc(' '); - for (i=0; i<size; i++) - putc('\b'); -} - static void program_ecc(u32 start_address, u32 num_bytes, u32 tlb_word2_i_value) { - u32 current_address; - u32 end_address; - u32 address_increment; u32 val; - char str[] = "ECC generation -"; - char slash[] = "\\|/-\\|/-"; - int loop = 0; - int loopi = 0; - - current_address = start_address; + u32 current_addr = start_address; + int bytes_remaining; sync(); - eieio(); wait_ddr_idle(); - if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) { - /* ECC bit set method for non-cached memory */ - address_increment = 4; - end_address = current_address + num_bytes; - - puts(str); - - while (current_address < end_address) { - *((u32 *)current_address) = 0x00000000; - current_address += address_increment; - - if ((loop++ % (2 << 20)) == 0) { - putc('\b'); - putc(slash[loopi++ % 8]); - } - } + /* + * Because of 440EPx errata CHIP 11, we don't touch the last 256 + * bytes of SDRAM. + */ + bytes_remaining = num_bytes - CFG_MEM_TOP_HIDE; - blank_string(strlen(str)); - } else { - /* ECC bit set method for cached memory */ -#if 0 /* test-only: will remove this define later, when ECC problems are solved! */ - /* - * Some boards (like lwmon5) need to preserve the memory - * content upon ECC generation (for the log-buffer). - * Therefore we don't fill the memory with a pattern or - * just zero it, but write the same values back that are - * already in the memory cells. - */ - address_increment = CFG_CACHELINE_SIZE; - end_address = current_address + num_bytes; - - current_address = start_address; - while (current_address < end_address) { - /* - * TODO: Th following sequence doesn't work correctly. - * Just invalidating and flushing the cache doesn't - * seem to trigger the re-write of the memory. - */ - ppcDcbi(current_address); - ppcDcbf(current_address); - current_address += CFG_CACHELINE_SIZE; - } -#else - dcbz_area(start_address, num_bytes); - dflush(); -#endif + /* + * We have to write the ECC bytes by zeroing and flushing in smaller + * steps, since the whole 256MByte takes too long for the external + * watchdog. + */ + while (bytes_remaining > 0) { + dcbz_area(current_addr, min((64 << 20), bytes_remaining)); + current_addr += 64 << 20; + bytes_remaining -= 64 << 20; + WATCHDOG_RESET(); } + dflush(); sync(); - eieio(); wait_ddr_idle(); /* Clear error status */ @@ -191,7 +142,6 @@ static void program_ecc(u32 start_address, mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF)); sync(); - eieio(); wait_ddr_idle(); } #endif diff --git a/board/mpr2/Makefile b/board/mpr2/Makefile new file mode 100644 index 0000000..17ca17e --- /dev/null +++ b/board/mpr2/Makefile @@ -0,0 +1,54 @@ +# +# Copyright (C) 2007 +# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> +# +# Copyright (C) 2007 +# Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +# +# Copyright (C) 2007 +# Kenati Technologies, Inc. +# +# (C) Copyright 2008 +# Mark Jonas <mark.jonas@de.bosch.com> +# +# board/mpr2/Makefile +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := mpr2.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/mpr2/config.mk b/board/mpr2/config.mk new file mode 100644 index 0000000..6d41d97 --- /dev/null +++ b/board/mpr2/config.mk @@ -0,0 +1,37 @@ +# +# Copyright (C) 2007 +# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> +# +# Copyright (C) 2007 +# Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +# +# Copyright (C) 2007 +# Kenati Technologies, Inc. +# +# Copyright (C) 2008 +# Mark Jonas <mark.jonas@de.bosch.com> +# +# board/mpr2/config.mk +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +# +# TEXT_BASE refers to image _after_ relocation. +# +# NOTE: Must match value used in u-boot.lds (in this directory). +# + +TEXT_BASE = 0x8FFC0000 diff --git a/board/mpr2/lowlevel_init.S b/board/mpr2/lowlevel_init.S new file mode 100644 index 0000000..060957a --- /dev/null +++ b/board/mpr2/lowlevel_init.S @@ -0,0 +1,148 @@ +/* + * (C) Copyright 2008 + * Mark Jonas <mark.jonas@de.bosch.com> + * + * (C) Copyright 2007 + * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * board/mpr2/lowlevel_init.S + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + +/* + * Set frequency multipliers and dividers in FRQCR. + */ + mov.l WTCSR_A,r1 + mov.l WTCSR_D,r0 + mov.w r0,@r1 + + mov.l WTCNT_A,r1 + mov.l WTCNT_D,r0 + mov.w r0,@r1 + + mov.l FRQCR_A,r1 + mov.l FRQCR_D,r0 + mov.w r0,@r1 + +/* + * Setup CS0 (Flash). + */ + mov.l CS0BCR_A, r1 + mov.l CS0BCR_D, r0 + mov.l r0, @r1 + + mov.l CS0WCR_A, r1 + mov.l CS0WCR_D, r0 + mov.l r0, @r1 + +/* + * Setup CS3 (SDRAM). + */ + mov.l CS3BCR_A, r1 + mov.l CS3BCR_D, r0 + mov.l r0, @r1 + + mov.l CS3WCR_A, r1 + mov.l CS3WCR_D, r0 + mov.l r0, @r1 + + mov.l SDCR_A, r1 + mov.l SDCR_D1, r0 + mov.l r0, @r1 + + mov.l RTCSR_A, r1 + mov.l RTCSR_D, r0 + mov.l r0, @r1 + + mov.l RTCNT_A, r1 + mov.l RTCNT_D, r0 + mov.l r0, @r1 + + mov.l RTCOR_A, r1 + mov.l RTCOR_D, r0 + mov.l r0, @r1 + + mov.l SDCR_A, r1 + mov.l SDCR_D2, r0 + mov.l r0, @r1 + + mov.l SDMR3_A, r1 + mov.l SDMR3_D, r0 + add r0, r1 + mov #0, r0 + mov.w r0, @r1 + + rts + nop + + .align 4 + +/* + * Configuration for MPR2 A.3 through A.7 + */ + +/* + * PLL Settings + */ +FRQCR_D: .long 0x1103 /* I:B:P=8:4:2 */ +WTCNT_D: .long 0x5A00 /* start counting at zero */ +WTCSR_D: .long 0xA507 /* divide by 4096 */ + +/* + * Spansion S29GL256N11 @ 48 MHz + */ +CS0BCR_D: .long 0x12490400 /* 1 idle cycle inserted, normal space, 16 bit */ +CS0WCR_D: .long 0x00000340 /* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */ + +/* + * Samsung K4S511632B-UL75 @ 48 MHz + * Micron MT48LC32M16A2-75 @ 48 MHz + */ +CS3BCR_D: .long 0x10004400 /* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */ +CS3WCR_D: .long 0x00000091 /* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */ +SDCR_D1: .long 0x00000012 /* no refresh, 13 rows, 10 cols, NO bank active mode */ +SDCR_D2: .long 0x00000812 /* refresh */ +RTCSR_D: .long 0xA55A0008 /* 1/4, once */ +RTCNT_D: .long 0xA55A005D /* count 93 */ +RTCOR_D: .long 0xa55a005d /* count 93 */ +SDMR3_D: .long 0x440 /* mode register CL2, burst read and SINGLE WRITE */ + +/* + * Registers + */ + +FRQCR_A: .long 0xA415FF80 +WTCNT_A: .long 0xA415FF84 +WTCSR_A: .long 0xA415FF86 + +#define BSC_BASE 0xA4FD0000 +CS0BCR_A: .long BSC_BASE + 0x04 +CS3BCR_A: .long BSC_BASE + 0x0C +CS0WCR_A: .long BSC_BASE + 0x24 +CS3WCR_A: .long BSC_BASE + 0x2C +SDCR_A: .long BSC_BASE + 0x44 +RTCSR_A: .long BSC_BASE + 0x48 +RTCNT_A: .long BSC_BASE + 0x4C +RTCOR_A: .long BSC_BASE + 0x50 +SDMR3_A: .long BSC_BASE + 0x5000 diff --git a/board/mpr2/mpr2.c b/board/mpr2/mpr2.c new file mode 100644 index 0000000..2ddb0c1 --- /dev/null +++ b/board/mpr2/mpr2.c @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2008 + * Mark Jonas <mark.jonas@de.bosch.com> + * + * board/mpr2/mpr2.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/processor.h> + +int checkboard(void) +{ + puts("BOARD: MPR2\n"); + return 0; +} + +int board_init(void) +{ + /* + * For MPR2 A.3 through A.7 + */ + + /* CS2: Ethernet (0xA8000000 - 0xABFFFFFF) */ + __raw_writel(0x36db0400, CS2BCR); /* 4 idle cycles, normal space, 16 bit data bus */ + __raw_writel(0x000003c0, CS2WCR); /* (WR:8), no ext. wait */ + + /* CS4: CAN1 (0xB0000000 - 0xB3FFFFFF) */ + __raw_writel(0x00000200, CS4BCR); /* no idle cycles, normal space, 8 bit data bus */ + __raw_writel(0x00100981, CS4WCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */ + + /* CS5a: CAN2 (0xB4000000 - 0xB5FFFFFF) */ + __raw_writel(0x00000200, CS5ABCR); /* no idle cycles, normal space, 8 bit data bus */ + __raw_writel(0x00100981, CS5AWCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */ + + /* CS5b: CAN3 (0xB6000000 - 0xB7FFFFFF) */ + __raw_writel(0x00000200, CS5BBCR); /* no idle cycles, normal space, 8 bit data bus */ + __raw_writel(0x00100981, CS5BWCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */ + + /* CS6a: Rotary (0xB8000000 - 0xB9FFFFFF) */ + __raw_writel(0x00000200, CS6ABCR); /* no idle cycles, normal space, 8 bit data bus */ + __raw_writel(0x001009C1, CS6AWCR); /* (SW:1.5 WR:3 HW:1.5), no ext. wait */ + + /* set Pin Select Register A: /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2, /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND */ + __raw_writew(0xAABC, PSELA); /* 10 10 10 10 10 11 11 00 */ + + /* set Pin Select Register B: /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC, LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved */ + __raw_writew(0x3C00, PSELB); /* 0 0 11 11 0 0 00000000 */ + + /* set Pin Select Register C: SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved */ + __raw_writew(0x0000, PSELC); /* 00 00 00 00 00000000 */ + + /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK, Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved */ + __raw_writew(0x0000, PSELD); /* 0 00 00 00 00 00 00 00 0 */ + + /* OTH: (00) Other fuction + * GPO: (01) General Purpose Output + * GPI: (11) General Purpose Input + * GPI+: (10) General Purpose Input with internal pull-up + *------------------------------------------------------- + * A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5); + * A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1); */ + __raw_writew(0x5555, PACR); /* 01 01 01 01 01 01 01 01 */ + + /* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1); + * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0); */ + __raw_writew(0x5555, PBCR); /* 01 01 01 01 01 01 01 01 */ + + /* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4); + * C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0; */ + __raw_writew(0x5500, PCCR); /* 01 01 01 01 00 00 00 00 */ + + /* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4); + * D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0); */ + __raw_writew(0x5555, PDCR); /* 01 01 01 01 01 01 01 01 */ + + /* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP; + * E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM; */ + __raw_writew(0x2800, PECR); /* 00 10 10 00 00 00 00 00 */ + + /* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3; + * F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc); */ + __raw_writew(0x0002, PFCR); /* 00 00 00 00 00 00 00 10 */ + + /* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ);G4 GPI(KEY2); + * G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9); */ + __raw_writew(0x03D5, PGCR); /* 00 00 00 11 11 01 01 01 */ + + /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE); + * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR; */ + __raw_writew(0x0050, PHCR); /* 00 00 00 00 01 01 00 00 */ + + /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3; + * J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC; */ + __raw_writew(0x0000, PJCR); /* 00 00 00 00 00 00 00 00 */ + + /* K7 (x); K6 (x); K5 (x); K4 (x) + * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nc); K0 PINT4(FLASH_READY); */ + __raw_writew(0x00FB, PKCR); /* 00 00 00 00 11 11 10 11 */ + + /* L7 TRST; L6 TMS; L5 TDO; L4 TDI; + * L3 TCK; L2 (x); L1 (x); L0 (x); */ + __raw_writew(0x0000, PLCR); /* 00 00 00 00 00 00 00 00 */ + + /* M7 GPO(CURRENT_SINK);M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED); M4 GPO(LAN_RESET); + * M3 GPO(BUZZER); M2 GPO(LCD_BL); M1 CS5B(CAN3_CS); M0 GPI+(nc); */ + __raw_writew(0x5552, PMCR); /* 01 01 01 01 01 01 00 10 */ + __raw_writeb(0xF0, PMDR); /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit, LAN_RESET=off, BUZZER=off, LCD_BL=off */ + + /* P7 (x); P6 (x); P5 (x); P4 GPO(on pullup); + * P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ);P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ); */ + __raw_writew(0x0100, PPCR); /* 00 00 00 01 00 00 00 00 */ + __raw_writeb(0x10, PPDR); /* no current flow through pullup */ + + /* R7 A25; R6 A24; R5 A23; R4 A22; + * R3 A21; R2 A20; R1 A19; R0 A0; */ + __raw_writew(0x0000, PRCR); /* 00 00 00 00 00 00 00 00 */ + + /* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2); + * S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK; */ + __raw_writew(0x0140, PSCR); /* 00 00 00 01 01 00 00 00 */ + + /* T7 (x); T6 (x); T5 (x); T4 COM1_CTS; + * T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG); */ + __raw_writew(0x0001, PTCR); /* 00 00 00 00 00 00 00 01 */ + + /* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT); + * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK; */ + __raw_writew(0x0240, PUCR); /* 00 00 00 10 01 00 00 00 */ + + /* V7 (x); V6 (x); V5 (x); V4 GPO(MID2); + * V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT); */ + __raw_writew(0x0142, PVCR); /* 00 00 00 01 01 00 00 10 */ + + return 0; +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_memstart = CFG_SDRAM_BASE; + gd->bd->bi_memsize = CFG_SDRAM_SIZE; + printf("SDRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + diff --git a/board/mpr2/u-boot.lds b/board/mpr2/u-boot.lds new file mode 100644 index 0000000..6fee7f2 --- /dev/null +++ b/board/mpr2/u-boot.lds @@ -0,0 +1,109 @@ +/* + * Copyright (C) 2007 + * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * Copyright (C) 2007 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * Copyright (C) 2008 + * Mark Jonas <mark.jonas@de.bosch.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + Base address of internal SDRAM is 0x8C000000. + U-Boot resides in the last 256 kB of the 64 MB. + + NOTE: This address must match with the definition of + TEXT_BASE in config.mk (in this directory). + + */ + . = 0x8C000000 + (64*1024*1024) - (256*1024); + + PROVIDE (reloc_dst = .); + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + cpu/sh3/start.o (.text) + . = ALIGN(8192); + common/environment.o (.ppcenv) + . = ALIGN(8192); + common/environment.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(.rodata) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + PROVIDE (__u_boot_cmd_start = .); + .u_boot_cmd : + { + *(.u_boot_cmd) + . = ALIGN(4); + } + PROVIDE (__u_boot_cmd_end = .); + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (_end = .); +} diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c index b764499..287f32e 100644 --- a/board/prodrive/alpr/alpr.c +++ b/board/prodrive/alpr/alpr.c @@ -23,10 +23,12 @@ #include <common.h> -#include <asm/processor.h> +#include <libfdt.h> +#include <fdt_support.h> #include <spd_sdram.h> #include <ppc4xx_enet.h> #include <miiphy.h> +#include <asm/processor.h> DECLARE_GLOBAL_DATA_PTR; @@ -315,3 +317,24 @@ int post_hotkeys_pressed(void) return (ctrlc()); } #endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + u32 val[4]; + int rc; + + ft_cpu_setup(blob, bd); + + /* Fixup NOR mapping */ + val[0] = 0; /* chip select number */ + val[1] = 0; /* always 0 */ + val[2] = gd->bd->bi_flashstart; + val[3] = gd->bd->bi_flashsize; + rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", + val, sizeof(val), 1); + if (rc) + printf("Unable to update property NOR mapping, err=%s\n", + fdt_strerror(rc)); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/prodrive/alpr/init.S b/board/prodrive/alpr/init.S index 135674c..76164ce 100644 --- a/board/prodrive/alpr/init.S +++ b/board/prodrive/alpr/init.S @@ -90,7 +90,16 @@ tlbtab: tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I ) tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) +#ifdef CONFIG_4xx_DCACHE + tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G) +#else tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) +#endif + +#ifdef CFG_INIT_RAM_DCACHE + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) +#endif tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) /* PCI */ diff --git a/board/r2dplus/Makefile b/board/r2dplus/Makefile new file mode 100644 index 0000000..ed609ea --- /dev/null +++ b/board/r2dplus/Makefile @@ -0,0 +1,43 @@ +# +# Copyright (C) 2007,2008 +# Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := r2dplus.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +################################################################# + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +################################################################# diff --git a/board/r2dplus/config.mk b/board/r2dplus/config.mk new file mode 100644 index 0000000..1ec7dcc --- /dev/null +++ b/board/r2dplus/config.mk @@ -0,0 +1,23 @@ +# +# Copyright (C) 2007,2008 +# Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# +# NOTE: Must match value used in u-boot.lds (in this directory). +# +TEXT_BASE = 0x0FFC0000 diff --git a/board/r2dplus/lowlevel_init.S b/board/r2dplus/lowlevel_init.S new file mode 100644 index 0000000..5755de8 --- /dev/null +++ b/board/r2dplus/lowlevel_init.S @@ -0,0 +1,154 @@ +/* + * modified from SH-IPL+g (init-r0p751rlc0011rl.S) + * Initial Register Data for R0P751RLC0011RL (SH7751R 240MHz/120MHz/60MHz) + * Coyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +*/ + +#include <config.h> +#include <version.h> + +#include <asm/processor.h> + + .global lowlevel_init + .text + .align 2 + +lowlevel_init: + + mov.l CCR_A, r1 + mov.l CCR_D_D, r0 + mov.l r0,@r1 + + mov.l MMUCR_A,r1 + mov.l MMUCR_D,r0 + mov.w r0,@r1 + + mov.l BCR1_A,r1 + mov.l BCR1_D,r0 + mov.l r0,@r1 + + mov.l BCR2_A,r1 + mov.l BCR2_D,r0 + mov.w r0,@r1 + + mov.l BCR3_A,r1 + mov.l BCR3_D,r0 + mov.w r0,@r1 + + mov.l BCR4_A,r1 + mov.l BCR4_D,r0 + mov.l r0,@r1 + + mov.l WCR1_A,r1 + mov.l WCR1_D,r0 + mov.l r0,@r1 + + mov.l WCR2_A,r1 + mov.l WCR2_D,r0 + mov.l r0,@r1 + + mov.l WCR3_A,r1 + mov.l WCR3_D,r0 + mov.l r0,@r1 + + mov.l PCR_A,r1 + mov.l PCR_D,r0 + mov.w r0,@r1 + + mov.l LED_A,r1 + mov #0xff,r0 + mov.w r0,@r1 + + mov.l MCR_A,r1 + mov.l MCR_D1,r0 + mov.l r0,@r1 + + mov.l RTCNT_A,r1 + mov.l RTCNT_D,r0 + mov.w r0,@r1 + + mov.l RTCOR_A,r1 + mov.l RTCOR_D,r0 + mov.w r0,@r1 + + mov.l RFCR_A,r1 + mov.l RFCR_D,r0 + mov.w r0,@r1 + + mov.l RTCSR_A,r1 + mov.l RTCSR_D,r0 + mov.w r0,@r1 + + mov.l SDMR3_A,r1 + mov #0x55,r0 + mov.b r0,@r1 + + /* Wait DRAM refresh 30 times */ + mov.l RFCR_A,r1 + mov #30,r3 +1: + mov.w @r1,r0 + extu.w r0,r2 + cmp/hi r3,r2 + bf 1b + + mov.l MCR_A,r1 + mov.l MCR_D2,r0 + mov.l r0,@r1 + + mov.l SDMR3_A,r1 + mov #0,r0 + mov.b r0,@r1 + + mov.l IRLMASK_A,r1 + mov.l IRLMASK_D,r0 + mov.l r0,@r1 + + mov.l CCR_A, r1 + mov.l CCR_D_E, r0 + mov.l r0, @r1 + + rts + nop + + .align 2 +CCR_A: .long CCR /* Cache Control Register */ +CCR_D_D: .long 0x0808 /* Flush the cache, disable */ +CCR_D_E: .long 0x8000090B + +FRQCR_A: .long FRQCR /* FRQCR Address */ +FRQCR_D: .long 0x00000e0a /* 03/07/15 modify */ +BCR1_A: .long BCR1 /* BCR1 Address */ +BCR1_D: .long 0x00180008 +BCR2_A: .long BCR2 /* BCR2 Address */ +BCR2_D: .long 0xabe8 +BCR3_A: .long BCR3 /* BCR3 Address */ +BCR3_D: .long 0x0000 +BCR4_A: .long BCR4 /* BCR4 Address */ +BCR4_D: .long 0x00000010 +WCR1_A: .long WCR1 /* WCR1 Address */ +WCR1_D: .long 0x33343333 +WCR2_A: .long WCR2 /* WCR2 Address */ +WCR2_D: .long 0xcff86fbf +WCR3_A: .long WCR3 /* WCR3 Address */ +WCR3_D: .long 0x07777707 +LED_A: .long 0x04000036 /* LED Address */ +RTCNT_A: .long RTCNT /* RTCNT Address */ +RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */ +RTCOR_A: .long RTCOR /* RTCOR Address */ +RTCOR_D: .long 0xA534 /* RTCOR Write Code */ +RTCSR_A: .long RTCSR /* RTCSR Address */ +RTCSR_D: .long 0xA510 /* RTCSR Write Code */ +SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */ +SDMR3_D: .long 0x55 +MCR_A: .long MCR /* MCR Address */ +MCR_D1: .long 0x081901F4 /* MRSET:'0' */ +MCR_D2: .long 0x481901F4 /* MRSET:'1' */ +RFCR_A: .long RFCR /* RFCR Address */ +RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */ +PCR_A: .long PCR /* PCR Address */ +PCR_D: .long 0x0000 +MMUCR_A: .long MMUCR /* MMUCCR Address */ +MMUCR_D: .long 0x00000000 /* MMUCCR Data */ +IRLMASK_A: .long 0xA4000000 /* IRLMASK Address */ +IRLMASK_D: .long 0x00000000 /* IRLMASK Data */ diff --git a/board/r2dplus/r2dplus.c b/board/r2dplus/r2dplus.c new file mode 100644 index 0000000..2ee3ea2 --- /dev/null +++ b/board/r2dplus/r2dplus.c @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2007,2008 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ide.h> +#include <asm/processor.h> +#include <asm/pci.h> + +int checkboard(void) +{ + puts("BOARD: Renesas Solutions R2D Plus\n"); + return 0; +} + +int board_init(void) +{ + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_memstart = CFG_SDRAM_BASE; + gd->bd->bi_memsize = CFG_SDRAM_SIZE; + printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + +int board_late_init(void) +{ + return 0; +} + +#define FPGA_BASE 0xA4000000 +#define FPGA_CFCTL (FPGA_BASE + 0x04) +#define FPGA_CFPOW (FPGA_BASE + 0x06) +#define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A) + +void ide_set_reset (int idereset) +{ + /* if reset = 1 IDE reset will be asserted */ + if (idereset){ + (*(vu_short *)FPGA_CFCTL) = 0x432; + (*(vu_short *)FPGA_CFPOW) |= 0x02; + (*(vu_short *)FPGA_CFCDINTCLR) = 0x01; + } +} + +#if defined(CONFIG_PCI) +static struct pci_controller hose; +void pci_init_board(void) +{ + pci_sh7751_init( &hose ); +} +#endif /* CONFIG_PCI */ diff --git a/board/r2dplus/u-boot.lds b/board/r2dplus/u-boot.lds new file mode 100644 index 0000000..96d8d81 --- /dev/null +++ b/board/r2dplus/u-boot.lds @@ -0,0 +1,105 @@ +/* + * Copyrigth (c) 2007,2008 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + Base address of internal SDRAM is 0x0C000000. + Although size of SDRAM can be either 16 or 32 MBytes, + we assume 16 MBytes (ie ignore upper half if the full + 32 MBytes is present). + + NOTE: This address must match with the definition of + TEXT_BASE in config.mk (in this directory). + + */ + . = 0x0C000000 + (64*1024*1024) - (256*1024); + + PROVIDE (reloc_dst = .); + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + cpu/sh4/start.o (.text) + . = ALIGN(8192); + common/environment.o (.ppcenv) + . = ALIGN(8192); + common/environment.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(.rodata) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + PROVIDE (__u_boot_cmd_start = .); + .u_boot_cmd : + { + *(.u_boot_cmd) + . = ALIGN(4); + } + PROVIDE (__u_boot_cmd_end = .); + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (_end = .); +} diff --git a/board/r7780mp/Makefile b/board/r7780mp/Makefile new file mode 100644 index 0000000..554dca1 --- /dev/null +++ b/board/r7780mp/Makefile @@ -0,0 +1,44 @@ +# +# Copyright (C) 2007,2008 Nobuhiro Iwamatsu +# +# board/r7780mp/Makefile +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := r7780mp.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/r7780mp/config.mk b/board/r7780mp/config.mk new file mode 100644 index 0000000..6a045a1 --- /dev/null +++ b/board/r7780mp/config.mk @@ -0,0 +1,27 @@ +# +# Copyright (C) 2007,2008 Nobuhiro Iwamatsu +# +# board/r77870mp/config.mk +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +# +# TEXT_BASE refers to image _after_ relocation. +# +# NOTE: Must match value used in u-boot.lds (in this directory). +# + +TEXT_BASE = 0x0FFC0000 diff --git a/board/r7780mp/lowlevel_init.S b/board/r7780mp/lowlevel_init.S new file mode 100644 index 0000000..eb5d8b7 --- /dev/null +++ b/board/r7780mp/lowlevel_init.S @@ -0,0 +1,428 @@ +/* + * Copyright (C) 2007,2008 Nobuhiro Iwamatsu + * + * u-boot/board/r7780mp/lowlevel_init.S + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/processor.h> + +/* + * Board specific low level init code, called _very_ early in the + * startup sequence. Relocation to SDRAM has not happened yet, no + * stack is available, bss section has not been initialised, etc. + * + * (Note: As no stack is available, no subroutines can be called...). + */ + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + + mov.l CCR_A, r1 /* Address of Cache Control Register */ + mov.l CCR_D, r0 /* Instruction Cache Invalidate */ + mov.l r0, @r1 + + mov.l FRQCR_A, r1 /* Frequency control register */ + mov.l FRQCR_D, r0 + mov.l r0, @r1 + + /* pin_multi_setting */ + mov.l BBG_PMMR_A,r1 + mov.l BBG_PMMR_D_PMSR1,r0 + mov.l r0,@r1 + + mov.l BBG_PMSR1_A,r1 + mov.l BBG_PMSR1_D,r0 + mov.l r0,@r1 + + mov.l BBG_PMMR_A,r1 + mov.l BBG_PMMR_D_PMSR2,r0 + mov.l r0,@r1 + + mov.l BBG_PMSR2_A,r1 + mov.l BBG_PMSR2_D,r0 + mov.l r0,@r1 + + mov.l BBG_PMMR_A,r1 + mov.l BBG_PMMR_D_PMSR3,r0 + mov.l r0,@r1 + + mov.l BBG_PMSR3_A,r1 + mov.l BBG_PMSR3_D,r0 + mov.l r0,@r1 + + mov.l BBG_PMMR_A,r1 + mov.l BBG_PMMR_D_PMSR4,r0 + mov.l r0,@r1 + + mov.l BBG_PMSR4_A,r1 + mov.l BBG_PMSR4_D,r0 + mov.l r0,@r1 + + mov.l BBG_PMMR_A,r1 + mov.l BBG_PMMR_D_PMSRG,r0 + mov.l r0,@r1 + + mov.l BBG_PMSRG_A,r1 + mov.l BBG_PMSRG_D,r0 + mov.l r0,@r1 + + /* cpg_setting */ + mov.l FRQCR_A,r1 + mov.l FRQCR_D,r0 + mov.l r0,@r1 + + mov.l DLLCSR_A,r1 + mov.l DLLCSR_D,r0 + mov.l r0,@r1 + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + + /* wait 200us */ + mov.l REPEAT0_R3,r3 + mov #0,r2 +repeat0: + add #1,r2 + cmp/hs r3,r2 + bf repeat0 + nop + + /* bsc_setting */ + mov.l MMSELR_A,r1 + mov.l MMSELR_D,r0 + mov.l r0,@r1 + + mov.l BCR_A,r1 + mov.l BCR_D,r0 + mov.l r0,@r1 + + mov.l CS0BCR_A,r1 + mov.l CS0BCR_D,r0 + mov.l r0,@r1 + + mov.l CS1BCR_A,r1 + mov.l CS1BCR_D,r0 + mov.l r0,@r1 + + mov.l CS2BCR_A,r1 + mov.l CS2BCR_D,r0 + mov.l r0,@r1 + + mov.l CS4BCR_A,r1 + mov.l CS4BCR_D,r0 + mov.l r0,@r1 + + mov.l CS5BCR_A,r1 + mov.l CS5BCR_D,r0 + mov.l r0,@r1 + + mov.l CS6BCR_A,r1 + mov.l CS6BCR_D,r0 + mov.l r0,@r1 + + mov.l CS0WCR_A,r1 + mov.l CS0WCR_D,r0 + mov.l r0,@r1 + + mov.l CS1WCR_A,r1 + mov.l CS1WCR_D,r0 + mov.l r0,@r1 + + mov.l CS2WCR_A,r1 + mov.l CS2WCR_D,r0 + mov.l r0,@r1 + + mov.l CS4WCR_A,r1 + mov.l CS4WCR_D,r0 + mov.l r0,@r1 + + mov.l CS5WCR_A,r1 + mov.l CS5WCR_D,r0 + mov.l r0,@r1 + + mov.l CS6WCR_A,r1 + mov.l CS6WCR_D,r0 + mov.l r0,@r1 + + mov.l CS5PCR_A,r1 + mov.l CS5PCR_D,r0 + mov.l r0,@r1 + + mov.l CS6PCR_A,r1 + mov.l CS6PCR_D,r0 + mov.l r0,@r1 + + /* ddr_setting */ + /* wait 200us */ + mov.l REPEAT0_R3,r3 + mov #0,r2 +repeat1: + add #1,r2 + cmp/hs r3,r2 + bf repeat1 + nop + + mov.l MIM_U_A,r0 + mov.l MIM_U_D,r1 + synco + mov.l r1,@r0 + synco + + mov.l MIM_L_A,r0 + mov.l MIM_L_D0,r1 + synco + mov.l r1,@r0 + synco + + mov.l STR_L_A,r0 + mov.l STR_L_D,r1 + synco + mov.l r1,@r0 + synco + + mov.l SDR_L_A,r0 + mov.l SDR_L_D,r1 + synco + mov.l r1,@r0 + synco + + nop + nop + nop + nop + + mov.l SCR_L_A,r0 + mov.l SCR_L_D0,r1 + synco + mov.l r1,@r0 + synco + + mov.l SCR_L_A,r0 + mov.l SCR_L_D1,r1 + synco + mov.l r1,@r0 + synco + + nop + nop + nop + + mov.l EMRS_A,r0 + mov.l EMRS_D,r1 + synco + mov.l r1,@r0 + synco + + nop + nop + nop + + mov.l MRS1_A,r0 + mov.l MRS1_D,r1 + synco + mov.l r1,@r0 + synco + + nop + nop + nop + + mov.l SCR_L_A,r0 + mov.l SCR_L_D2,r1 + synco + mov.l r1,@r0 + synco + + nop + nop + nop + + mov.l SCR_L_A,r0 + mov.l SCR_L_D3,r1 + synco + mov.l r1,@r0 + synco + + nop + nop + nop + + mov.l SCR_L_A,r0 + mov.l SCR_L_D4,r1 + synco + mov.l r1,@r0 + synco + + nop + nop + nop + + mov.l MRS2_A,r0 + mov.l MRS2_D,r1 + synco + mov.l r1,@r0 + synco + + nop + nop + nop + + mov.l SCR_L_A,r0 + mov.l SCR_L_D5,r1 + synco + mov.l r1,@r0 + synco + + /* wait 200us */ + mov.l REPEAT0_R1,r3 + mov #0,r2 +repeat2: + add #1,r2 + cmp/hs r3,r2 + bf repeat2 + + synco + + mov.l MIM_L_A,r0 + mov.l MIM_L_D1,r1 + synco + mov.l r1,@r0 + synco + + rts + nop + .align 4 + +RWTCSR_D_1: .word 0xA507 +RWTCSR_D_2: .word 0xA507 +RWTCNT_D: .word 0x5A00 + +BBG_PMMR_A: .long 0xFF800010 +BBG_PMSR1_A: .long 0xFF800014 +BBG_PMSR2_A: .long 0xFF800018 +BBG_PMSR3_A: .long 0xFF80001C +BBG_PMSR4_A: .long 0xFF800020 +BBG_PMSRG_A: .long 0xFF800024 + +BBG_PMMR_D_PMSR1: .long 0xffffbffd +BBG_PMSR1_D: .long 0x00004002 +BBG_PMMR_D_PMSR2: .long 0xfc21a7ff +BBG_PMSR2_D: .long 0x03de5800 +BBG_PMMR_D_PMSR3: .long 0xfffffff8 +BBG_PMSR3_D: .long 0x00000007 +BBG_PMMR_D_PMSR4: .long 0xdffdfff9 +BBG_PMSR4_D: .long 0x20020006 +BBG_PMMR_D_PMSRG: .long 0xffffffff +BBG_PMSRG_D: .long 0x00000000 + +FRQCR_A: .long FRQCR +DLLCSR_A: .long 0xffc40010 +FRQCR_D: .long 0x40233035 +DLLCSR_D: .long 0x00000000 + +/* for DDR-SDRAM */ +MIM_U_A: .long MIM_1 +MIM_L_A: .long MIM_2 +SCR_U_A: .long SCR_1 +SCR_L_A: .long SCR_2 +STR_U_A: .long STR_1 +STR_L_A: .long STR_2 +SDR_U_A: .long SDR_1 +SDR_L_A: .long SDR_2 + +EMRS_A: .long 0xFEC02000 +MRS1_A: .long 0xFEC00B08 +MRS2_A: .long 0xFEC00308 + +MIM_U_D: .long 0x00004000 +MIM_L_D0: .long 0x03e80009 +MIM_L_D1: .long 0x03e80209 +SCR_L_D0: .long 0x3 +SCR_L_D1: .long 0x2 +SCR_L_D2: .long 0x2 +SCR_L_D3: .long 0x4 +SCR_L_D4: .long 0x4 +SCR_L_D5: .long 0x0 +STR_L_D: .long 0x000f0000 +SDR_L_D: .long 0x00000400 +EMRS_D: .long 0x0 +MRS1_D: .long 0x0 +MRS2_D: .long 0x0 + +/* Cache Controller */ +CCR_A: .long CCR +MMUCR_A: .long MMUCR +RWTCNT_A: .long WTCNT + +CCR_D: .long 0x0000090b +CCR_D_2: .long 0x00000103 +MMUCR_D: .long 0x00000004 +MSTPCR0_D: .long 0x00001001 +MSTPCR2_D: .long 0xffffffff + +/* local Bus State Controller */ +MMSELR_A: .long MMSELR +BCR_A: .long BCR +CS0BCR_A: .long CS0BCR +CS1BCR_A: .long CS1BCR +CS2BCR_A: .long CS2BCR +CS4BCR_A: .long CS4BCR +CS5BCR_A: .long CS5BCR +CS6BCR_A: .long CS6BCR +CS0WCR_A: .long CS0WCR +CS1WCR_A: .long CS1WCR +CS2WCR_A: .long CS2WCR +CS4WCR_A: .long CS4WCR +CS5WCR_A: .long CS5WCR +CS6WCR_A: .long CS6WCR +CS5PCR_A: .long CS5PCR +CS6PCR_A: .long CS6PCR + +MMSELR_D: .long 0xA5A50003 +BCR_D: .long 0x00000000 +CS0BCR_D: .long 0x77777770 +CS1BCR_D: .long 0x77777670 +CS2BCR_D: .long 0x77777770 +CS4BCR_D: .long 0x77777770 +CS5BCR_D: .long 0x77777670 +CS6BCR_D: .long 0x77777770 +CS0WCR_D: .long 0x00020006 +CS1WCR_D: .long 0x00232304 +CS2WCR_D: .long 0x7777770F +CS4WCR_D: .long 0x7777770F +CS5WCR_D: .long 0x00101006 +CS6WCR_D: .long 0x77777703 +CS5PCR_D: .long 0x77000000 +CS6PCR_D: .long 0x77000000 + +REPEAT0_R3: .long 0x00002000 +REPEAT0_R1: .long 0x0000200 diff --git a/board/r7780mp/r7780mp.c b/board/r7780mp/r7780mp.c new file mode 100644 index 0000000..1a37711 --- /dev/null +++ b/board/r7780mp/r7780mp.c @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ide.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/pci.h> +#include "r7780mp.h" + +int checkboard(void) +{ +#if defined(CONFIG_R7780MP) + puts("BOARD: Renesas Solutions R7780MP\n"); +#else + puts("BOARD: Renesas Solutions R7780RP\n"); +#endif + return 0; +} + +int board_init(void) +{ + /* SCIF Enable */ + *(vu_short*)PHCR = 0x0000; + + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_memstart = CFG_SDRAM_BASE; + gd->bd->bi_memsize = CFG_SDRAM_SIZE; + printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + +void led_set_state (unsigned short value) +{ + +} + +void ide_set_reset (int idereset) +{ + /* if reset = 1 IDE reset will be asserted */ + if (idereset){ + (*(vu_short *)FPGA_CFCTL) = 0x432; +#if defined(CONFIG_R7780MP) + (*(vu_short *)FPGA_CFPOW) |= 0x01; +#else + (*(vu_short *)FPGA_CFPOW) |= 0x02; +#endif + (*(vu_short *)FPGA_CFCDINTCLR) = 0x01; + } +} + +#if defined(CONFIG_PCI) +static struct pci_controller hose; +void pci_init_board(void) +{ + pci_sh7780_init( &hose ); +} +#endif diff --git a/board/r7780mp/r7780mp.h b/board/r7780mp/r7780mp.h new file mode 100644 index 0000000..476a413 --- /dev/null +++ b/board/r7780mp/r7780mp.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2007 Nobuhiro Iwamatsu + * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> + * + * u-boot/board/r7780mp/r7780mp.h + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BOARD_R7780MP_R7780MP_H_ +#define _BOARD_R7780MP_R7780MP_H_ + +/* R7780MP's FPGA register map */ +#define FPGA_BASE 0xa4000000 +#define FPGA_IRLMSK (FPGA_BASE + 0x00) +#define FPGA_IRLMON (FPGA_BASE + 0x02) +#define FPGA_IRLPRI1 (FPGA_BASE + 0x04) +#define FPGA_IRLPRI2 (FPGA_BASE + 0x06) +#define FPGA_IRLPRI3 (FPGA_BASE + 0x08) +#define FPGA_IRLPRI4 (FPGA_BASE + 0x0A) +#define FPGA_RSTCTL (FPGA_BASE + 0x0C) +#define FPGA_PCIBD (FPGA_BASE + 0x0E) +#define FPGA_PCICD (FPGA_BASE + 0x10) +#define FPGA_EXTGIO (FPGA_BASE + 0x16) +#define FPGA_IVDRMON (FPGA_BASE + 0x18) +#define FPGA_IVDRCR (FPGA_BASE + 0x1A) +#define FPGA_OBLED (FPGA_BASE + 0x1C) +#define FPGA_OBSW (FPGA_BASE + 0x1E) +#define FPGA_TPCTL (FPGA_BASE + 0x100) +#define FPGA_TPDCKCTL (FPGA_BASE + 0x102) +#define FPGA_TPCLR (FPGA_BASE + 0x104) +#define FPGA_TPXPOS (FPGA_BASE + 0x106) +#define FPGA_TPYPOS (FPGA_BASE + 0x108) +#define FPGA_DBSW (FPGA_BASE + 0x200) +#define FPGA_VERSION (FPGA_BASE + 0x700) +#define FPGA_CFCTL (FPGA_BASE + 0x300) +#define FPGA_CFPOW (FPGA_BASE + 0x302) +#define FPGA_CFCDINTCLR (FPGA_BASE + 0x304) +#define FPGA_PMR (FPGA_BASE + 0x900) + +#endif /* _BOARD_R7780RP_R7780RP_H_ */ diff --git a/board/r7780mp/u-boot.lds b/board/r7780mp/u-boot.lds new file mode 100644 index 0000000..e7499e5 --- /dev/null +++ b/board/r7780mp/u-boot.lds @@ -0,0 +1,105 @@ +/* + * Copyrigth (c) 2007,2008 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + Base address of internal SDRAM is 0x0C000000. + Although size of SDRAM can be either 16 or 32 MBytes, + we assume 16 MBytes (ie ignore upper half if the full + 32 MBytes is present). + + NOTE: This address must match with the definition of + TEXT_BASE in config.mk (in this directory). + + */ + . = 0x08000000 + (128*1024*1024) - (256*1024); + + PROVIDE (reloc_dst = .); + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + cpu/sh4/start.o (.text) + . = ALIGN(8192); + common/environment.o (.ppcenv) + . = ALIGN(8192); + common/environment.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(.rodata) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + PROVIDE (__u_boot_cmd_start = .); + .u_boot_cmd : + { + *(.u_boot_cmd) + . = ALIGN(4); + } + PROVIDE (__u_boot_cmd_end = .); + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (_end = .); +} |