diff options
Diffstat (limited to 'board')
31 files changed, 335 insertions, 808 deletions
diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c index df10d6a..9465cea 100644 --- a/board/bachmann/ot1200/ot1200.c +++ b/board/bachmann/ot1200/ot1200.c @@ -169,17 +169,6 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - int board_early_init_f(void) { ccgr_init(); diff --git a/board/barco/platinum/platinum.h b/board/barco/platinum/platinum.h index d3ea8bd..3013ed9 100644 --- a/board/barco/platinum/platinum.h +++ b/board/barco/platinum/platinum.h @@ -75,15 +75,4 @@ static inline void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static inline void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - #endif /* _PLATINUM_H_ */ diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c index 8cd0090..2ed66d3 100644 --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c @@ -955,17 +955,6 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - /* Define a minimal structure so that the part number can be read via SPL */ struct mfgdata { unsigned char tsize; diff --git a/board/congatec/conga-qeval20-qa3-e3845/Kconfig b/board/congatec/conga-qeval20-qa3-e3845/Kconfig index e1fae73..9e44413 100644 --- a/board/congatec/conga-qeval20-qa3-e3845/Kconfig +++ b/board/congatec/conga-qeval20-qa3-e3845/Kconfig @@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SPI_FLASH_STMICRO imply SPI_FLASH_SPANSION imply SPI_FLASH_WINBOND + select SERIAL_RX_BUFFER config PCIE_ECAM_BASE default 0xe0000000 diff --git a/board/dfi/dfi-bt700/Kconfig b/board/dfi/dfi-bt700/Kconfig index 4b6c3fc..f92f50a 100644 --- a/board/dfi/dfi-bt700/Kconfig +++ b/board/dfi/dfi-bt700/Kconfig @@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SPI_FLASH_STMICRO imply SPI_FLASH_SPANSION imply SPI_FLASH_WINBOND + select SERIAL_RX_BUFFER config PCIE_ECAM_BASE default 0xe0000000 diff --git a/board/el/el6x/el6x.c b/board/el/el6x/el6x.c index 6b98b5c..fb128f5 100644 --- a/board/el/el6x/el6x.c +++ b/board/el/el6x/el6x.c @@ -570,17 +570,6 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - /* * This section requires the differentiation between iMX6 Sabre boards, but * for now, it will configure only for the mx6q variant. diff --git a/board/engicam/common/spl.c b/board/engicam/common/spl.c index a8a7cf3..6964c13 100644 --- a/board/engicam/common/spl.c +++ b/board/engicam/common/spl.c @@ -39,6 +39,17 @@ static iomux_v3_cfg_t const uart_pads[] = { #endif }; +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + + return 0; +} +#endif + #ifdef CONFIG_MX6QDL /* * Driving strength: @@ -332,17 +343,6 @@ static void ccgr_init(void) #endif } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - static void spl_dram_init(void) { #ifdef CONFIG_MX6QDL diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c index f8f77f6..15ca029 100644 --- a/board/freescale/mx6sabreauto/mx6sabreauto.c +++ b/board/freescale/mx6sabreauto/mx6sabreauto.c @@ -798,23 +798,6 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - if (is_mx6dqp()) { - /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ - writel(0x77177717, &iomux->gpr[6]); - writel(0x77177717, &iomux->gpr[7]); - } else { - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); - } -} - static int mx6q_dcd_table[] = { 0x020e0798, 0x000C0000, 0x020e0758, 0x00000000, diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 9a562b3..5b50bc8 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -747,23 +747,6 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - if (is_mx6dqp()) { - /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ - writel(0x77177717, &iomux->gpr[6]); - writel(0x77177717, &iomux->gpr[7]); - } else { - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); - } -} - static int mx6q_dcd_table[] = { 0x020e0798, 0x000C0000, 0x020e0758, 0x00000000, diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 9524da7..c2e370b 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -583,17 +583,6 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - /* * called from C runtime startup code (arch/arm/lib/crt0.S:_main) * - we have a stack and a place to store GD, both in SRAM diff --git a/board/isee/igep00x0/MAINTAINERS b/board/isee/igep00x0/MAINTAINERS index 720ef2a..d75d400 100644 --- a/board/isee/igep00x0/MAINTAINERS +++ b/board/isee/igep00x0/MAINTAINERS @@ -3,6 +3,5 @@ M: Enric Balletbo i Serra <eballetbo@gmail.com> S: Maintained F: board/isee/igep00x0/ F: include/configs/omap3_igep00x0.h -F: configs/igep0020_defconfig -F: configs/igep0030_defconfig +F: configs/igep00x0_defconfig F: configs/igep0032_defconfig diff --git a/board/isee/igep00x0/Makefile b/board/isee/igep00x0/Makefile index 68b151c..74594da 100644 --- a/board/isee/igep00x0/Makefile +++ b/board/isee/igep00x0/Makefile @@ -5,4 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := igep00x0.o +ifdef CONFIG_SPL_BUILD +obj-y := spl.o common.o +else +obj-y := igep00x0.o common.o +endif diff --git a/board/isee/igep00x0/common.c b/board/isee/igep00x0/common.c new file mode 100644 index 0000000..e59516f --- /dev/null +++ b/board/isee/igep00x0/common.c @@ -0,0 +1,68 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <twl4030.h> +#include <asm/io.h> +#include <asm/omap_mmc.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <jffs2/load_kernel.h> +#include <linux/mtd/nand.h> +#include "igep00x0.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_DEFAULT(); +} + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + int loops = 100; + + /* find out flash memory type, assume NAND first */ + gpmc_cs0_flash = MTD_DEV_TYPE_NAND; + gpmc_init(); + + /* Issue a RESET and then READID */ + writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); + writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); + while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY) + != NAND_STATUS_READY) { + udelay(1); + if (--loops == 0) { + gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; + gpmc_init(); /* reinitialize for OneNAND */ + break; + } + } + + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +#if defined(CONFIG_MMC) +int board_mmc_init(bd_t *bis) +{ + return omap_mmc_init(0, 0, 0, -1, -1); +} + +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} +#endif diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index a7a7560..5c7f256 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -17,18 +17,14 @@ #include <asm/arch/mmc_host_def.h> #include <asm/arch/mux.h> #include <asm/arch/sys_proto.h> -#include <asm/mach-types.h> #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> -#include <linux/mtd/nand.h> #include <linux/mtd/onenand.h> #include <jffs2/load_kernel.h> #include <mtd_node.h> #include <fdt_support.h> #include "igep00x0.h" -DECLARE_GLOBAL_DATA_PTR; - static const struct ns16550_platdata igep_serial = { .base = OMAP34XX_UART3, .reg_shift = 2, @@ -42,96 +38,41 @@ U_BOOT_DEVICE(igep_uart) = { }; /* - * Routine: board_init - * Description: Early hardware init. + * Routine: get_board_revision + * Description: GPIO_28 and GPIO_129 are used to read board and revision from + * IGEP00x0 boards. First of all, it is necessary to reset USB transceiver from + * IGEP0030 in order to read GPIO_IGEP00X0_BOARD_DETECTION correctly, because + * this functionality is shared by USB HOST. + * Once USB reset is applied, U-boot configures these pins as input pullup to + * detect board and revision: + * IGEP0020-RF = 0b00 + * IGEP0020-RC = 0b01 + * IGEP0030-RG = 0b10 + * IGEP0030-RE = 0b11 */ -int board_init(void) +static int get_board_revision(void) { - int loops = 100; - - /* find out flash memory type, assume NAND first */ - gpmc_cs0_flash = MTD_DEV_TYPE_NAND; - gpmc_init(); + int revision; - /* Issue a RESET and then READID */ - writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); - writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); - while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY) - != NAND_STATUS_READY) { - udelay(1); - if (--loops == 0) { - gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; - gpmc_init(); /* reinitialize for OneNAND */ - break; - } - } + gpio_request(IGEP0030_USB_TRANSCEIVER_RESET, + "igep0030_usb_transceiver_reset"); + gpio_direction_output(IGEP0030_USB_TRANSCEIVER_RESET, 0); - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + gpio_request(GPIO_IGEP00X0_BOARD_DETECTION, "igep00x0_board_detection"); + gpio_direction_input(GPIO_IGEP00X0_BOARD_DETECTION); + revision = 2 * gpio_get_value(GPIO_IGEP00X0_BOARD_DETECTION); + gpio_free(GPIO_IGEP00X0_BOARD_DETECTION); -#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE) - status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON); -#endif - - return 0; -} - -#ifdef CONFIG_SPL_BUILD -/* - * Routine: get_board_mem_timings - * Description: If we use SPL then there is no x-loader nor config header - * so we have to setup the DDR timings ourself on both banks. - */ -void get_board_mem_timings(struct board_sdrc_timings *timings) -{ - int mfr, id, err = identify_nand_chip(&mfr, &id); - - timings->mr = MICRON_V_MR_165; - if (!err) { - switch (mfr) { - case NAND_MFR_HYNIX: - timings->mcfg = HYNIX_V_MCFG_200(256 << 20); - timings->ctrla = HYNIX_V_ACTIMA_200; - timings->ctrlb = HYNIX_V_ACTIMB_200; - break; - case NAND_MFR_MICRON: - timings->mcfg = MICRON_V_MCFG_200(256 << 20); - timings->ctrla = MICRON_V_ACTIMA_200; - timings->ctrlb = MICRON_V_ACTIMB_200; - break; - default: - /* Should not happen... */ - break; - } - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; - gpmc_cs0_flash = MTD_DEV_TYPE_NAND; - } else { - if (get_cpu_family() == CPU_OMAP34XX) { - timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); - timings->ctrla = NUMONYX_V_ACTIMA_165; - timings->ctrlb = NUMONYX_V_ACTIMB_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; - } else { - timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); - timings->ctrla = NUMONYX_V_ACTIMA_200; - timings->ctrlb = NUMONYX_V_ACTIMB_200; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; - } - gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; - } -} + gpio_request(GPIO_IGEP00X0_REVISION_DETECTION, + "igep00x0_revision_detection"); + gpio_direction_input(GPIO_IGEP00X0_REVISION_DETECTION); + revision = revision + gpio_get_value(GPIO_IGEP00X0_REVISION_DETECTION); + gpio_free(GPIO_IGEP00X0_REVISION_DETECTION); -#ifdef CONFIG_SPL_OS_BOOT -int spl_start_uboot(void) -{ - /* break into full u-boot on 'c' */ - if (serial_tstc() && serial_getc() == 'c') - return 1; + gpio_free(IGEP0030_USB_TRANSCEIVER_RESET); - return 0; + return revision; } -#endif -#endif int onenand_board_init(struct mtd_info *mtd) { @@ -199,20 +140,6 @@ int board_eth_init(bd_t *bis) static inline void setup_net_chip(void) {} #endif -#if defined(CONFIG_MMC) -int board_mmc_init(bd_t *bis) -{ - return omap_mmc_init(0, 0, 0, -1, -1); -} -#endif - -#if defined(CONFIG_MMC) -void board_mmc_power_init(void) -{ - twl4030_power_mmc_init(0); -} -#endif - #ifdef CONFIG_OF_BOARD_SETUP static int ft_enable_by_compatible(void *blob, char *compat, int enable) { @@ -247,31 +174,69 @@ int ft_board_setup(void *blob, bd_t *bd) } #endif -void set_fdt(void) +void set_led(void) { - switch (gd->bd->bi_arch_number) { - case MACH_TYPE_IGEP0020: - env_set("fdtfile", "omap3-igep0020.dtb"); + switch (get_board_revision()) { + case 0: + case 1: + gpio_request(IGEP0020_GPIO_LED, "igep0020_gpio_led"); + gpio_direction_output(IGEP0020_GPIO_LED, 1); + break; + case 2: + case 3: + gpio_request(IGEP0030_GPIO_LED, "igep0030_gpio_led"); + gpio_direction_output(IGEP0030_GPIO_LED, 0); break; - case MACH_TYPE_IGEP0030: - env_set("fdtfile", "omap3-igep0030.dtb"); + default: + /* Should not happen... */ break; } } +void set_boardname(void) +{ + char rev[5] = { 'F','C','G','E', }; + int i = get_board_revision(); + + rev[i+1] = 0; + env_set("board_rev", rev + i); + env_set("board_name", i < 2 ? "igep0020" : "igep0030"); +} + /* * Routine: misc_init_r * Description: Configure board specific parts */ int misc_init_r(void) { + t2_t *t2_base = (t2_t *)T2_BASE; + u32 pbias_lite; + twl4030_power_init(); + /* set VSIM to 1.8V */ + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VSIM_DEDICATED, + TWL4030_PM_RECEIVER_VSIM_VSEL_18, + TWL4030_PM_RECEIVER_VSIM_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_P1); + + /* set up dual-voltage GPIOs to 1.8V */ + pbias_lite = readl(&t2_base->pbias_lite); + pbias_lite &= ~PBIASLITEVMODE1; + pbias_lite |= PBIASLITEPWRDNZ1; + writel(pbias_lite, &t2_base->pbias_lite); + if (get_cpu_family() == CPU_OMAP36XX) + writel(readl(OMAP34XX_CTRL_WKUP_CTRL) | + OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ, + OMAP34XX_CTRL_WKUP_CTRL); + setup_net_chip(); omap_die_id_display(); - set_fdt(); + set_led(); + + set_boardname(); return 0; } @@ -292,22 +257,3 @@ void board_mtdparts_default(const char **mtdids, const char **mtdparts) *mtdparts = parts; } } - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs(void) -{ - MUX_DEFAULT(); - -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) - MUX_IGEP0020(); -#endif - -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) - MUX_IGEP0030(); -#endif -} diff --git a/board/isee/igep00x0/igep00x0.h b/board/isee/igep00x0/igep00x0.h index 5698efa..1cbe7c9 100644 --- a/board/isee/igep00x0/igep00x0.h +++ b/board/isee/igep00x0/igep00x0.h @@ -103,6 +103,8 @@ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */\ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\ @@ -117,13 +119,10 @@ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\ MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /* GPIO_28 */\ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M4)) /* GPIO_54 */\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64 */\ + MUX_VAL(CP(GPIO129), (IEN | PTU | EN | M4)) /* GPIO_129 */\ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */ #endif - -#define MUX_IGEP0020() \ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64-ETH_NRST */\ - -#define MUX_IGEP0030() \ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */ diff --git a/board/isee/igep00x0/spl.c b/board/isee/igep00x0/spl.c new file mode 100644 index 0000000..eb705cb --- /dev/null +++ b/board/isee/igep00x0/spl.c @@ -0,0 +1,64 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/sys_proto.h> +#include <jffs2/load_kernel.h> +#include <linux/mtd/nand.h> +#include "igep00x0.h" + +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on both banks. + */ +void get_board_mem_timings(struct board_sdrc_timings *timings) +{ + int mfr, id, err = identify_nand_chip(&mfr, &id); + + timings->mr = MICRON_V_MR_165; + if (!err) { + switch (mfr) { + case NAND_MFR_HYNIX: + timings->mcfg = HYNIX_V_MCFG_200(256 << 20); + timings->ctrla = HYNIX_V_ACTIMA_200; + timings->ctrlb = HYNIX_V_ACTIMB_200; + break; + case NAND_MFR_MICRON: + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + break; + default: + /* Should not happen... */ + break; + } + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + gpmc_cs0_flash = MTD_DEV_TYPE_NAND; + } else { + if (get_cpu_family() == CPU_OMAP34XX) { + timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_165; + timings->ctrlb = NUMONYX_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } else { + timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_200; + timings->ctrlb = NUMONYX_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + } + gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; + } +} + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + + return 0; +} +#endif diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c index 3645b75..512f06d 100644 --- a/board/kosagi/novena/novena_spl.c +++ b/board/kosagi/novena/novena_spl.c @@ -550,17 +550,6 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - /* * called from C runtime startup code (arch/arm/lib/crt0.S:_main) * - we have a stack and a place to store GD, both in SRAM diff --git a/board/liebherr/mccmon6/spl.c b/board/liebherr/mccmon6/spl.c index 15844ef..a2f804d 100644 --- a/board/liebherr/mccmon6/spl.c +++ b/board/liebherr/mccmon6/spl.c @@ -260,17 +260,6 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - static void spl_dram_init(void) { if (is_cpu_type(MXC_CPU_MX6SOLO)) { diff --git a/board/phytec/pcm058/pcm058.c b/board/phytec/pcm058/pcm058.c index 4257fbc..1538158 100644 --- a/board/phytec/pcm058/pcm058.c +++ b/board/phytec/pcm058/pcm058.c @@ -487,18 +487,6 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - - static void spl_dram_init(void) { struct mx6_ddr_sysinfo sysinfo = { diff --git a/board/phytec/pfla02/Kconfig b/board/phytec/pfla02/Kconfig index 142a122..f4da68b 100644 --- a/board/phytec/pfla02/Kconfig +++ b/board/phytec/pfla02/Kconfig @@ -9,4 +9,10 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "pfla02" +config SPL_DRAM_1_BANK + bool "DRAM on just one bank" + help + activate, if the module has just one bank + of RAM + endif diff --git a/board/phytec/pfla02/pfla02.c b/board/phytec/pfla02/pfla02.c index 8d2ce63..136f1d5 100644 --- a/board/phytec/pfla02/pfla02.c +++ b/board/phytec/pfla02/pfla02.c @@ -485,9 +485,9 @@ static const struct mx6_mmdc_calibration mx6_mmcd_calib = { /* Index in RAM Chip array */ enum { - RAM_1GB, - RAM_2GB, - RAM_4GB + RAM_MT64K, + RAM_MT128K, + RAM_MT256K }; static struct mx6_ddr3_cfg mt41k_xx[] = { @@ -550,42 +550,11 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static void gpr_init(void) +static void spl_dram_init(struct mx6_ddr_sysinfo *sysinfo, + struct mx6_ddr3_cfg *mem_ddr) { - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - -static void spl_dram_init(struct mx6_ddr3_cfg *mem_ddr) -{ - struct mx6_ddr_sysinfo sysinfo = { - /* width of data bus:0=16,1=32,2=64 */ - .dsize = 2, - /* config for full 4GB range so that get_mem_size() works */ - .cs_density = 32, /* 32Gb per CS */ - /* single chip select */ - .ncs = 2, - .cs1_mirror = 0, - .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ - .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ - .walat = 1, /* Write additional latency */ - .ralat = 5, /* Read additional latency */ - .mif3_mode = 3, /* Command prediction working mode */ - .bi_on = 1, /* Bank interleaving enabled */ - .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ - .ddr_type = DDR_TYPE_DDR3, - .refsel = 1, /* Refresh cycles at 32KHz */ - .refr = 7, /* 8 refresh commands per refresh cycle */ - }; - mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); - mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, mem_ddr); + mx6_dram_cfg(sysinfo, &mx6_mmcd_calib, mem_ddr); } int board_mmc_init(bd_t *bis) @@ -627,10 +596,12 @@ void board_boot_order(u32 *spl_boot_list) * Function checks for mirrors in the first CS */ #define RAM_TEST_PATTERN 0xaa5555aa -static unsigned int pfla02_detect_ramsize(void) +#define MIN_BANK_SIZE (512 * 1024 * 1024) + +static unsigned int pfla02_detect_chiptype(void) { u32 *p, *p1; - unsigned int offset = 512 * 1024 * 1024; + unsigned int offset = MIN_BANK_SIZE; int i; for (i = 0; i < 2; i++) { @@ -649,12 +620,38 @@ static unsigned int pfla02_detect_ramsize(void) if (*p == *p1) return i; } - return RAM_4GB; + return RAM_MT256K; } void board_init_f(ulong dummy) { unsigned int ramchip; + + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = 2, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 512 MB */ + /* single chip select */ +#if IS_ENABLED(CONFIG_SPL_DRAM_1_BANK) + .ncs = 1, +#else + .ncs = 2, +#endif + .cs1_mirror = 1, + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ + .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ + }; + #ifdef CONFIG_CMD_NAND /* Enable NAND */ setup_gpmi_nand(); @@ -682,10 +679,23 @@ void board_init_f(ulong dummy) setup_gpios(); /* DDR initialization */ - spl_dram_init(&mt41k_xx[RAM_4GB]); - ramchip = pfla02_detect_ramsize(); - if (ramchip != RAM_4GB) - spl_dram_init(&mt41k_xx[ramchip]); + spl_dram_init(&sysinfo, &mt41k_xx[RAM_MT256K]); + ramchip = pfla02_detect_chiptype(); + debug("Detected chip %d\n", ramchip); +#if !IS_ENABLED(CONFIG_SPL_DRAM_1_BANK) + switch (ramchip) { + case RAM_MT64K: + sysinfo.cs_density = 6; + break; + case RAM_MT128K: + sysinfo.cs_density = 10; + break; + case RAM_MT256K: + sysinfo.cs_density = 18; + break; + } +#endif + spl_dram_init(&sysinfo, &mt41k_xx[ramchip]); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index 7e59fb2..986abc5 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -581,17 +581,6 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - static void spl_dram_init(int width) { struct mx6_ddr_sysinfo sysinfo = { diff --git a/board/spear/common/Makefile b/board/spear/common/Makefile deleted file mode 100644 index b0ba320..0000000 --- a/board/spear/common/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_SPL_BUILD -# necessary to create built-in.o -obj- := __dummy__.o -else -obj-y := spr_misc.o -obj-y += spr_lowlevel_init.o -endif diff --git a/board/spear/common/spr_lowlevel_init.S b/board/spear/common/spr_lowlevel_init.S deleted file mode 100644 index 6494883..0000000 --- a/board/spear/common/spr_lowlevel_init.S +++ /dev/null @@ -1,174 +0,0 @@ -/* - * (C) Copyright 2006 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> - -/* - * platform specific initializations are already done in Xloader - * Initializations already done include - * DDR, PLLs, IP's clock enable and reset release etc - */ -.globl lowlevel_init -lowlevel_init: - mov pc, lr - -/* void setfreq(unsigned int device, unsigned int frequency) */ -.global setfreq -setfreq: - stmfd sp!,{r14} - stmfd sp!,{r0-r12} - - mov r8,sp - ldr sp,SRAM_STACK_V - - /* Saving the function arguements for later use */ - mov r4,r0 - mov r5,r1 - - /* Putting DDR into self refresh */ - ldr r0,DDR_07_V - ldr r1,[r0] - ldr r2,DDR_ACTIVE_V - bic r1, r1, r2 - str r1,[r0] - ldr r0,DDR_57_V - ldr r1,[r0] - ldr r2,CYCLES_MASK_V - bic r1, r1, r2 - ldr r2,REFRESH_CYCLES_V - orr r1, r1, r2, lsl #16 - str r1,[r0] - ldr r0,DDR_07_V - ldr r1,[r0] - ldr r2,SREFRESH_MASK_V - orr r1, r1, r2 - str r1,[r0] - - /* flush pipeline */ - b flush - .align 5 -flush: - /* Delay to ensure self refresh mode */ - ldr r0,SREFRESH_DELAY_V -delay: - sub r0,r0,#1 - cmp r0,#0 - bne delay - - /* Putting system in slow mode */ - ldr r0,SCCTRL_V - mov r1,#2 - str r1,[r0] - - /* Changing PLL(1/2) frequency */ - mov r0,r4 - mov r1,r5 - - cmp r4,#0 - beq pll1_freq - - /* Change PLL2 (DDR frequency) */ - ldr r6,PLL2_FREQ_V - ldr r7,PLL2_CNTL_V - b pll2_freq - -pll1_freq: - /* Change PLL1 (CPU frequency) */ - ldr r6,PLL1_FREQ_V - ldr r7,PLL1_CNTL_V - -pll2_freq: - mov r0,r6 - ldr r1,[r0] - ldr r2,PLLFREQ_MASK_V - bic r1,r1,r2 - mov r2,r5,lsr#1 - orr r1,r1,r2,lsl#24 - str r1,[r0] - - mov r0,r7 - ldr r1,P1C0A_V - str r1,[r0] - ldr r1,P1C0E_V - str r1,[r0] - ldr r1,P1C06_V - str r1,[r0] - ldr r1,P1C0E_V - str r1,[r0] - -lock: - ldr r1,[r0] - and r1,r1,#1 - cmp r1,#0 - beq lock - - /* Putting system back to normal mode */ - ldr r0,SCCTRL_V - mov r1,#4 - str r1,[r0] - - /* Putting DDR back to normal */ - ldr r0,DDR_07_V - ldr r1,[R0] - ldr r2,SREFRESH_MASK_V - bic r1, r1, r2 - str r1,[r0] - ldr r2,DDR_ACTIVE_V - orr r1, r1, r2 - str r1,[r0] - - /* Delay to ensure self refresh mode */ - ldr r0,SREFRESH_DELAY_V -1: - sub r0,r0,#1 - cmp r0,#0 - bne 1b - - mov sp,r8 - /* Resuming back to code */ - ldmia sp!,{r0-r12} - ldmia sp!,{pc} - -SCCTRL_V: - .word 0xfca00000 -PLL1_FREQ_V: - .word 0xfca8000C -PLL1_CNTL_V: - .word 0xfca80008 -PLL2_FREQ_V: - .word 0xfca80018 -PLL2_CNTL_V: - .word 0xfca80014 -PLLFREQ_MASK_V: - .word 0xff000000 -P1C0A_V: - .word 0x1C0A -P1C0E_V: - .word 0x1C0E -P1C06_V: - .word 0x1C06 - -SREFRESH_DELAY_V: - .word 0x9999 -SRAM_STACK_V: - .word 0xD2800600 -DDR_07_V: - .word 0xfc60001c -DDR_ACTIVE_V: - .word 0x01000000 -DDR_57_V: - .word 0xfc6000e4 -CYCLES_MASK_V: - .word 0xffff0000 -REFRESH_CYCLES_V: - .word 0xf0f0 -SREFRESH_MASK_V: - .word 0x00010000 - -.global setfreq_sz -setfreq_sz: - .word setfreq_sz - setfreq diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c deleted file mode 100644 index a02304f..0000000 --- a/board/spear/common/spr_misc.c +++ /dev/null @@ -1,249 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <i2c.h> -#include <net.h> -#include <linux/mtd/st_smi.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/arch/spr_emi.h> -#include <asm/arch/spr_defs.h> - -#define CPU 0 -#define DDR 1 -#define SRAM_REL 0xD2801000 - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CMD_NET) -static int i2c_read_mac(uchar *buffer); -#endif - -int dram_init(void) -{ - /* Store complete RAM size and return */ - gd->ram_size = get_ram_size(PHYS_SDRAM_1, PHYS_SDRAM_1_MAXSIZE); - - return 0; -} - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = gd->ram_size; - - return 0; -} - -int board_early_init_f() -{ -#if defined(CONFIG_ST_SMI) - smi_init(); -#endif - return 0; -} -int misc_init_r(void) -{ -#if defined(CONFIG_CMD_NET) - uchar mac_id[6]; - - if (!eth_env_get_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id)) - eth_env_set_enetaddr("ethaddr", mac_id); -#endif - env_set("verify", "n"); - -#if defined(CONFIG_SPEAR_USBTTY) - env_set("stdin", "usbtty"); - env_set("stdout", "usbtty"); - env_set("stderr", "usbtty"); - -#ifndef CONFIG_SYS_NO_DCACHE - dcache_enable(); -#endif -#endif - return 0; -} - -#ifdef CONFIG_SPEAR_EMI -struct cust_emi_para { - unsigned int tap; - unsigned int tsdp; - unsigned int tdpw; - unsigned int tdpr; - unsigned int tdcs; -}; - -/* EMI timing setting of m28w640hc of linux kernel */ -const struct cust_emi_para emi_timing_m28w640hc = { - .tap = 0x10, - .tsdp = 0x05, - .tdpw = 0x0a, - .tdpr = 0x0a, - .tdcs = 0x05, -}; - -/* EMI timing setting of bootrom */ -const struct cust_emi_para emi_timing_bootrom = { - .tap = 0xf, - .tsdp = 0x0, - .tdpw = 0xff, - .tdpr = 0x111, - .tdcs = 0x02, -}; - -void spear_emi_init(void) -{ - const struct cust_emi_para *p = &emi_timing_m28w640hc; - struct emi_regs *emi_regs_p = (struct emi_regs *)CONFIG_SPEAR_EMIBASE; - unsigned int cs; - unsigned int val, tmp; - - val = readl(CONFIG_SPEAR_RASBASE); - - if (val & EMI_ACKMSK) - tmp = 0x3f; - else - tmp = 0x0; - - writel(tmp, &emi_regs_p->ack); - - for (cs = 0; cs < CONFIG_SYS_MAX_FLASH_BANKS; cs++) { - writel(p->tap, &emi_regs_p->bank_regs[cs].tap); - writel(p->tsdp, &emi_regs_p->bank_regs[cs].tsdp); - writel(p->tdpw, &emi_regs_p->bank_regs[cs].tdpw); - writel(p->tdpr, &emi_regs_p->bank_regs[cs].tdpr); - writel(p->tdcs, &emi_regs_p->bank_regs[cs].tdcs); - writel(EMI_CNTL_ENBBYTERW | ((val & 0x18) >> 3), - &emi_regs_p->bank_regs[cs].control); - } -} -#endif - -int spear_board_init(ulong mach_type) -{ - gd->bd->bi_arch_number = mach_type; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR; - -#ifdef CONFIG_SPEAR_EMI - spear_emi_init(); -#endif - return 0; -} - -#if defined(CONFIG_CMD_NET) -static int i2c_read_mac(uchar *buffer) -{ - u8 buf[2]; - - i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN); - - /* Check if mac in i2c memory is valid */ - if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) { - /* Valid mac address is saved in i2c eeprom */ - i2c_read(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, buffer, MAC_LEN); - return 0; - } - - return -1; -} - -static int write_mac(uchar *mac) -{ - u8 buf[2]; - - buf[0] = (u8)MAGIC_BYTE0; - buf[1] = (u8)MAGIC_BYTE1; - i2c_write(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN); - - buf[0] = (u8)~MAGIC_BYTE0; - buf[1] = (u8)~MAGIC_BYTE1; - - i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN); - - /* check if valid MAC address is saved in I2C EEPROM or not? */ - if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) { - i2c_write(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, mac, MAC_LEN); - puts("I2C EEPROM written with mac address \n"); - return 0; - } - - puts("I2C EEPROM writing failed\n"); - return -1; -} -#endif - -int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - void (*sram_setfreq) (unsigned int, unsigned int); - unsigned int frequency; -#if defined(CONFIG_CMD_NET) - unsigned char mac[6]; -#endif - - if ((argc > 3) || (argc < 2)) - return cmd_usage(cmdtp); - - if ((!strcmp(argv[1], "cpufreq")) || (!strcmp(argv[1], "ddrfreq"))) { - - frequency = simple_strtoul(argv[2], NULL, 0); - - if (frequency > 333) { - printf("Frequency is limited to 333MHz\n"); - return 1; - } - - sram_setfreq = memcpy((void *)SRAM_REL, setfreq, setfreq_sz); - - if (!strcmp(argv[1], "cpufreq")) { - sram_setfreq(CPU, frequency); - printf("CPU frequency changed to %u\n", frequency); - } else { - sram_setfreq(DDR, frequency); - printf("DDR frequency changed to %u\n", frequency); - } - - return 0; - -#if defined(CONFIG_CMD_NET) - } else if (!strcmp(argv[1], "ethaddr")) { - - u32 reg; - char *e, *s = argv[2]; - for (reg = 0; reg < 6; ++reg) { - mac[reg] = s ? simple_strtoul(s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - write_mac(mac); - - return 0; -#endif - } else if (!strcmp(argv[1], "print")) { -#if defined(CONFIG_CMD_NET) - if (!i2c_read_mac(mac)) { - printf("Ethaddr (from i2c mem) = %pM\n", mac); - } else { - printf("Ethaddr (from i2c mem) = Not set\n"); - } -#endif - return 0; - } - - return cmd_usage(cmdtp); -} - -U_BOOT_CMD(chip_config, 3, 1, do_chip_config, - "configure chip", - "chip_config cpufreq/ddrfreq frequency\n" -#if defined(CONFIG_CMD_NET) - "chip_config ethaddr XX:XX:XX:XX:XX:XX\n" -#endif - "chip_config print"); diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile index f4411f0..526cb72 100644 --- a/board/sunxi/Makefile +++ b/board/sunxi/Makefile @@ -9,7 +9,7 @@ # SPDX-License-Identifier: GPL-2.0+ # obj-y += board.o -obj-$(CONFIG_SUNXI_GMAC) += gmac.o +obj-$(CONFIG_SUN7I_GMAC) += gmac.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_SUNXI_AHCI) += ahci.o endif diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index 6bf57f9..1f0433d 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -122,6 +122,17 @@ int board_init(void) return 0; } +#if defined(CONFIG_SPL_OS_BOOT) +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + + return 0; +} +#endif /* CONFIG_SPL_OS_BOOT */ + #if defined(CONFIG_SPL_BUILD) /* * Routine: get_board_mem_timings @@ -323,7 +334,14 @@ void board_mmc_power_init(void) } #endif /* CONFIG_MMC */ -#if defined(CONFIG_USB_EHCI_HCD) +#if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD) +/* Call usb_stop() before starting the kernel */ +void show_boot_progress(int val) +{ + if (val == BOOTSTAGE_ID_RUN_OS) + usb_stop(); +} + static struct omap_usbhs_board_data usbhs_bdata = { .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index 7a3e493..ebc6c12 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -29,6 +29,7 @@ #include <dm/platform_data/serial_mxc.h> #include <dm/platdata.h> #include <fsl_esdhc.h> +#include <g_dnl.h> #include <i2c.h> #include <imx_thermal.h> #include <linux/errno.h> @@ -1159,17 +1160,6 @@ static void ccgr_init(void) writel(0x000000FB, &ccm->ccosr); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - static void ddr_init(int *table, int size) { int i; @@ -1234,6 +1224,18 @@ void reset_cpu(ulong addr) { } +#ifdef CONFIG_SPL_USB_GADGET_SUPPORT +int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) +{ + unsigned short usb_pid; + + usb_pid = TORADEX_USB_PRODUCT_NUM_OFFSET + 0xfff; + put_unaligned(usb_pid, &dev->idProduct); + + return 0; +} +#endif + #endif static struct mxc_serial_platdata mxc_serial_plat = { diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index dbcd233..669d912 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -28,6 +28,7 @@ #include <dm/platform_data/serial_mxc.h> #include <dm/platdata.h> #include <fsl_esdhc.h> +#include <g_dnl.h> #include <i2c.h> #include <imx_thermal.h> #include <linux/errno.h> @@ -1036,17 +1037,6 @@ static void ccgr_init(void) writel(0x000000FB, &ccm->ccosr); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - static void ddr_init(int *table, int size) { int i; @@ -1118,6 +1108,18 @@ void reset_cpu(ulong addr) { } +#ifdef CONFIG_SPL_USB_GADGET_SUPPORT +int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) +{ + unsigned short usb_pid; + + usb_pid = TORADEX_USB_PRODUCT_NUM_OFFSET + 0xfff; + put_unaligned(usb_pid, &dev->idProduct); + + return 0; +} +#endif + #endif static struct mxc_serial_platdata mxc_serial_plat = { diff --git a/board/udoo/udoo_spl.c b/board/udoo/udoo_spl.c index e83e7c3..3645969 100644 --- a/board/udoo/udoo_spl.c +++ b/board/udoo/udoo_spl.c @@ -211,17 +211,6 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000FF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - static void spl_dram_init(void) { if (is_cpu_type(MXC_CPU_MX6DL)) { diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c index 47082a8..99a0286 100644 --- a/board/wandboard/spl.c +++ b/board/wandboard/spl.c @@ -266,17 +266,6 @@ static void ccgr_init(void) writel(0x000003FF, &ccm->CCGR6); } -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - static void spl_dram_init(void) { if (is_cpu_type(MXC_CPU_MX6SOLO)) { |