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-rw-r--r--board/icecube/icecube.c11
-rw-r--r--board/icu862/u-boot.lds5
-rw-r--r--board/rmu/rmu.c19
3 files changed, 22 insertions, 13 deletions
diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c
index 396ad2a..f75e675 100644
--- a/board/icecube/icecube.c
+++ b/board/icecube/icecube.c
@@ -25,6 +25,7 @@
#include <mpc5xxx.h>
#include <pci.h>
+#ifndef CFG_RAMBOOT
static long int dram_size(long int *base, long int maxsize)
{
volatile long int *addr;
@@ -86,11 +87,14 @@ static void sdram_start (int hi_addr)
/* normal operation */
*(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000 | hi_addr_bit;
}
+#endif
long int initdram (int board_type)
{
- ulong test1, test2, dramsize = 0;
+ ulong dramsize = 0;
#ifndef CFG_RAMBOOT
+ ulong test1, test2;
+
/* configure SDRAM start/end */
#if defined(CONFIG_MPC5200)
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
@@ -133,8 +137,11 @@ long int initdram (int board_type)
#else
#ifdef CONFIG_MGT5100
*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
+ dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
+#else
+ dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
#endif
-#endif
+#endif /* CFG_RAMBOOT */
/* return total ram size */
return dramsize;
}
diff --git a/board/icu862/u-boot.lds b/board/icu862/u-boot.lds
index 496c598..84e9cbf 100644
--- a/board/icu862/u-boot.lds
+++ b/board/icu862/u-boot.lds
@@ -136,11 +136,6 @@ SECTIONS
*(.bss)
*(COMMON)
}
- . = ALIGN(256 * 1024);
- .ppcenv :
- {
- common/environment.o (.ppcenv)
- }
_end = . ;
PROVIDE (end = .);
}
diff --git a/board/rmu/rmu.c b/board/rmu/rmu.c
index c9925d0..331fb98 100644
--- a/board/rmu/rmu.c
+++ b/board/rmu/rmu.c
@@ -96,7 +96,7 @@ long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size10 ;
+ long int size9 ;
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
@@ -109,7 +109,7 @@ long int initdram (int board_type)
memctl->memc_or1 = CFG_OR1_PRELIM;
memctl->memc_br1 = CFG_BR1_PRELIM;
- memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
+ memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
udelay(200);
@@ -122,13 +122,20 @@ long int initdram (int board_type)
udelay (1000);
- /* Check Bank 0 Memory Size
- * try 10 column mode
+ /* Check Bank 0 Memory Size,
+ * 9 column mode
*/
- size10 = dram_size (CFG_MAMR_10COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE) ;
+ size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE) ;
- return (size10);
+ /*
+ * Final mapping:
+ */
+
+ memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+ udelay (1000);
+
+ return (size9);
}
/* ------------------------------------------------------------------------- */