summaryrefslogtreecommitdiff
path: root/board
diff options
context:
space:
mode:
Diffstat (limited to 'board')
-rw-r--r--board/freescale/common/vid.c174
-rw-r--r--board/freescale/ls1012afrdm/ls1012afrdm.c34
-rw-r--r--board/freescale/ls1012aqds/ls1012aqds.c34
-rw-r--r--board/freescale/ls1012ardb/ls1012ardb.c34
-rw-r--r--board/freescale/ls1043aqds/ddr.c29
-rw-r--r--board/freescale/ls1043aqds/ls1043aqds.c5
-rw-r--r--board/freescale/ls1043ardb/ddr.c29
-rw-r--r--board/freescale/ls1043ardb/ls1043ardb.c7
-rw-r--r--board/freescale/ls1046aqds/ddr.c29
-rw-r--r--board/freescale/ls1046aqds/ls1046aqds.c5
-rw-r--r--board/freescale/ls1046ardb/ddr.c29
-rw-r--r--board/freescale/ls1046ardb/ls1046ardb.c7
-rw-r--r--board/freescale/ls2080a/ddr.c55
-rw-r--r--board/freescale/ls2080a/ls2080a.c17
-rw-r--r--board/freescale/ls2080aqds/ddr.c55
-rw-r--r--board/freescale/ls2080aqds/ls2080aqds.c26
-rw-r--r--board/freescale/ls2080ardb/ddr.c55
-rw-r--r--board/freescale/ls2080ardb/ls2080ardb.c26
-rw-r--r--board/st/stm32f746-disco/stm32f746-disco.c111
19 files changed, 228 insertions, 533 deletions
diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index 1a50304..9b65c13 100644
--- a/board/freescale/common/vid.c
+++ b/board/freescale/common/vid.c
@@ -284,10 +284,170 @@ static int set_voltage(int i2caddress, int vdd)
return vdd_last;
}
+#ifdef CONFIG_FSL_LSCH3
int adjust_vdd(ulong vdd_override)
{
int re_enable = disable_interrupts();
-#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 fusesr;
+ u8 vid, buf;
+ int vdd_target, vdd_current, vdd_last;
+ int ret, i2caddress;
+ unsigned long vdd_string_override;
+ char *vdd_string;
+ static const uint16_t vdd[32] = {
+ 10500,
+ 0, /* reserved */
+ 9750,
+ 0, /* reserved */
+ 9500,
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 10000, /* 1.0000V */
+ 0, /* reserved */
+ 10250,
+ 0, /* reserved */
+ 10500,
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ };
+ struct vdd_drive {
+ u8 vid;
+ unsigned voltage;
+ };
+
+ ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
+ if (ret) {
+ debug("VID: I2C failed to switch channel\n");
+ ret = -1;
+ goto exit;
+ }
+ ret = find_ir_chip_on_i2c();
+ if (ret < 0) {
+ printf("VID: Could not find voltage regulator on I2C.\n");
+ ret = -1;
+ goto exit;
+ } else {
+ i2caddress = ret;
+ debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
+ }
+
+ /* check IR chip work on Intel mode*/
+ ret = i2c_read(i2caddress,
+ IR36021_INTEL_MODE_OOFSET,
+ 1, (void *)&buf, 1);
+ if (ret) {
+ printf("VID: failed to read IR chip mode.\n");
+ ret = -1;
+ goto exit;
+ }
+ if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) {
+ printf("VID: IR Chip is not used in Intel mode.\n");
+ ret = -1;
+ goto exit;
+ }
+
+ /* get the voltage ID from fuse status register */
+ fusesr = in_le32(&gur->dcfg_fusesr);
+ vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
+ FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
+ if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
+ vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
+ FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
+ }
+ vdd_target = vdd[vid];
+
+ /* check override variable for overriding VDD */
+ vdd_string = getenv(CONFIG_VID_FLS_ENV);
+ if (vdd_override == 0 && vdd_string &&
+ !strict_strtoul(vdd_string, 10, &vdd_string_override))
+ vdd_override = vdd_string_override;
+
+ if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) {
+ vdd_target = vdd_override * 10; /* convert to 1/10 mV */
+ debug("VDD override is %lu\n", vdd_override);
+ } else if (vdd_override != 0) {
+ printf("Invalid value.\n");
+ }
+
+ /* divide and round up by 10 to get a value in mV */
+ vdd_target = DIV_ROUND_UP(vdd_target, 10);
+ if (vdd_target == 0) {
+ debug("VID: VID not used\n");
+ ret = 0;
+ goto exit;
+ } else if (vdd_target < VDD_MV_MIN || vdd_target > VDD_MV_MAX) {
+ /* Check vdd_target is in valid range */
+ printf("VID: Target VID %d mV is not in range.\n",
+ vdd_target);
+ ret = -1;
+ goto exit;
+ } else {
+ debug("VID: vid = %d mV\n", vdd_target);
+ }
+
+ /*
+ * Read voltage monitor to check real voltage.
+ */
+ vdd_last = read_voltage(i2caddress);
+ if (vdd_last < 0) {
+ printf("VID: Couldn't read sensor abort VID adjustment\n");
+ ret = -1;
+ goto exit;
+ }
+ vdd_current = vdd_last;
+ debug("VID: Core voltage is currently at %d mV\n", vdd_last);
+ /*
+ * Adjust voltage to at or one step above target.
+ * As measurements are less precise than setting the values
+ * we may run through dummy steps that cancel each other
+ * when stepping up and then down.
+ */
+ while (vdd_last > 0 &&
+ vdd_last < vdd_target) {
+ vdd_current += IR_VDD_STEP_UP;
+ vdd_last = set_voltage(i2caddress, vdd_current);
+ }
+ while (vdd_last > 0 &&
+ vdd_last > vdd_target + (IR_VDD_STEP_DOWN - 1)) {
+ vdd_current -= IR_VDD_STEP_DOWN;
+ vdd_last = set_voltage(i2caddress, vdd_current);
+ }
+
+ if (vdd_last > 0)
+ printf("VID: Core voltage after adjustment is at %d mV\n",
+ vdd_last);
+ else
+ ret = -1;
+exit:
+ if (re_enable)
+ enable_interrupts();
+ i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
+ return ret;
+}
+#else /* !CONFIG_FSL_LSCH3 */
+int adjust_vdd(ulong vdd_override)
+{
+ int re_enable = disable_interrupts();
+#if defined(CONFIG_FSL_LSCH2)
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
#else
ccsr_gur_t __iomem *gur =
@@ -364,11 +524,7 @@ int adjust_vdd(ulong vdd_override)
}
/* get the voltage ID from fuse status register */
-#ifdef CONFIG_FSL_LSCH3
- fusesr = in_le32(&gur->dcfg_fusesr);
-#else
fusesr = in_be32(&gur->dcfg_fusesr);
-#endif
/*
* VID is used according to the table below
* ---------------------------------------
@@ -393,13 +549,6 @@ int adjust_vdd(ulong vdd_override)
vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
}
-#elif defined(CONFIG_FSL_LSCH3)
- vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
- FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
- if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
- vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
- FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
- }
#else
vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
@@ -472,6 +621,7 @@ exit:
return ret;
}
+#endif
static int print_vdd(void)
{
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
index 789cae2..25d22d2 100644
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -12,6 +12,7 @@
#ifdef CONFIG_FSL_LS_PPA
#include <asm/arch/ppa.h>
#endif
+#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <hwconfig.h>
#include <environment.h>
@@ -48,6 +49,10 @@ int dram_init(void)
mmdc_init(&mparam);
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+ /* This will break-before-make MMU for DDR */
+ update_early_mmu_table();
+#endif
return 0;
}
@@ -91,32 +96,3 @@ int ft_board_setup(void *blob, bd_t *bd)
return 0;
}
-
-void dram_init_banksize(void)
-{
- /*
- * gd->arch.secure_ram tracks the location of secure memory.
- * It was set as if the memory starts from 0.
- * The address needs to add the offset of its bank.
- */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
- gd->bd->bi_dram[1].size = gd->ram_size -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[1].start +
- gd->arch.secure_ram -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- } else {
- gd->bd->bi_dram[0].size = gd->ram_size;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[0].start +
- gd->arch.secure_ram;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- }
-}
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index 4281790..97ab340 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -14,6 +14,7 @@
#include <asm/arch/ppa.h>
#endif
#include <asm/arch/fdt.h>
+#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <ahci.h>
#include <hwconfig.h>
@@ -76,6 +77,10 @@ int dram_init(void)
mmdc_init(&mparam);
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+ /* This will break-before-make MMU for DDR */
+ update_early_mmu_table();
+#endif
return 0;
}
@@ -166,32 +171,3 @@ int ft_board_setup(void *blob, bd_t *bd)
return 0;
}
#endif
-
-void dram_init_banksize(void)
-{
- /*
- * gd->arch.secure_ram tracks the location of secure memory.
- * It was set as if the memory starts from 0.
- * The address needs to add the offset of its bank.
- */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
- gd->bd->bi_dram[1].size = gd->ram_size -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[1].start +
- gd->arch.secure_ram -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- } else {
- gd->bd->bi_dram[0].size = gd->ram_size;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[0].start +
- gd->arch.secure_ram;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- }
-}
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
index e3a8a76..a23a23b 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -12,6 +12,7 @@
#ifdef CONFIG_FSL_LS_PPA
#include <asm/arch/ppa.h>
#endif
+#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <hwconfig.h>
#include <ahci.h>
@@ -80,6 +81,10 @@ int dram_init(void)
mmdc_init(&mparam);
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+ /* This will break-before-make MMU for DDR */
+ update_early_mmu_table();
+#endif
return 0;
}
@@ -165,32 +170,3 @@ int ft_board_setup(void *blob, bd_t *bd)
return 0;
}
-
-void dram_init_banksize(void)
-{
- /*
- * gd->secure_ram tracks the location of secure memory.
- * It was set as if the memory starts from 0.
- * The address needs to add the offset of its bank.
- */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
- gd->bd->bi_dram[1].size = gd->ram_size -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[1].start +
- gd->arch.secure_ram -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- } else {
- gd->bd->bi_dram[0].size = gd->ram_size;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[0].start +
- gd->arch.secure_ram;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- }
-}
diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c
index 7882a9a..c740062 100644
--- a/board/freescale/ls1043aqds/ddr.c
+++ b/board/freescale/ls1043aqds/ddr.c
@@ -127,32 +127,3 @@ phys_size_t initdram(int board_type)
return dram_size;
}
-
-void dram_init_banksize(void)
-{
- /*
- * gd->arch.secure_ram tracks the location of secure memory.
- * It was set as if the memory starts from 0.
- * The address needs to add the offset of its bank.
- */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
- gd->bd->bi_dram[1].size = gd->ram_size -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[1].start +
- gd->arch.secure_ram -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- } else {
- gd->bd->bi_dram[0].size = gd->ram_size;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[0].start +
- gd->arch.secure_ram;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- }
-}
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index 8835a49..6507c09 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -11,6 +11,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/fdt.h>
+#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <ahci.h>
#include <hwconfig.h>
@@ -153,6 +154,10 @@ int dram_init(void)
*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
gd->ram_size = initdram(0);
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+ /* This will break-before-make MMU for DDR */
+ update_early_mmu_table();
+#endif
return 0;
}
diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c
index 849f1d1..f90b85d 100644
--- a/board/freescale/ls1043ardb/ddr.c
+++ b/board/freescale/ls1043ardb/ddr.c
@@ -188,32 +188,3 @@ phys_size_t initdram(int board_type)
return dram_size;
}
-
-void dram_init_banksize(void)
-{
- /*
- * gd->arch.secure_ram tracks the location of secure memory.
- * It was set as if the memory starts from 0.
- * The address needs to add the offset of its bank.
- */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
- gd->bd->bi_dram[1].size = gd->ram_size -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[1].start +
- gd->arch.secure_ram -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- } else {
- gd->bd->bi_dram[0].size = gd->ram_size;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[0].start +
- gd->arch.secure_ram;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- }
-}
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index e213128..2333843 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -67,13 +67,6 @@ int checkboard(void)
return 0;
}
-int dram_init(void)
-{
- gd->ram_size = initdram(0);
-
- return 0;
-}
-
int board_early_init_f(void)
{
fsl_lsch2_early_init_f();
diff --git a/board/freescale/ls1046aqds/ddr.c b/board/freescale/ls1046aqds/ddr.c
index 4ea8b23..dc4d689 100644
--- a/board/freescale/ls1046aqds/ddr.c
+++ b/board/freescale/ls1046aqds/ddr.c
@@ -112,32 +112,3 @@ phys_size_t initdram(int board_type)
return dram_size;
}
-
-void dram_init_banksize(void)
-{
- /*
- * gd->arch.secure_ram tracks the location of secure memory.
- * It was set as if the memory starts from 0.
- * The address needs to add the offset of its bank.
- */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
- gd->bd->bi_dram[1].size = gd->ram_size -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[1].start +
- gd->arch.secure_ram -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- } else {
- gd->bd->bi_dram[0].size = gd->ram_size;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[0].start +
- gd->arch.secure_ram;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- }
-}
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c
index 552365b..af3f70a 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -11,6 +11,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/fdt.h>
+#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <ahci.h>
#include <hwconfig.h>
@@ -149,6 +150,10 @@ int dram_init(void)
*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
gd->ram_size = initdram(0);
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+ /* This will break-before-make MMU for DDR */
+ update_early_mmu_table();
+#endif
return 0;
}
diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c
index dd3b5d0..efe2ba6 100644
--- a/board/freescale/ls1046ardb/ddr.c
+++ b/board/freescale/ls1046ardb/ddr.c
@@ -112,32 +112,3 @@ phys_size_t initdram(int board_type)
return dram_size;
}
-
-void dram_init_banksize(void)
-{
- /*
- * gd->arch.secure_ram tracks the location of secure memory.
- * It was set as if the memory starts from 0.
- * The address needs to add the offset of its bank.
- */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
- gd->bd->bi_dram[1].size = gd->ram_size -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[1].start +
- gd->arch.secure_ram -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- } else {
- gd->bd->bi_dram[0].size = gd->ram_size;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[0].start +
- gd->arch.secure_ram;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- }
-}
diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c
index 33a58cf..02b6c4c 100644
--- a/board/freescale/ls1046ardb/ls1046ardb.c
+++ b/board/freescale/ls1046ardb/ls1046ardb.c
@@ -56,13 +56,6 @@ int checkboard(void)
return 0;
}
-int dram_init(void)
-{
- gd->ram_size = initdram(0);
-
- return 0;
-}
-
int board_early_init_f(void)
{
fsl_lsch2_early_init_f();
diff --git a/board/freescale/ls2080a/ddr.c b/board/freescale/ls2080a/ddr.c
index e6130ec..5ed9e14 100644
--- a/board/freescale/ls2080a/ddr.c
+++ b/board/freescale/ls2080a/ddr.c
@@ -169,58 +169,3 @@ phys_size_t initdram(int board_type)
return dram_size;
}
-
-void dram_init_banksize(void)
-{
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
- phys_size_t dp_ddr_size;
-#endif
-
- /*
- * gd->arch.secure_ram tracks the location of secure memory.
- * It was set as if the memory starts from 0.
- * The address needs to add the offset of its bank.
- */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
- gd->bd->bi_dram[1].size = gd->ram_size -
- CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[1].start +
- gd->arch.secure_ram -
- CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- } else {
- gd->bd->bi_dram[0].size = gd->ram_size;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[0].start +
- gd->arch.secure_ram;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- }
-
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
- if (soc_has_dp_ddr()) {
- /* initialize DP-DDR here */
- puts("DP-DDR: ");
- /*
- * DDR controller use 0 as the base address for binding.
- * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
- */
- dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
- CONFIG_DP_DDR_CTRL,
- CONFIG_DP_DDR_NUM_CTRLS,
- CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
- NULL, NULL, NULL);
- if (dp_ddr_size) {
- gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
- gd->bd->bi_dram[2].size = dp_ddr_size;
- } else {
- puts("Not detected");
- }
- }
-#endif
-}
diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c
index 4f9b9c8..9e7701d 100644
--- a/board/freescale/ls2080a/ls2080a.c
+++ b/board/freescale/ls2080a/ls2080a.c
@@ -49,13 +49,6 @@ void detail_board_ddr_info(void)
#endif
}
-int dram_init(void)
-{
- gd->ram_size = initdram(0);
-
- return 0;
-}
-
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
@@ -123,6 +116,16 @@ int ft_board_setup(void *blob, bd_t *bd)
base[1] = gd->bd->bi_dram[1].start;
size[1] = gd->bd->bi_dram[1].size;
+#ifdef CONFIG_RESV_RAM
+ /* reduce size if reserved memory is within this bank */
+ if (gd->arch.resv_ram >= base[0] &&
+ gd->arch.resv_ram < base[0] + size[0])
+ size[0] = gd->arch.resv_ram - base[0];
+ else if (gd->arch.resv_ram >= base[1] &&
+ gd->arch.resv_ram < base[1] + size[1])
+ size[1] = gd->arch.resv_ram - base[1];
+#endif
+
fdt_fixup_memory_banks(blob, base, size, 2);
#ifdef CONFIG_FSL_MC_ENET
diff --git a/board/freescale/ls2080aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c
index 9c6f477..0408c0f 100644
--- a/board/freescale/ls2080aqds/ddr.c
+++ b/board/freescale/ls2080aqds/ddr.c
@@ -169,58 +169,3 @@ phys_size_t initdram(int board_type)
return dram_size;
}
-
-void dram_init_banksize(void)
-{
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
- phys_size_t dp_ddr_size;
-#endif
-
- /*
- * gd->arch.secure_ram tracks the location of secure memory.
- * It was set as if the memory starts from 0.
- * The address needs to add the offset of its bank.
- */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
- gd->bd->bi_dram[1].size = gd->ram_size -
- CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[1].start +
- gd->arch.secure_ram -
- CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- } else {
- gd->bd->bi_dram[0].size = gd->ram_size;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[0].start +
- gd->arch.secure_ram;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- }
-
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
- if (soc_has_dp_ddr()) {
- /* initialize DP-DDR here */
- puts("DP-DDR: ");
- /*
- * DDR controller use 0 as the base address for binding.
- * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
- */
- dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
- CONFIG_DP_DDR_CTRL,
- CONFIG_DP_DDR_NUM_CTRLS,
- CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
- NULL, NULL, NULL);
- if (dp_ddr_size) {
- gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
- gd->bd->bi_dram[2].size = dp_ddr_size;
- } else {
- puts("Not detected");
- }
- }
-#endif
-}
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index 73a61fd..277013b 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -22,6 +22,7 @@
#include "../common/qixis.h"
#include "ls2080aqds_qixis.h"
+#include "../common/vid.h"
#define PIN_MUX_SEL_SDHC 0x00
#define PIN_MUX_SEL_DSPI 0x0a
@@ -240,6 +241,14 @@ int board_early_init_f(void)
return 0;
}
+int misc_init_r(void)
+{
+ if (adjust_vdd(0))
+ printf("Warning: Adjusting core voltage failed.\n");
+
+ return 0;
+}
+
void detail_board_ddr_info(void)
{
puts("\nDDR ");
@@ -254,13 +263,6 @@ void detail_board_ddr_info(void)
#endif
}
-int dram_init(void)
-{
- gd->ram_size = initdram(0);
-
- return 0;
-}
-
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
@@ -313,6 +315,16 @@ int ft_board_setup(void *blob, bd_t *bd)
base[1] = gd->bd->bi_dram[1].start;
size[1] = gd->bd->bi_dram[1].size;
+#ifdef CONFIG_RESV_RAM
+ /* reduce size if reserved memory is within this bank */
+ if (gd->arch.resv_ram >= base[0] &&
+ gd->arch.resv_ram < base[0] + size[0])
+ size[0] = gd->arch.resv_ram - base[0];
+ else if (gd->arch.resv_ram >= base[1] &&
+ gd->arch.resv_ram < base[1] + size[1])
+ size[1] = gd->arch.resv_ram - base[1];
+#endif
+
fdt_fixup_memory_banks(blob, base, size, 2);
fsl_fdt_fixup_dr_usb(blob, bd);
diff --git a/board/freescale/ls2080ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c
index 959dfeb..2851d5b 100644
--- a/board/freescale/ls2080ardb/ddr.c
+++ b/board/freescale/ls2080ardb/ddr.c
@@ -172,58 +172,3 @@ phys_size_t initdram(int board_type)
return dram_size;
}
-
-void dram_init_banksize(void)
-{
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
- phys_size_t dp_ddr_size;
-#endif
-
- /*
- * gd->arch.secure_ram tracks the location of secure memory.
- * It was set as if the memory starts from 0.
- * The address needs to add the offset of its bank.
- */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
- gd->bd->bi_dram[1].size = gd->ram_size -
- CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[1].start +
- gd->arch.secure_ram -
- CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- } else {
- gd->bd->bi_dram[0].size = gd->ram_size;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[0].start +
- gd->arch.secure_ram;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- }
-
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
- if (soc_has_dp_ddr()) {
- /* initialize DP-DDR here */
- puts("DP-DDR: ");
- /*
- * DDR controller use 0 as the base address for binding.
- * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
- */
- dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
- CONFIG_DP_DDR_CTRL,
- CONFIG_DP_DDR_NUM_CTRLS,
- CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
- NULL, NULL, NULL);
- if (dp_ddr_size) {
- gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
- gd->bd->bi_dram[2].size = dp_ddr_size;
- } else {
- puts("Not detected");
- }
- }
-#endif
-}
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index 02954ef..4c01f56 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -17,6 +17,7 @@
#include <environment.h>
#include <efi_loader.h>
#include <i2c.h>
+#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <fsl_sec.h>
@@ -202,14 +203,6 @@ int misc_init_r(void)
if (adjust_vdd(0))
printf("Warning: Adjusting core voltage failed.\n");
-#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)
- if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
- efi_add_memory_map(gd->bd->bi_dram[2].start,
- gd->bd->bi_dram[2].size >> EFI_PAGE_SHIFT,
- EFI_RESERVED_MEMORY_TYPE, false);
- }
-#endif
-
return 0;
}
@@ -227,13 +220,6 @@ void detail_board_ddr_info(void)
#endif
}
-int dram_init(void)
-{
- gd->ram_size = initdram(0);
-
- return 0;
-}
-
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
@@ -286,6 +272,16 @@ int ft_board_setup(void *blob, bd_t *bd)
base[1] = gd->bd->bi_dram[1].start;
size[1] = gd->bd->bi_dram[1].size;
+#ifdef CONFIG_RESV_RAM
+ /* reduce size if reserved memory is within this bank */
+ if (gd->arch.resv_ram >= base[0] &&
+ gd->arch.resv_ram < base[0] + size[0])
+ size[0] = gd->arch.resv_ram - base[0];
+ else if (gd->arch.resv_ram >= base[1] &&
+ gd->arch.resv_ram < base[1] + size[1])
+ size[1] = gd->arch.resv_ram - base[1];
+#endif
+
fdt_fixup_memory_banks(blob, base, size, 2);
fsl_fdt_fixup_dr_usb(blob, bd);
diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c
index 7ed7bf7..fdad8d1 100644
--- a/board/st/stm32f746-disco/stm32f746-disco.c
+++ b/board/st/stm32f746-disco/stm32f746-disco.c
@@ -27,14 +27,6 @@ const struct stm32_gpio_ctl gpio_ctl_gpout = {
.af = STM32_GPIO_AF0
};
-const struct stm32_gpio_ctl gpio_ctl_usart = {
- .mode = STM32_GPIO_MODE_AF,
- .otype = STM32_GPIO_OTYPE_PP,
- .speed = STM32_GPIO_SPEED_50M,
- .pupd = STM32_GPIO_PUPD_UP,
- .af = STM32_GPIO_AF7
-};
-
const struct stm32_gpio_ctl gpio_ctl_fmc = {
.mode = STM32_GPIO_MODE_AF,
.otype = STM32_GPIO_OTYPE_PP,
@@ -245,81 +237,24 @@ int dram_init(void)
return rv;
}
-static const struct stm32_gpio_dsc usart_gpio[] = {
- {STM32_GPIO_PORT_A, STM32_GPIO_PIN_9}, /* TX */
- {STM32_GPIO_PORT_B, STM32_GPIO_PIN_7}, /* RX */
-};
-
int uart_setup_gpio(void)
{
- int i;
- int rv = 0;
-
clock_setup(GPIO_A_CLOCK_CFG);
clock_setup(GPIO_B_CLOCK_CFG);
- for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) {
- rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart);
- if (rv)
- goto out;
- }
-
-out:
- return rv;
+ return 0;
}
-static const struct stm32x7_serial_platdata serial_platdata = {
- .base = (struct stm32_usart *)USART1_BASE,
- .clock = CONFIG_SYS_CLK_FREQ,
-};
-
-U_BOOT_DEVICE(stm32x7_serials) = {
- .name = "serial_stm32x7",
- .platdata = &serial_platdata,
-};
-
#ifdef CONFIG_ETH_DESIGNWARE
-const struct stm32_gpio_ctl gpio_ctl_eth = {
- .mode = STM32_GPIO_MODE_AF,
- .otype = STM32_GPIO_OTYPE_PP,
- .speed = STM32_GPIO_SPEED_100M,
- .pupd = STM32_GPIO_PUPD_NO,
- .af = STM32_GPIO_AF11
-};
-
-static const struct stm32_gpio_dsc eth_gpio[] = {
- {STM32_GPIO_PORT_A, STM32_GPIO_PIN_1}, /* ETH_RMII_REF_CLK */
- {STM32_GPIO_PORT_A, STM32_GPIO_PIN_2}, /* ETH_MDIO */
- {STM32_GPIO_PORT_A, STM32_GPIO_PIN_7}, /* ETH_RMII_CRS_DV */
-
- {STM32_GPIO_PORT_C, STM32_GPIO_PIN_1}, /* ETH_MDC */
- {STM32_GPIO_PORT_C, STM32_GPIO_PIN_4}, /* ETH_RMII_RXD0 */
- {STM32_GPIO_PORT_C, STM32_GPIO_PIN_5}, /* ETH_RMII_RXD1 */
-
- {STM32_GPIO_PORT_G, STM32_GPIO_PIN_11}, /* ETH_RMII_TX_EN */
- {STM32_GPIO_PORT_G, STM32_GPIO_PIN_13}, /* ETH_RMII_TXD0 */
- {STM32_GPIO_PORT_G, STM32_GPIO_PIN_14}, /* ETH_RMII_TXD1 */
-};
static int stmmac_setup(void)
{
- int res = 0;
- int i;
-
clock_setup(SYSCFG_CLOCK_CFG);
-
/* Set >RMII mode */
STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
clock_setup(GPIO_A_CLOCK_CFG);
clock_setup(GPIO_C_CLOCK_CFG);
clock_setup(GPIO_G_CLOCK_CFG);
-
- for (i = 0; i < ARRAY_SIZE(eth_gpio); i++) {
- res = stm32_gpio_config(&eth_gpio[i], &gpio_ctl_eth);
- if (res)
- return res;
- }
-
clock_setup(STMMAC_CLOCK_CFG);
return 0;
@@ -327,55 +262,12 @@ static int stmmac_setup(void)
#endif
#ifdef CONFIG_STM32_QSPI
-const struct stm32_gpio_ctl gpio_ctl_qspi_9 = {
- .mode = STM32_GPIO_MODE_AF,
- .otype = STM32_GPIO_OTYPE_PP,
- .speed = STM32_GPIO_SPEED_100M,
- .pupd = STM32_GPIO_PUPD_NO,
- .af = STM32_GPIO_AF9
-};
-
-const struct stm32_gpio_ctl gpio_ctl_qspi_10 = {
- .mode = STM32_GPIO_MODE_AF,
- .otype = STM32_GPIO_OTYPE_PP,
- .speed = STM32_GPIO_SPEED_100M,
- .pupd = STM32_GPIO_PUPD_NO,
- .af = STM32_GPIO_AF10
-};
-
-static const struct stm32_gpio_dsc qspi_af9_gpio[] = {
- {STM32_GPIO_PORT_B, STM32_GPIO_PIN_2}, /* QUADSPI_CLK */
- {STM32_GPIO_PORT_D, STM32_GPIO_PIN_11}, /* QUADSPI_BK1_IO0 */
- {STM32_GPIO_PORT_D, STM32_GPIO_PIN_12}, /* QUADSPI_BK1_IO1 */
- {STM32_GPIO_PORT_D, STM32_GPIO_PIN_13}, /* QUADSPI_BK1_IO3 */
- {STM32_GPIO_PORT_E, STM32_GPIO_PIN_2}, /* QUADSPI_BK1_IO2 */
-};
-
-static const struct stm32_gpio_dsc qspi_af10_gpio[] = {
- {STM32_GPIO_PORT_B, STM32_GPIO_PIN_6}, /* QUADSPI_BK1_NCS */
-};
static int qspi_setup(void)
{
- int res = 0;
- int i;
-
clock_setup(GPIO_B_CLOCK_CFG);
clock_setup(GPIO_D_CLOCK_CFG);
clock_setup(GPIO_E_CLOCK_CFG);
-
- for (i = 0; i < ARRAY_SIZE(qspi_af9_gpio); i++) {
- res = stm32_gpio_config(&qspi_af9_gpio[i], &gpio_ctl_qspi_9);
- if (res)
- return res;
- }
-
- for (i = 0; i < ARRAY_SIZE(qspi_af10_gpio); i++) {
- res = stm32_gpio_config(&qspi_af10_gpio[i], &gpio_ctl_qspi_10);
- if (res)
- return res;
- }
-
return 0;
}
#endif
@@ -390,7 +282,6 @@ int board_early_init_f(void)
int res;
res = uart_setup_gpio();
- clock_setup(USART1_CLOCK_CFG);
if (res)
return res;
generated by cgit v0.10.2 at 2024-08-02 04:50:06 (GMT)