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-rw-r--r--cpu/mcf532x/cpu.c21
-rw-r--r--cpu/mcf532x/cpu_init.c202
-rw-r--r--cpu/mcf532x/speed.c119
-rw-r--r--cpu/mcf532x/start.S11
4 files changed, 304 insertions, 49 deletions
diff --git a/cpu/mcf532x/cpu.c b/cpu/mcf532x/cpu.c
index fd77939..bcb092d 100644
--- a/cpu/mcf532x/cpu.c
+++ b/cpu/mcf532x/cpu.c
@@ -3,7 +3,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -56,6 +56,24 @@ int checkcpu(void)
msk = (ccm->cir >> 6);
ver = (ccm->cir & 0x003f);
switch (msk) {
+#ifdef CONFIG_MCF5301x
+ case 0x78:
+ id = 53010;
+ break;
+ case 0x77:
+ id = 53012;
+ break;
+ case 0x76:
+ id = 53015;
+ break;
+ case 0x74:
+ id = 53011;
+ break;
+ case 0x73:
+ id = 53013;
+ break;
+#endif
+#ifdef CONFIG_MCF532x
case 0x54:
id = 5329;
break;
@@ -77,6 +95,7 @@ int checkcpu(void)
case 0x6B:
id = 5372;
break;
+#endif
}
if (id) {
diff --git a/cpu/mcf532x/cpu_init.c b/cpu/mcf532x/cpu_init.c
index 39be11f..687c7e4 100644
--- a/cpu/mcf532x/cpu_init.c
+++ b/cpu/mcf532x/cpu_init.c
@@ -3,7 +3,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * (C) Copyright 2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -35,13 +35,180 @@
#include <asm/fec.h>
#endif
-/*
- * Breath some life into the CPU...
- *
- * Set up the memory map,
- * initialize a bunch of registers,
- * initialize the UPM's
- */
+#ifdef CONFIG_MCF5301x
+void cpu_init_f(void)
+{
+ volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+ volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+
+ /* watchdog is enabled by default - disable the watchdog */
+#ifndef CONFIG_WATCHDOG
+ /*wdog->cr = 0; */
+#endif
+
+ scm1->mpr = 0x77777777;
+ scm1->pacra = 0;
+ scm1->pacrb = 0;
+ scm1->pacrc = 0;
+ scm1->pacrd = 0;
+ scm1->pacre = 0;
+ scm1->pacrf = 0;
+ scm1->pacrg = 0;
+
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
+ && defined(CONFIG_SYS_CS0_CTRL))
+ gpio->par_cs |= GPIO_PAR_CS0_CS0;
+ fbcs->csar0 = CONFIG_SYS_CS0_BASE;
+ fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
+ fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+#endif
+
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
+ && defined(CONFIG_SYS_CS1_CTRL))
+ gpio->par_cs |= GPIO_PAR_CS1_CS1;
+ fbcs->csar1 = CONFIG_SYS_CS1_BASE;
+ fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
+ fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+#endif
+
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
+ && defined(CONFIG_SYS_CS2_CTRL))
+ fbcs->csar2 = CONFIG_SYS_CS2_BASE;
+ fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
+ fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+#endif
+
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
+ && defined(CONFIG_SYS_CS3_CTRL))
+ fbcs->csar3 = CONFIG_SYS_CS3_BASE;
+ fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
+ fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+#endif
+
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
+ && defined(CONFIG_SYS_CS4_CTRL))
+ gpio->par_cs |= GPIO_PAR_CS4;
+ fbcs->csar4 = CONFIG_SYS_CS4_BASE;
+ fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
+ fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+#endif
+
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
+ && defined(CONFIG_SYS_CS5_CTRL))
+ gpio->par_cs |= GPIO_PAR_CS5;
+ fbcs->csar5 = CONFIG_SYS_CS5_BASE;
+ fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
+ fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+#endif
+
+#ifdef CONFIG_FSL_I2C
+ gpio->par_feci2c = GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL;
+#endif
+
+ icache_enable();
+}
+
+/* initialize higher level parts of CPU like timers */
+int cpu_init_r(void)
+{
+#ifdef CONFIG_MCFFEC
+ volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+#endif
+#ifdef CONFIG_MCFRTC
+ volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
+ volatile rtcex_t *rtcex = (rtcex_t *) & rtc->extended;
+
+ rtcex->gocu = CONFIG_SYS_RTC_CNT;
+ rtcex->gocl = CONFIG_SYS_RTC_SETUP;
+
+#endif
+#ifdef CONFIG_MCFFEC
+ if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE)
+ ccm->misccr |= CCM_MISCCR_FECM;
+ else
+ ccm->misccr &= ~CCM_MISCCR_FECM;
+#endif
+
+ return (0);
+}
+
+void uart_port_conf(void)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ /* Setup Ports: */
+ switch (CONFIG_SYS_UART_PORT) {
+ case 0:
+ gpio->par_uart = (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+ break;
+ case 1:
+#ifdef CONFIG_SYS_UART1_ALT1_GPIO
+ gpio->par_simp1h &=
+ ~(GPIO_PAR_SIMP1H_DATA1_MASK | GPIO_PAR_SIMP1H_VEN1_MASK);
+ gpio->par_simp1h |=
+ (GPIO_PAR_SIMP1H_DATA1_U1TXD | GPIO_PAR_SIMP1H_VEN1_U1RXD);
+#elif defined(CONFIG_SYS_UART1_ALT2_GPIO)
+ gpio->par_ssih &=
+ ~(GPIO_PAR_SSIH_RXD_MASK | GPIO_PAR_SSIH_TXD_MASK);
+ gpio->par_ssih |=
+ (GPIO_PAR_SSIH_RXD_U1RXD | GPIO_PAR_SSIH_TXD_U1TXD);
+#endif
+ break;
+ case 2:
+#ifdef CONFIG_SYS_UART2_PRI_GPIO
+ gpio->par_uart |= (GPIO_PAR_UART_U2TXD | GPIO_PAR_UART_U2RXD);
+#elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
+ gpio->par_dspih &=
+ ~(GPIO_PAR_DSPIH_SIN_MASK | GPIO_PAR_DSPIH_SOUT_MASK);
+ gpio->par_dspih |=
+ (GPIO_PAR_DSPIH_SIN_U2RXD | GPIO_PAR_DSPIH_SOUT_U2TXD);
+#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
+ gpio->par_feci2c &=
+ ~(GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK);
+ gpio->par_feci2c |=
+ (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
+#endif
+ break;
+ }
+}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ struct fec_info_s *info = (struct fec_info_s *)dev->priv;
+
+ if (setclear) {
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+ gpio->par_fec |=
+ GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC;
+ gpio->par_feci2c |=
+ GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0;
+ } else {
+ gpio->par_fec |=
+ GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC;
+ gpio->par_feci2c |=
+ GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1;
+ }
+ } else {
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+ gpio->par_fec &=
+ ~(GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
+ gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_MASK;
+ } else {
+ gpio->par_fec &=
+ ~(GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
+ gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_MASK;
+ }
+ }
+ return 0;
+}
+#endif /* CONFIG_CMD_NET */
+#endif /* CONFIG_MCF5301x */
+
+#ifdef CONFIG_MCF532x
void cpu_init_f(void)
{
volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
@@ -68,13 +235,15 @@ void cpu_init_f(void)
/* Port configuration */
gpio->par_cs = 0;
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
+ && defined(CONFIG_SYS_CS0_CTRL))
fbcs->csar0 = CONFIG_SYS_CS0_BASE;
fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
#endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
+ && defined(CONFIG_SYS_CS1_CTRL))
/* Latch chipselect */
gpio->par_cs |= GPIO_PAR_CS1;
fbcs->csar1 = CONFIG_SYS_CS1_BASE;
@@ -82,28 +251,32 @@ void cpu_init_f(void)
fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
#endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
+ && defined(CONFIG_SYS_CS2_CTRL))
gpio->par_cs |= GPIO_PAR_CS2;
fbcs->csar2 = CONFIG_SYS_CS2_BASE;
fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
#endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
+ && defined(CONFIG_SYS_CS3_CTRL))
gpio->par_cs |= GPIO_PAR_CS3;
fbcs->csar3 = CONFIG_SYS_CS3_BASE;
fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
#endif
-#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
+ && defined(CONFIG_SYS_CS4_CTRL))
gpio->par_cs |= GPIO_PAR_CS4;
fbcs->csar4 = CONFIG_SYS_CS4_BASE;
fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
#endif
-#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
+ && defined(CONFIG_SYS_CS5_CTRL))
gpio->par_cs |= GPIO_PAR_CS5;
fbcs->csar5 = CONFIG_SYS_CS5_BASE;
fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
@@ -162,3 +335,4 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
return 0;
}
#endif
+#endif /* CONFIG_MCF532x */
diff --git a/cpu/mcf532x/speed.c b/cpu/mcf532x/speed.c
index 1e40374..0d378e6 100644
--- a/cpu/mcf532x/speed.c
+++ b/cpu/mcf532x/speed.c
@@ -3,7 +3,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -36,26 +36,33 @@ DECLARE_GLOBAL_DATA_PTR;
#define MAX_FVCO 500000 /* KHz */
#define MAX_FSYS 80000 /* KHz */
#define MIN_FSYS 58333 /* KHz */
+
+#ifdef CONFIG_MCF5301x
+#define FREF 20000 /* KHz */
+#define MAX_MFD 63 /* Multiplier */
+#define MIN_MFD 0 /* Multiplier */
+#define USBDIV 8
+
+/* Low Power Divider specifications */
+#define MIN_LPD (0) /* Divider (not encoded) */
+#define MAX_LPD (15) /* Divider (not encoded) */
+#define DEFAULT_LPD (0) /* Divider (not encoded) */
+#endif
+
+#ifdef CONFIG_MCF532x
#define FREF 16000 /* KHz */
#define MAX_MFD 135 /* Multiplier */
#define MIN_MFD 88 /* Multiplier */
-#define BUSDIV 6 /* Divider */
-/*
- * Low Power Divider specifications
- */
+
+/* Low Power Divider specifications */
#define MIN_LPD (1 << 0) /* Divider (not encoded) */
#define MAX_LPD (1 << 15) /* Divider (not encoded) */
#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */
+#endif
-/*
- * Get the value of the current system clock
- *
- * Parameters:
- * none
- *
- * Return Value:
- * The current output system frequency
- */
+#define BUSDIV 6 /* Divider */
+
+/* Get the value of the current system clock */
int get_sys_clock(void)
{
volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
@@ -65,9 +72,23 @@ int get_sys_clock(void)
/* Test to see if device is in LIMP mode */
if (ccm->misccr & CCM_MISCCR_LIMP) {
divider = ccm->cdr & CCM_CDR_LPDIV(0xF);
+#ifdef CONFIG_MCF5301x
+ return (FREF / (3 * (1 << divider)));
+#endif
+#ifdef CONFIG_MCF532x
return (FREF / (2 << divider));
+#endif
} else {
+#ifdef CONFIG_MCF5301x
+ u32 pfdr = (pll->pcr & 0x3F) + 1;
+ u32 refdiv = (1 << ((pll->pcr & PLL_PCR_REFDIV(7)) >> 8));
+ u32 busdiv = ((pll->pdr & 0x00F0) >> 4) + 1;
+
+ return (((FREF * pfdr) / refdiv) / busdiv);
+#endif
+#ifdef CONFIG_MCF532x
return ((FREF * pll->pfdr) / (BUSDIV * 4));
+#endif
}
}
@@ -92,7 +113,7 @@ int clock_limp(int div)
div = MAX_LPD;
/* Save of the current value of the SSIDIV so we don't overwrite the value */
- temp = (ccm->cdr & CCM_CDR_SSIDIV(0xF));
+ temp = (ccm->cdr & CCM_CDR_SSIDIV(0xFF));
/* Apply the divider to the system clock */
ccm->cdr = (CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));
@@ -102,15 +123,7 @@ int clock_limp(int div)
return (FREF / (3 * (1 << div)));
}
-/*
- * Exit low power LIMP mode
- *
- * Parameters:
- * div Desired system frequency divider
- *
- * Return Value:
- * The resulting output system frequency
- */
+/* Exit low power LIMP mode */
int clock_exit_limp(void)
{
volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
@@ -139,7 +152,10 @@ int clock_exit_limp(void)
*/
int clock_pll(int fsys, int flags)
{
+#ifdef CONFIG_MCF532x
volatile u32 *sdram_workaround = (volatile u32 *)(MMAP_SDRAM + 0x80);
+#endif
+ volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
int fref, temp, fout, mfd;
u32 i;
@@ -148,9 +164,17 @@ int clock_pll(int fsys, int flags)
if (fsys == 0) {
/* Return current PLL output */
+#ifdef CONFIG_MCF5301x
+ u32 busdiv = ((pll->pdr >> 4) & 0x0F) + 1;
+ mfd = (pll->pcr & 0x3F) + 1;
+
+ return (fref * mfd) / busdiv;
+#endif
+#ifdef CONFIG_MCF532x
mfd = pll->pfdr;
return (fref * mfd / (BUSDIV * 4));
+#endif
}
/* Check bounds of requested system clock */
@@ -160,21 +184,33 @@ int clock_pll(int fsys, int flags)
if (fsys < MIN_FSYS)
fsys = MIN_FSYS;
- /* Multiplying by 100 when calculating the temp value,
- and then dividing by 100 to calculate the mfd allows
- for exact values without needing to include floating
- point libraries. */
+ /*
+ * Multiplying by 100 when calculating the temp value,
+ * and then dividing by 100 to calculate the mfd allows
+ * for exact values without needing to include floating
+ * point libraries.
+ */
temp = (100 * fsys) / fref;
+#ifdef CONFIG_MCF5301x
+ mfd = (BUSDIV * temp) / 100;
+
+ /* Determine the output frequency for selected values */
+ fout = ((fref * mfd) / BUSDIV);
+#endif
+#ifdef CONFIG_MCF532x
mfd = (4 * BUSDIV * temp) / 100;
/* Determine the output frequency for selected values */
fout = ((fref * mfd) / (BUSDIV * 4));
+#endif
/*
* Check to see if the SDRAM has already been initialized.
* If it has then the SDRAM needs to be put into self refresh
* mode before reprogramming the PLL.
*/
+ if (sdram->ctrl & SDRAMC_SDCR_REF)
+ sdram->ctrl &= ~SDRAMC_SDCR_CKE;
/*
* Initialize the PLL to generate the new system clock frequency.
@@ -184,20 +220,37 @@ int clock_pll(int fsys, int flags)
/* Enter LIMP mode */
clock_limp(DEFAULT_LPD);
+#ifdef CONFIG_MCF5301x
+ pll->pdr =
+ PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) |
+ PLL_PDR_OUTDIV2(BUSDIV - 1) |
+ PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) |
+ PLL_PDR_OUTDIV4(USBDIV - 1);
+
+ pll->pcr &= PLL_PCR_FBDIV_MASK;
+ pll->pcr |= PLL_PCR_FBDIV(mfd - 1);
+#endif
+#ifdef CONFIG_MCF532x
/* Reprogram PLL for desired fsys */
pll->podr = (PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV));
pll->pfdr = mfd;
+#endif
/* Exit LIMP mode */
clock_exit_limp();
+ /* Return the SDRAM to normal operation if it is in use. */
+ if (sdram->ctrl & SDRAMC_SDCR_REF)
+ sdram->ctrl |= SDRAMC_SDCR_CKE;
+
+#ifdef CONFIG_MCF532x
/*
- * Return the SDRAM to normal operation if it is in use.
+ * software workaround for SDRAM opeartion after exiting LIMP
+ * mode errata
*/
-
- /* software workaround for SDRAM opeartion after exiting LIMP mode errata */
*sdram_workaround = CONFIG_SYS_SDRAM_BASE;
+#endif
/* wait for DQS logic to relock */
for (i = 0; i < 0x200; i++) ;
@@ -205,9 +258,7 @@ int clock_pll(int fsys, int flags)
return fout;
}
-/*
- * get_clocks() fills in gd->cpu_clock and gd->bus_clk
- */
+/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
int get_clocks(void)
{
gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000;
diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S
index 7a3eb5f..8fa605a 100644
--- a/cpu/mcf532x/start.S
+++ b/cpu/mcf532x/start.S
@@ -2,6 +2,9 @@
* Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
* Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
*
+ * (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -140,6 +143,14 @@ _start:
movec %d0, %ACR0
movec %d0, %ACR1
+#ifdef CONFIG_MCF5301x
+ move.l #(0xFC0a0010), %a0
+ move.w (%a0), %d0
+ and.l %d0, 0xEFFF
+
+ move.w %d0, (%a0)
+#endif
+
/* initialize general use internal ram */
move.l #0, %d0
move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
generated by cgit v0.10.2 at 2024-11-04 14:31:00 (GMT)