summaryrefslogtreecommitdiff
path: root/cpu
diff options
context:
space:
mode:
Diffstat (limited to 'cpu')
-rw-r--r--cpu/ppc4xx/40x_spd_sdram.c26
-rw-r--r--cpu/ppc4xx/44x_spd_ddr.c44
-rw-r--r--cpu/ppc4xx/sdram.c60
3 files changed, 65 insertions, 65 deletions
diff --git a/cpu/ppc4xx/40x_spd_sdram.c b/cpu/ppc4xx/40x_spd_sdram.c
index 83fa709..c50f673 100644
--- a/cpu/ppc4xx/40x_spd_sdram.c
+++ b/cpu/ppc4xx/40x_spd_sdram.c
@@ -424,30 +424,30 @@ long int spd_sdram(int(read_spd)(uint addr))
#define mtsdram0(reg, data) mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data)
/* disable memcontroller so updates work */
- mtsdram0( mem_mcopt1, 0 );
+ mtsdram0( SDRAM0_CFG, 0 );
#ifndef CONFIG_405EP /* not on PPC405EP */
- mtsdram0( mem_besra , sdram0_besr0 );
- mtsdram0( mem_besrb , sdram0_besr1 );
- mtsdram0( mem_ecccf , sdram0_ecccfg );
- mtsdram0( mem_eccerr, sdram0_eccesr );
+ mtsdram0( SDRAM0_BESR0 , sdram0_besr0 );
+ mtsdram0( SDRAM0_BESR1 , sdram0_besr1 );
+ mtsdram0( SDRAM0_ECCCFG , sdram0_ecccfg );
+ mtsdram0( SDRAM0_ECCESR, sdram0_eccesr );
#endif
- mtsdram0( mem_rtr , sdram0_rtr );
- mtsdram0( mem_pmit , sdram0_pmit );
- mtsdram0( mem_mb0cf , sdram0_b0cr );
- mtsdram0( mem_mb1cf , sdram0_b1cr );
+ mtsdram0( SDRAM0_RTR , sdram0_rtr );
+ mtsdram0( SDRAM0_PMIT , sdram0_pmit );
+ mtsdram0( SDRAM0_B0CR , sdram0_b0cr );
+ mtsdram0( SDRAM0_B1CR , sdram0_b1cr );
#ifndef CONFIG_405EP /* not on PPC405EP */
- mtsdram0( mem_mb2cf , sdram0_b2cr );
- mtsdram0( mem_mb3cf , sdram0_b3cr );
+ mtsdram0( SDRAM0_B2CR , sdram0_b2cr );
+ mtsdram0( SDRAM0_B3CR , sdram0_b3cr );
#endif
- mtsdram0( mem_sdtr1 , sdram0_tr );
+ mtsdram0( SDRAM0_TR , sdram0_tr );
/* SDRAM have a power on delay, 500 micro should do */
udelay(500);
sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
if (ecc_on)
sdram0_cfg |= SDRAM0_CFG_MEMCHK;
- mtsdram0(mem_mcopt1, sdram0_cfg);
+ mtsdram0(SDRAM0_CFG, sdram0_cfg);
return (total_size);
}
diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c
index c93f23a..6176eab 100644
--- a/cpu/ppc4xx/44x_spd_ddr.c
+++ b/cpu/ppc4xx/44x_spd_ddr.c
@@ -230,7 +230,7 @@ long int spd_sdram(void) {
/*
* program SDRAM Clock Timing Register (SDRAM0_CLKTR)
*/
- mtsdram(mem_clktr, 0x40000000);
+ mtsdram(SDRAM0_CLKTR, 0x40000000);
/*
* delay to ensure 200 usec has elapsed
@@ -240,14 +240,14 @@ long int spd_sdram(void) {
/*
* enable the memory controller
*/
- mfsdram(mem_cfg0, cfg0);
- mtsdram(mem_cfg0, cfg0 | SDRAM_CFG0_DCEN);
+ mfsdram(SDRAM0_CFG0, cfg0);
+ mtsdram(SDRAM0_CFG0, cfg0 | SDRAM_CFG0_DCEN);
/*
* wait for SDRAM_CFG0_DC_EN to complete
*/
while (1) {
- mfsdram(mem_mcsts, mcsts);
+ mfsdram(SDRAM0_MCSTS, mcsts);
if ((mcsts & SDRAM_MCSTS_MRSC) != 0)
break;
}
@@ -386,7 +386,7 @@ static void program_cfg0(unsigned long *dimm_populated,
/*
* get Memory Controller Options 0 data
*/
- mfsdram(mem_cfg0, cfg0);
+ mfsdram(SDRAM0_CFG0, cfg0);
/*
* clear bits
@@ -457,7 +457,7 @@ static void program_cfg0(unsigned long *dimm_populated,
* Note: DCEN must be enabled after all DDR SDRAM controller
* configuration registers get initialized.
*/
- mtsdram(mem_cfg0, cfg0);
+ mtsdram(SDRAM0_CFG0, cfg0);
}
static void program_cfg1(unsigned long *dimm_populated,
@@ -465,7 +465,7 @@ static void program_cfg1(unsigned long *dimm_populated,
unsigned long num_dimm_banks)
{
unsigned long cfg1;
- mfsdram(mem_cfg1, cfg1);
+ mfsdram(SDRAM0_CFG1, cfg1);
/*
* Self-refresh exit, disable PM
@@ -475,7 +475,7 @@ static void program_cfg1(unsigned long *dimm_populated,
/*
* program Memory Controller Options 1
*/
- mtsdram(mem_cfg1, cfg1);
+ mtsdram(SDRAM0_CFG1, cfg1);
}
static void program_rtr(unsigned long *dimm_populated,
@@ -535,7 +535,7 @@ static void program_rtr(unsigned long *dimm_populated,
/*
* program Refresh Timer Register (SDRAM0_RTR)
*/
- mtsdram(mem_rtr, sdram_rtr);
+ mtsdram(SDRAM0_RTR, sdram_rtr);
}
static void program_tr0(unsigned long *dimm_populated,
@@ -576,7 +576,7 @@ static void program_tr0(unsigned long *dimm_populated,
/*
* get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
*/
- mfsdram(mem_tr0, tr0);
+ mfsdram(SDRAM0_TR0, tr0);
tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
@@ -821,7 +821,7 @@ static void program_tr0(unsigned long *dimm_populated,
}
debug("tr0: %x\n", tr0);
- mtsdram(mem_tr0, tr0);
+ mtsdram(SDRAM0_TR0, tr0);
}
static int short_mem_test(void)
@@ -848,7 +848,7 @@ static int short_mem_test(void)
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}};
for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
- mtdcr(SDRAM0_CFGADDR, mem_b0cr + (bxcr_num << 2));
+ mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (bxcr_num << 2));
if ((mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
/* Bank is enabled */
membase = (unsigned long*)
@@ -918,11 +918,11 @@ static void program_tr1(void)
/*
* get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
*/
- mfsdram(mem_tr1, tr1);
+ mfsdram(SDRAM0_TR1, tr1);
tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
- mfsdram(mem_tr0, tr0);
+ mfsdram(SDRAM0_TR0, tr0);
if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
(sys_info.freqPLB > 100000000)) {
tr1 |= SDRAM_TR1_RDSS_TR2;
@@ -937,14 +937,14 @@ static void program_tr1(void)
/*
* save CFG0 ECC setting to a temporary variable and turn ECC off
*/
- mfsdram(mem_cfg0, cfg0);
+ mfsdram(SDRAM0_CFG0, cfg0);
ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK;
- mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
+ mtsdram(SDRAM0_CFG0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
/*
* get the delay line calibration register value
*/
- mfsdram(mem_dlycal, dlycal);
+ mfsdram(SDRAM0_DLYCAL, dlycal);
dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
max_pass_length = 0;
@@ -964,7 +964,7 @@ static void program_tr1(void)
/*
* Set the timing reg for the test.
*/
- mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
+ mtsdram(SDRAM0_TR1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
if (short_mem_test()) {
if (fail_found == TRUE) {
@@ -1018,7 +1018,7 @@ static void program_tr1(void)
/*
* restore the orignal ECC setting
*/
- mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
+ mtsdram(SDRAM0_CFG0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
/*
* set the SDRAM TR1 RDCD value
@@ -1056,7 +1056,7 @@ static void program_tr1(void)
/*
* program SDRAM Timing Register 1 TR1
*/
- mtsdram(mem_tr1, tr1);
+ mtsdram(SDRAM0_TR1, tr1);
}
static unsigned long program_bxcr(unsigned long *dimm_populated,
@@ -1086,7 +1086,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
* Set the BxCR regs. First, wipe out the bank config registers.
*/
for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
- mtdcr(SDRAM0_CFGADDR, mem_b0cr + (bx_cr_num << 2));
+ mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (bx_cr_num << 2));
mtdcr(SDRAM0_CFGDATA, 0x00000000);
bank_parms[bx_cr_num].bank_size_bytes = 0;
}
@@ -1232,7 +1232,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
/* Set the SDRAM0_BxCR regs thanks to sort tables */
for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) {
- mtdcr(SDRAM0_CFGADDR, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2));
+ mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (sorted_bank_num[bx_cr_num] << 2));
temp = mfdcr(SDRAM0_CFGDATA) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK |
SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE);
temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) |
diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c
index 5a3336e..30c6e0e 100644
--- a/cpu/ppc4xx/sdram.c
+++ b/cpu/ppc4xx/sdram.c
@@ -188,14 +188,14 @@ phys_size_t initdram(int board_type)
/*
* Disable memory controller.
*/
- mtsdram(mem_mcopt1, 0x00000000);
+ mtsdram(SDRAM0_CFG, 0x00000000);
/*
* Set MB0CF for bank 0.
*/
- mtsdram(mem_mb0cf, mb0cf[i].reg);
- mtsdram(mem_sdtr1, sdtr1);
- mtsdram(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64));
+ mtsdram(SDRAM0_B0CR, mb0cf[i].reg);
+ mtsdram(SDRAM0_TR, sdtr1);
+ mtsdram(SDRAM0_RTR, compute_rtr(speed, mb0cf[i].rows, 64));
udelay(200);
@@ -204,7 +204,7 @@ phys_size_t initdram(int board_type)
* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
* read/prefetch.
*/
- mtsdram(mem_mcopt1, 0x80800000);
+ mtsdram(SDRAM0_CFG, 0x80800000);
udelay(10000);
@@ -216,9 +216,9 @@ phys_size_t initdram(int board_type)
* defined (assumes same type as bank 0)
*/
#ifdef CONFIG_SDRAM_BANK1
- mtsdram(mem_mcopt1, 0x00000000);
- mtsdram(mem_mb1cf, mb0cf[i].size | mb0cf[i].reg);
- mtsdram(mem_mcopt1, 0x80800000);
+ mtsdram(SDRAM0_CFG, 0x00000000);
+ mtsdram(SDRAM0_B1CR, mb0cf[i].size | mb0cf[i].reg);
+ mtsdram(SDRAM0_CFG, 0x80800000);
udelay(10000);
/*
@@ -228,8 +228,8 @@ phys_size_t initdram(int board_type)
*/
if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) !=
mb0cf[i].size) {
- mtsdram(mem_mb1cf, 0);
- mtsdram(mem_mcopt1, 0);
+ mtsdram(SDRAM0_B1CR, 0);
+ mtsdram(SDRAM0_CFG, 0);
} else {
/*
* We have two identical banks, so the size
@@ -315,7 +315,7 @@ static void sdram_tr1_set(int ram_address, int* tr1_value)
/* go through all possible SDRAM0_TR1[RDCT] values */
for (i=0; i<=0x1ff; i++) {
/* set the current value for TR1 */
- mtsdram(mem_tr1, (0x80800800 | i));
+ mtsdram(SDRAM0_TR1, (0x80800800 | i));
/* write values */
for (j=0; j<NUM_TRIES; j++) {
@@ -383,31 +383,31 @@ phys_size_t initdram(int board_type)
/*
* Disable memory controller.
*/
- mtsdram(mem_cfg0, 0x00000000);
+ mtsdram(SDRAM0_CFG0, 0x00000000);
/*
* Setup some default
*/
- mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
- mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
- mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
- mtsdram(mem_wddctr, CONFIG_SYS_SDRAM0_WDDCTR);
- mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
+ mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
+ mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
+ mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
+ mtsdram(SDRAM0_WDDCTR, CONFIG_SYS_SDRAM0_WDDCTR);
+ mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
- mtsdram(mem_b0cr, mb0cf[i].reg);
- mtsdram(mem_tr0, CONFIG_SYS_SDRAM0_TR0);
- mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
- mtsdram(mem_rtr, CONFIG_SYS_SDRAM0_RTR);
- mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/
+ mtsdram(SDRAM0_B0CR, mb0cf[i].reg);
+ mtsdram(SDRAM0_TR0, CONFIG_SYS_SDRAM0_TR0);
+ mtsdram(SDRAM0_TR1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
+ mtsdram(SDRAM0_RTR, CONFIG_SYS_SDRAM0_RTR);
+ mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM*/
udelay(400); /* Delay 200 usecs (min) */
/*
* Enable the controller, then wait for DCEN to complete
*/
- mtsdram(mem_cfg0, CONFIG_SYS_SDRAM0_CFG0);
+ mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
udelay(10000);
if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
@@ -416,7 +416,7 @@ phys_size_t initdram(int board_type)
* Optimize TR1 to current hardware environment
*/
sdram_tr1_set(0x00000000, &tr1_bank1);
- mtsdram(mem_tr1, (tr1_bank1 | 0x80800800));
+ mtsdram(SDRAM0_TR1, (tr1_bank1 | 0x80800800));
/*
@@ -424,9 +424,9 @@ phys_size_t initdram(int board_type)
* defined (assumes same type as bank 0)
*/
#ifdef CONFIG_SDRAM_BANK1
- mtsdram(mem_cfg0, 0);
- mtsdram(mem_b1cr, mb0cf[i].size | mb0cf[i].reg);
- mtsdram(mem_cfg0, CONFIG_SYS_SDRAM0_CFG0);
+ mtsdram(SDRAM0_CFG0, 0);
+ mtsdram(SDRAM0_B1CR, mb0cf[i].size | mb0cf[i].reg);
+ mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
udelay(10000);
/*
@@ -436,9 +436,9 @@ phys_size_t initdram(int board_type)
*/
if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size)
!= mb0cf[i].size) {
- mtsdram(mem_cfg0, 0);
- mtsdram(mem_b1cr, 0);
- mtsdram(mem_cfg0, CONFIG_SYS_SDRAM0_CFG0);
+ mtsdram(SDRAM0_CFG0, 0);
+ mtsdram(SDRAM0_B1CR, 0);
+ mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
udelay(10000);
} else {
/*
generated by cgit v0.10.2 at 2024-11-03 13:16:21 (GMT)