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Diffstat (limited to 'doc')
| -rw-r--r-- | doc/README.kmeter1 | 91 | ||||
| -rw-r--r-- | doc/README.nios_CONFIG_SYS_NIOS_CPU | 140 | ||||
| -rw-r--r-- | doc/README.simpc8313 | 80 |
3 files changed, 311 insertions, 0 deletions
diff --git a/doc/README.kmeter1 b/doc/README.kmeter1 new file mode 100644 index 0000000..44ebb7a --- /dev/null +++ b/doc/README.kmeter1 @@ -0,0 +1,91 @@ +Keymile kmeter1 Board +----------------------------------------- +1. Alternative Boot EEPROM + + Upon the kmeter1 startup the I2C_1 controller is used to fetch the boot + configuration from a serial EEPROM. During the development and debugging + phase it might be helpful to apply an alternative boot configuration in + a simple way. Therefore it is an alternative boot eeprom on the PIGGY, + which can be activated by setting the "ST" jumper on the PIGGY board. + +2. Memory Map + + BaseAddr PortSz Size Device + ----------- ------ ----- ------ + 0x0000_0000 64 bit 256MB DDR + 0x8000_0000 8 bit 256KB GPIO/PIGGY on CS1 + 0xa000_0000 8 bit 256MB PAXE on CS3 + 0xe000_0000 2MB Int Mem Reg Space + 0xf000_0000 16 bit 256MB FLASH on CS0 + + + DDR-SDRAM: + The current realization is made with four 16-bits memory devices. + Mounting options have been foreseen for device architectures from + 4Mx16 to 512Mx16. The kmeter1 is equipped with four 32Mx16 devices + thus resulting in a total capacity of 256MBytes. + +3. Compilation + + Assuming you're using BASH shell: + + export CROSS_COMPILE=your-cross-compile-prefix + cd u-boot + make distclean + make kmeter1_config + make + +4. Downloading and Flashing Images + +4.0 Download over serial line using Kermit: + + loadb + [Drop to kermit: + ^\c + send <u-boot-bin-image> + c + ] + + + Or via tftp: + + tftp 10000 u-boot.bin + => run load + Using FSL UEC0 device + TFTP from server 192.168.1.1; our IP address is 192.168.205.4 + Filename '/tftpboot/kmeter1/u-boot.bin'. + Load address: 0x200000 + Loading: ############## + done + Bytes transferred = 204204 (31dac hex) + => + +4.1 Reflash U-boot Image using U-boot + + => run update + ..... done + Un-Protected 5 sectors + + ..... done + Erased 5 sectors + Copy to Flash... done + ..... done + Protected 5 sectors + Total of 204204 bytes were the same + Saving Environment to Flash... + . done + Un-Protected 1 sectors + . done + Un-Protected 1 sectors + Erasing Flash... + . done + Erased 1 sectors + Writing to Flash... done + . done + Protected 1 sectors + . done + Protected 1 sectors + => + +5. Notes + 1) The console baudrate for kmeter1 is 115200bps. diff --git a/doc/README.nios_CONFIG_SYS_NIOS_CPU b/doc/README.nios_CONFIG_SYS_NIOS_CPU new file mode 100644 index 0000000..3547c34 --- /dev/null +++ b/doc/README.nios_CONFIG_SYS_NIOS_CPU @@ -0,0 +1,140 @@ + +=============================================================================== + C F G _ N I O S _ C P U _ * v s . N I O S S D K +=============================================================================== + +When ever you have to make a new NIOS CPU configuration you can use this table +as a reference list to the original NIOS SDK symbols made by Alteras SOPC +Builder. Look into excalibur.h and excalibur.s in your SDK path cpu_sdk/inc. +Symbols beginning with a '[ptf]:' are coming from your SOPC sytem description +(PTF file) in sections WIZARD_SCRIPT_ARGUMENTS or SYSTEM_BUILDER_INFO. + +C O R E N I O S S D K [1],[7] +------------------------------------------------------------------------------- +CONFIG_SYS_NIOS_CPU_CLK nasys_clock_freq +CONFIG_SYS_NIOS_CPU_ICACHE nasys_icache_size +CONFIG_SYS_NIOS_CPU_DCACHE nasys_dcache_size +CONFIG_SYS_NIOS_CPU_REG_NUMS nasys_nios_num_regs +CONFIG_SYS_NIOS_CPU_MUL __nios_use_multiply__ +CONFIG_SYS_NIOS_CPU_MSTEP __nios_use_mstep__ +CONFIG_SYS_NIOS_CPU_STACK nasys_stack_top +CONFIG_SYS_NIOS_CPU_VEC_BASE nasys_vector_table +CONFIG_SYS_NIOS_CPU_VEC_SIZE nasys_vector_table_size +CONFIG_SYS_NIOS_CPU_VEC_NUMS +CONFIG_SYS_NIOS_CPU_RST_VECT nasys_reset_address +CONFIG_SYS_NIOS_CPU_DBG_CORE nasys_debug_core +CONFIG_SYS_NIOS_CPU_RAM_BASE na_onchip_ram_64_kbytes +CONFIG_SYS_NIOS_CPU_RAM_SIZE na_onchip_ram_64_kbytes_size +CONFIG_SYS_NIOS_CPU_ROM_BASE na_boot_monitor_rom +CONFIG_SYS_NIOS_CPU_ROM_SIZE na_boot_monitor_rom_size +CONFIG_SYS_NIOS_CPU_OCI_BASE nasys_oci_core +CONFIG_SYS_NIOS_CPU_OCI_SIZE +CONFIG_SYS_NIOS_CPU_SRAM_BASE na_ext_ram nasys_program_mem + nasys_data_mem +CONFIG_SYS_NIOS_CPU_SRAM_SIZE na_ext_ram_size nasys_program_mem_size + nasys_data_mem_size +CONFIG_SYS_NIOS_CPU_SDRAM_BASE na_sdram +CONFIG_SYS_NIOS_CPU_SDRAM_SIZE na_sdram_size +CONFIG_SYS_NIOS_CPU_FLASH_BASE na_ext_flash nasys_main_flash + nasys_am29lv065d_flash_0 + nasys_flash_0 +CONFIG_SYS_NIOS_CPU_FLASH_SIZE na_ext_flash_size nasys_main_flash_size + +T I M E R N I O S S D K [3] +------------------------------------------------------------------------------- +CONFIG_SYS_NIOS_CPU_TIMER_NUMS nasys_timer_count +CONFIG_SYS_NIOS_CPU_TIMER[0-9] nasys_timer_[0-9] +CONFIG_SYS_NIOS_CPU_TIMER[0-9]_IRQ nasys_timer_[0-9]_irq +CONFIG_SYS_NIOS_CPU_TIMER[0-9]_PER [ptf]:period + [ptf]:period_units + [ptf]:mult +CONFIG_SYS_NIOS_CPU_TIMER[0-9]_AR [ptf]:always_run +CONFIG_SYS_NIOS_CPU_TIMER[0-9]_FP [ptf]:fixed_period +CONFIG_SYS_NIOS_CPU_TIMER[0-9]_SS [ptf]:snapshot + +U A R T N I O S S D K [2] +------------------------------------------------------------------------------- +CONFIG_SYS_NIOS_CPU_UART_NUMS nasys_uart_count +CONFIG_SYS_NIOS_CPU_UART[0-9] nasys_uart_[0-9] +CONFIG_SYS_NIOS_CPU_UART[0-9]_IRQ nasys_uart_[0-9]_irq +CONFIG_SYS_NIOS_CPU_UART[0-9]_BR [ptf]:baud +CONFIG_SYS_NIOS_CPU_UART[0-9]_DB [ptf]:data_bits +CONFIG_SYS_NIOS_CPU_UART[0-9]_SB [ptf]:stop_bits +CONFIG_SYS_NIOS_CPU_UART[0-9]_PA [ptf]:parity +CONFIG_SYS_NIOS_CPU_UART[0-9]_HS [ptf]:use_cts_rts +CONFIG_SYS_NIOS_CPU_UART[0-9]_EOP [ptf]:use_eop_register + +P I O N I O S S D K [4] +------------------------------------------------------------------------------- +CONFIG_SYS_NIOS_CPU_PIO_NUMS nasys_pio_count +CONFIG_SYS_NIOS_CPU_PIO[0-9] nasys_pio_[0-9] +CONFIG_SYS_NIOS_CPU_PIO[0-9]_IRQ nasys_pio_[0-9]_irq +CONFIG_SYS_NIOS_CPU_PIO[0-9]_BITS [ptf]:Data_Width +CONFIG_SYS_NIOS_CPU_PIO[0-9]_TYPE [ptf]:has_tri + [ptf]:has_out + [ptf]:has_in +CONFIG_SYS_NIOS_CPU_PIO[0-9]_CAP [ptf]:capture +CONFIG_SYS_NIOS_CPU_PIO[0-9]_EDGE [ptf]:edge_type +CONFIG_SYS_NIOS_CPU_PIO[0-9]_ITYPE [ptf]:irq_type + +S P I N I O S S D K [6] +------------------------------------------------------------------------------- +CONFIG_SYS_NIOS_CPU_SPI_NUMS nasys_spi_count +CONFIG_SYS_NIOS_CPU_SPI[0-9] nasys_spi_[0-9] +CONFIG_SYS_NIOS_CPU_SPI[0-9]_IRQ nasys_spi_[0-9]_irq +CONFIG_SYS_NIOS_CPU_SPI[0-9]_BITS [ptf]:databits +CONFIG_SYS_NIOS_CPU_SPI[0-9]_MA [ptf]:ismaster +CONFIG_SYS_NIOS_CPU_SPI[0-9]_SLN [ptf]:numslaves +CONFIG_SYS_NIOS_CPU_SPI[0-9]_TCLK [ptf]:targetclock +CONFIG_SYS_NIOS_CPU_SPI[0-9]_TDELAY [ptf]:targetdelay +CONFIG_SYS_NIOS_CPU_SPI[0-9]_* [ptf]:* + +I D E N I O S S D K +------------------------------------------------------------------------------- +CONFIG_SYS_NIOS_CPU_IDE_NUMS nasys_usersocket_count +CONFIG_SYS_NIOS_CPU_IDE[0-9] nasys_usersocket_[0-9] + +A S M I N I O S S D K [5] +------------------------------------------------------------------------------- +CONFIG_SYS_NIOS_CPU_ASMI_NUMS nasys_asmi_count +CONFIG_SYS_NIOS_CPU_ASMI[0-9] nasys_asmi_[0-9] +CONFIG_SYS_NIOS_CPU_ASMI[0-9]_IRQ nasys_asmi_[0-9]_irq + +E t h e r n e t ( L A N ) N I O S S D K +------------------------------------------------------------------------------- +CONFIG_SYS_NIOS_CPU_LAN_NUMS +CONFIG_SYS_NIOS_CPU_LAN[0-9]_BASE na_lan91c111 +CONFIG_SYS_NIOS_CPU_LAN[0-9]_OFFS LAN91C111_REGISTERS_OFFSET +CONFIG_SYS_NIOS_CPU_LAN[0-9]_IRQ na_lan91c111_irq +CONFIG_SYS_NIOS_CPU_LAN[0-9]_BUSW LAN91C111_DATA_BUS_WIDTH +CONFIG_SYS_NIOS_CPU_LAN[0-9]_TYPE + +s y s t e m c o m p o s i n g N I O S S D K +------------------------------------------------------------------------------- +CONFIG_SYS_NIOS_CPU_TICK_TIMER (na_low_priority_timer2) +CONFIG_SYS_NIOS_CPU_USER_TIMER (na_timer1) +CONFIG_SYS_NIOS_CPU_BUTTON_PIO (na_button_pio) +CONFIG_SYS_NIOS_CPU_LCD_PIO (na_lcd_pio) +CONFIG_SYS_NIOS_CPU_LED_PIO (na_led_pio) +CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO (na_seven_seg_pio) +CONFIG_SYS_NIOS_CPU_RECONF_PIO (na_reconfig_request_pio) +CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO (na_cf_present_pio) +CONFIG_SYS_NIOS_CPU_CFPOWER_PIO (na_cf_power_pio) +CONFIG_SYS_NIOS_CPU_CFATASEL_PIO (na_cf_ata_select_pio) +CONFIG_SYS_NIOS_CPU_USER_SPI (na_spi) + + +=============================================================================== + R E F E R E N C E S +=============================================================================== +[1] http://www.altera.com/literature/ds/ds_nioscpu.pdf +[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf +[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf +[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf +[5] http://www.altera.com/literature/ds/ds_nios_asmi.pdf +[6] http://www.altera.com/literature/ds/ds_nios_spi.pdf +[7] http://www.altera.com/literature/ds/ds_legacy_sdram_ctrl.pdf + + +=============================================================================== +Stephan Linz <linz@li-pro.net> diff --git a/doc/README.simpc8313 b/doc/README.simpc8313 new file mode 100644 index 0000000..b362c6a --- /dev/null +++ b/doc/README.simpc8313 @@ -0,0 +1,80 @@ +Sheldon Instruments SIMPC8313 Board +----------------------------------------- + +1. Board Switches and Jumpers + + S2 is used to set CFG_RESET_SOURCE. + + To boot the image in Large page NAND flash, use these DIP + switch settings for S2: + + +----------+ ON + | * * **** | + | * * | + +----------+ + 12345678 + + To boot the image in Small page NAND flash, use these DIP + switch settings for S2: + + +----------+ ON + | *** **** | + | * | + +----------+ + 12345678 + (where the '*' indicates the position of the tab of the switch.) + +2. Memory Map + The memory map looks like this: + + 0x0000_0000 0x1fff_ffff DDR 512M + 0x8000_0000 0x8fff_ffff PCI MEM 256M + 0x9000_0000 0x9fff_ffff PCI_MMIO 256M + 0xe000_0000 0xe00f_ffff IMMR 1M + 0xe200_0000 0xe20f_ffff PCI IO 16M + 0xe280_0000 0xe280_7fff NAND FLASH (CS0) 32K + or + 0xe280_0000 0xe281_ffff NAND FLASH (CS0) 128K + 0xff00_0000 0xff00_7fff FPGA (CS1) 1M + +3. Compilation + + Assuming you're using BASH (or similar) as your shell: + + export CROSS_COMPILE=your-cross-compiler-prefix- + make distclean + make SIMPC8313_LP_config + (or make SIMPC8313_SP_config, depending on the page size + of your NAND flash) + make + +4. Downloading and Flashing Images + +4.1 Reflash U-boot Image using U-boot + + =>run update_uboot + + You may want to try + =>tftp $loadaddr $uboot + first, to make sure that the TFTP load will succeed before it + goes ahead and wipes out your current firmware. And of course, + if the new u-boot doesn't boot, you can plug the board into + your PCI slot and with the supplied driver and sample app + you can reburn a working u-boot. + +4.2 Downloading and Booting Linux Kernel + + Ensure that all networking-related environment variables are set + properly (including ipaddr, serverip, gatewayip (if needed), + netmask, ethaddr, eth1addr, fdtfile, and bootfile). + + =>tftp $loadaddr uImage + =>nand write $loadaddr kernel $filesize + =>tftp $loadaddr $fdtfile + =>nand write $loadaddr 7e0000 1800 + + =>boot + +5 Notes + + The console baudrate for SIMPC8313 is 115200bps. |