diff options
Diffstat (limited to 'drivers/clk')
29 files changed, 670 insertions, 178 deletions
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c index ccf47a1..c2efdda 100644 --- a/drivers/clk/aspeed/clk_ast2500.c +++ b/drivers/clk/aspeed/clk_ast2500.c @@ -429,7 +429,7 @@ static int ast2500_clk_probe(struct udevice *dev) { struct ast2500_clk_priv *priv = dev_get_priv(dev); - priv->scu = dev_get_addr_ptr(dev); + priv->scu = devfdt_get_addr_ptr(dev); if (IS_ERR(priv->scu)) return PTR_ERR(priv->scu); diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c index ac27d3e..8c9a3cb 100644 --- a/drivers/clk/at91/clk-generated.c +++ b/drivers/clk/at91/clk-generated.c @@ -7,7 +7,7 @@ #include <common.h> #include <clk-uclass.h> -#include <dm/device.h> +#include <dm.h> #include <linux/io.h> #include <mach/at91_pmc.h> #include "pmc.h" diff --git a/drivers/clk/at91/clk-h32mx.c b/drivers/clk/at91/clk-h32mx.c index 1a304ba..dcc64fb 100644 --- a/drivers/clk/at91/clk-h32mx.c +++ b/drivers/clk/at91/clk-h32mx.c @@ -7,7 +7,7 @@ #include <common.h> #include <clk-uclass.h> -#include <dm/device.h> +#include <dm.h> #include <dm/util.h> #include <linux/io.h> #include <mach/at91_pmc.h> diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c index 252d076..a234ce8 100644 --- a/drivers/clk/at91/clk-main.c +++ b/drivers/clk/at91/clk-main.c @@ -7,7 +7,7 @@ #include <common.h> #include <clk-uclass.h> -#include <dm/device.h> +#include <dm.h> #include <linux/io.h> #include <mach/at91_pmc.h> #include "pmc.h" diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index 72d0a73..6bc78ba 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -7,7 +7,7 @@ #include <common.h> #include <clk-uclass.h> -#include <dm/device.h> +#include <dm.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c index 62fabe3..212a30b 100644 --- a/drivers/clk/at91/clk-peripheral.c +++ b/drivers/clk/at91/clk-peripheral.c @@ -7,7 +7,7 @@ #include <common.h> #include <clk-uclass.h> -#include <dm/device.h> +#include <dm.h> #include <linux/io.h> #include <mach/at91_pmc.h> #include "pmc.h" diff --git a/drivers/clk/at91/clk-plla.c b/drivers/clk/at91/clk-plla.c index 2a71399..f5b2ca1 100644 --- a/drivers/clk/at91/clk-plla.c +++ b/drivers/clk/at91/clk-plla.c @@ -7,7 +7,7 @@ #include <common.h> #include <clk-uclass.h> -#include <dm/device.h> +#include <dm.h> #include <linux/io.h> #include <mach/at91_pmc.h> #include "pmc.h" diff --git a/drivers/clk/at91/clk-slow.c b/drivers/clk/at91/clk-slow.c index f7666b4..f18f002 100644 --- a/drivers/clk/at91/clk-slow.c +++ b/drivers/clk/at91/clk-slow.c @@ -7,7 +7,7 @@ #include <common.h> #include <clk-uclass.h> -#include <dm/device.h> +#include <dm.h> static int at91_slow_clk_enable(struct clk *clk) { diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c index 5b59a0c..24b271a 100644 --- a/drivers/clk/at91/clk-system.c +++ b/drivers/clk/at91/clk-system.c @@ -7,7 +7,7 @@ #include <common.h> #include <clk-uclass.h> -#include <dm/device.h> +#include <dm.h> #include <linux/io.h> #include <mach/at91_pmc.h> #include "pmc.h" diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c index 369a687..af5362d 100644 --- a/drivers/clk/at91/clk-utmi.c +++ b/drivers/clk/at91/clk-utmi.c @@ -7,7 +7,7 @@ #include <common.h> #include <clk-uclass.h> -#include <dm/device.h> +#include <dm.h> #include <linux/io.h> #include <mach/at91_pmc.h> #include "pmc.h" diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c index 72d52c5..be1d11e 100644 --- a/drivers/clk/at91/pmc.c +++ b/drivers/clk/at91/pmc.c @@ -7,9 +7,8 @@ #include <common.h> #include <clk-uclass.h> -#include <dm/device.h> +#include <dm.h> #include <dm/lists.h> -#include <dm/root.h> #include <dm/util.h> #include "pmc.h" @@ -40,7 +39,7 @@ int at91_pmc_core_probe(struct udevice *dev) dev = dev_get_parent(dev); - plat->reg_base = (struct at91_pmc *)dev_get_addr_ptr(dev); + plat->reg_base = (struct at91_pmc *)devfdt_get_addr_ptr(dev); return 0; } @@ -80,7 +79,7 @@ int at91_clk_sub_device_bind(struct udevice *dev, const char *drv_name) if (!name) return -EINVAL; ret = device_bind_driver_to_node(dev, drv_name, name, - offset, NULL); + offset_to_ofnode(offset), NULL); if (ret) return ret; } @@ -88,7 +87,7 @@ int at91_clk_sub_device_bind(struct udevice *dev, const char *drv_name) return 0; } -int at91_clk_of_xlate(struct clk *clk, struct fdtdec_phandle_args *args) +int at91_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) { int periph; @@ -115,7 +114,7 @@ int at91_clk_probe(struct udevice *dev) dev_periph_container = dev_get_parent(dev); dev_pmc = dev_get_parent(dev_periph_container); - plat->reg_base = (struct at91_pmc *)dev_get_addr_ptr(dev_pmc); + plat->reg_base = (struct at91_pmc *)devfdt_get_addr_ptr(dev_pmc); return 0; } diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index f222fce..bd3caba 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -15,7 +15,7 @@ struct pmc_platdata { int at91_pmc_core_probe(struct udevice *dev); int at91_clk_sub_device_bind(struct udevice *dev, const char *drv_name); -int at91_clk_of_xlate(struct clk *clk, struct fdtdec_phandle_args *args); +int at91_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args); int at91_clk_probe(struct udevice *dev); #endif diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c index 6035e20..0c08812 100644 --- a/drivers/clk/at91/sckc.c +++ b/drivers/clk/at91/sckc.c @@ -6,8 +6,7 @@ */ #include <common.h> -#include <dm/device.h> -#include <dm/root.h> +#include <dm.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 6fcfd69..83b6328 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -38,7 +38,7 @@ int clk_get_by_index_platdata(struct udevice *dev, int index, } # else static int clk_of_xlate_default(struct clk *clk, - struct fdtdec_phandle_args *args) + struct ofnode_phandle_args *args) { debug("%s(clk=%p)\n", __func__, clk); @@ -58,23 +58,22 @@ static int clk_of_xlate_default(struct clk *clk, int clk_get_by_index(struct udevice *dev, int index, struct clk *clk) { int ret; - struct fdtdec_phandle_args args; + struct ofnode_phandle_args args; struct udevice *dev_clk; struct clk_ops *ops; debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk); assert(clk); - ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev), - "clocks", "#clock-cells", 0, index, - &args); + ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0, + index, &args); if (ret) { debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n", __func__, ret); return ret; } - ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &dev_clk); + ret = uclass_get_device_by_ofnode(UCLASS_CLK, args.node, &dev_clk); if (ret) { debug("%s: uclass_get_device_by_of_offset failed: err=%d\n", __func__, ret); @@ -104,8 +103,7 @@ int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk) debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk); - index = fdt_stringlist_search(gd->fdt_blob, dev_of_offset(dev), - "clock-names", name); + index = dev_read_stringlist_search(dev, "clock-names", name); if (index < 0) { debug("fdt_stringlist_search() failed: %d\n", index); return index; diff --git a/drivers/clk/clk_bcm6345.c b/drivers/clk/clk_bcm6345.c index 4c7a2df..93603fa 100644 --- a/drivers/clk/clk_bcm6345.c +++ b/drivers/clk/clk_bcm6345.c @@ -59,7 +59,7 @@ static int bcm63xx_clk_probe(struct udevice *dev) fdt_addr_t addr; fdt_size_t size; - addr = dev_get_addr_size_index(dev, 0, &size); + addr = devfdt_get_addr_size_index(dev, 0, &size); if (addr == FDT_ADDR_T_NONE) return -EINVAL; diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c index 3911bf6..63565b6 100644 --- a/drivers/clk/clk_fixed_rate.c +++ b/drivers/clk/clk_fixed_rate.c @@ -6,7 +6,7 @@ #include <common.h> #include <clk-uclass.h> -#include <dm/device.h> +#include <dm.h> DECLARE_GLOBAL_DATA_PTR; @@ -31,9 +31,8 @@ const struct clk_ops clk_fixed_rate_ops = { static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev) { #if !CONFIG_IS_ENABLED(OF_PLATDATA) - to_clk_fixed_rate(dev)->fixed_rate = - fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "clock-frequency", 0); + to_clk_fixed_rate(dev)->fixed_rate = dev_read_u32_default(dev, + "clock-frequency", 0); #endif return 0; diff --git a/drivers/clk/clk_stm32f7.c b/drivers/clk/clk_stm32f7.c index da3c204..fcdc3c0 100644 --- a/drivers/clk/clk_stm32f7.c +++ b/drivers/clk/clk_stm32f7.c @@ -252,8 +252,7 @@ static int stm32_clk_probe(struct udevice *dev) return 0; } -static int stm32_clk_of_xlate(struct clk *clk, - struct fdtdec_phandle_args *args) +static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) { debug("%s(clk=%p)\n", __func__, clk); diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c index 6edc4dc..50f2a65 100644 --- a/drivers/clk/clk_zynq.c +++ b/drivers/clk/clk_zynq.c @@ -459,14 +459,14 @@ static int zynq_clk_probe(struct udevice *dev) for (i = 0; i < 2; i++) { sprintf(name, "gem%d_emio_clk", i); ret = clk_get_by_name(dev, name, &priv->gem_emio_clk[i]); - if (ret < 0 && ret != -FDT_ERR_NOTFOUND) { + if (ret < 0 && ret != -ENODATA) { dev_err(dev, "failed to get %s clock\n", name); return ret; } } #endif - priv->ps_clk_freq = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, + priv->ps_clk_freq = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), "ps-clk-frequency", 33333333UL); return 0; diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index 694274d..50eaf31 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -9,8 +9,8 @@ #include <common.h> #include <linux/bitops.h> #include <clk-uclass.h> -#include <dm/device.h> #include <clk.h> +#include <dm.h> #define ZYNQMP_GEM0_REF_CTRL 0xFF5E0050 #define ZYNQMP_IOPLL_CTRL 0xFF5E0020 diff --git a/drivers/clk/exynos/clk-exynos7420.c b/drivers/clk/exynos/clk-exynos7420.c index 1f017a3..e34945d 100644 --- a/drivers/clk/exynos/clk-exynos7420.c +++ b/drivers/clk/exynos/clk-exynos7420.c @@ -98,7 +98,7 @@ static int exynos7420_clk_topc_probe(struct udevice *dev) fdt_addr_t base; int ret; - base = dev_get_addr(dev); + base = devfdt_get_addr(dev); if (base == FDT_ADDR_T_NONE) return -EINVAL; @@ -152,7 +152,7 @@ static int exynos7420_clk_top0_probe(struct udevice *dev) if (!priv) return -EINVAL; - base = dev_get_addr(dev); + base = devfdt_get_addr(dev); if (base == FDT_ADDR_T_NONE) return -EINVAL; diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index 1091a76..e404c0c 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -8,4 +8,6 @@ obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o +obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o +obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c index d866d0b..5ecf512 100644 --- a/drivers/clk/rockchip/clk_rk3036.c +++ b/drivers/clk/rockchip/clk_rk3036.c @@ -40,7 +40,7 @@ enum { #hz "Hz cannot be hit with PLL "\ "divisors on line " __stringify(__LINE__)); -/* use interge mode*/ +/* use integer mode*/ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); @@ -61,16 +61,15 @@ static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id, assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); - /* use interger mode */ - rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); + /* use integer mode */ + rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); rk_clrsetreg(&pll->con0, - PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK, + PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); - rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT | - PLL_REFDIV_MASK << PLL_REFDIV_SHIFT, - (div->postdiv2 << PLL_POSTDIV2_SHIFT | - div->refdiv << PLL_REFDIV_SHIFT)); + rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, + (div->postdiv2 << PLL_POSTDIV2_SHIFT | + div->refdiv << PLL_REFDIV_SHIFT)); /* waiting for pll lock */ while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) @@ -87,8 +86,7 @@ static void rkclk_init(struct rk3036_cru *cru) /* pll enter slow-mode */ rk_clrsetreg(&cru->cru_mode_con, - GPLL_MODE_MASK << GPLL_MODE_SHIFT | - APLL_MODE_MASK << APLL_MODE_SHIFT, + GPLL_MODE_MASK | APLL_MODE_MASK, GPLL_MODE_SLOW << GPLL_MODE_SHIFT | APLL_MODE_SLOW << APLL_MODE_SHIFT); @@ -97,8 +95,8 @@ static void rkclk_init(struct rk3036_cru *cru) rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); /* - * select apll as core clock pll source and - * set up dependent divisors for PCLK/HCLK and ACLK clocks. + * select apll as cpu/core clock pll source and + * set up dependent divisors for PERI and ACLK clocks. * core hz : apll = 1:1 */ aclk_div = APLL_HZ / CORE_ACLK_HZ - 1; @@ -108,44 +106,40 @@ static void rkclk_init(struct rk3036_cru *cru) assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf); rk_clrsetreg(&cru->cru_clksel_con[0], - CORE_CLK_PLL_SEL_MASK << CORE_CLK_PLL_SEL_SHIFT | - CORE_DIV_CON_MASK << CORE_DIV_CON_SHIFT, + CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK, CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | 0 << CORE_DIV_CON_SHIFT); rk_clrsetreg(&cru->cru_clksel_con[1], - CORE_ACLK_DIV_MASK << CORE_ACLK_DIV_SHIFT | - CORE_PERI_DIV_MASK << CORE_PERI_DIV_SHIFT, + CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK, aclk_div << CORE_ACLK_DIV_SHIFT | pclk_div << CORE_PERI_DIV_SHIFT); /* - * select apll as cpu clock pll source and + * select apll as pd_bus bus clock source and * set up dependent divisors for PCLK/HCLK and ACLK clocks. */ - aclk_div = APLL_HZ / CPU_ACLK_HZ - 1; - assert((aclk_div + 1) * CPU_ACLK_HZ == APLL_HZ && aclk_div < 0x1f); + aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; + assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); - pclk_div = APLL_HZ / CPU_PCLK_HZ - 1; - assert((pclk_div + 1) * CPU_PCLK_HZ == APLL_HZ && pclk_div < 0x7); + pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; + assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); - hclk_div = APLL_HZ / CPU_HCLK_HZ - 1; - assert((hclk_div + 1) * CPU_HCLK_HZ == APLL_HZ && hclk_div < 0x3); + hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; + assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); rk_clrsetreg(&cru->cru_clksel_con[0], - CPU_CLK_PLL_SEL_MASK << CPU_CLK_PLL_SEL_SHIFT | - ACLK_CPU_DIV_MASK << ACLK_CPU_DIV_SHIFT, - CPU_CLK_PLL_SEL_APLL << CPU_CLK_PLL_SEL_SHIFT | - aclk_div << ACLK_CPU_DIV_SHIFT); + BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK, + BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT | + aclk_div << BUS_ACLK_DIV_SHIFT); rk_clrsetreg(&cru->cru_clksel_con[1], - CPU_PCLK_DIV_MASK << CPU_PCLK_DIV_SHIFT | - CPU_HCLK_DIV_MASK << CPU_HCLK_DIV_SHIFT, - pclk_div << CPU_PCLK_DIV_SHIFT | - hclk_div << CPU_HCLK_DIV_SHIFT); + BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK, + pclk_div << BUS_PCLK_DIV_SHIFT | + hclk_div << BUS_HCLK_DIV_SHIFT); /* - * select gpll as peri clock pll source and + * select gpll as pd_peri bus clock source and * set up dependent divisors for PCLK/HCLK and ACLK clocks. */ aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; @@ -153,17 +147,15 @@ static void rkclk_init(struct rk3036_cru *cru) hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); assert((1 << hclk_div) * PERI_HCLK_HZ == - PERI_ACLK_HZ && (pclk_div < 0x4)); + PERI_ACLK_HZ && (hclk_div < 0x4)); pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); assert((1 << pclk_div) * PERI_PCLK_HZ == PERI_ACLK_HZ && pclk_div < 0x8); rk_clrsetreg(&cru->cru_clksel_con[10], - PERI_PLL_SEL_MASK << PERI_PLL_SEL_SHIFT | - PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT | - PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT | - PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT, + PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK | + PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK, PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | pclk_div << PERI_PCLK_DIV_SHIFT | hclk_div << PERI_HCLK_DIV_SHIFT | @@ -171,8 +163,7 @@ static void rkclk_init(struct rk3036_cru *cru) /* PLL enter normal-mode */ rk_clrsetreg(&cru->cru_mode_con, - GPLL_MODE_MASK << GPLL_MODE_SHIFT | - APLL_MODE_MASK << APLL_MODE_SHIFT, + GPLL_MODE_MASK | APLL_MODE_MASK, GPLL_MODE_NORM << GPLL_MODE_SHIFT | APLL_MODE_NORM << APLL_MODE_SHIFT); } @@ -189,9 +180,9 @@ static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru, 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff, GPLL_MODE_SHIFT, 0xff }; - static u8 clk_mask[CLK_COUNT] = { - 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff, - GPLL_MODE_MASK, 0xff + static u32 clk_mask[CLK_COUNT] = { + 0xffffffff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xffffffff, + GPLL_MODE_MASK, 0xffffffff }; uint shift; uint mask; @@ -200,18 +191,18 @@ static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru, shift = clk_shift[clk_id]; mask = clk_mask[clk_id]; - switch ((con >> shift) & mask) { + switch ((con & mask) >> shift) { case GPLL_MODE_SLOW: return OSC_HZ; case GPLL_MODE_NORM: /* normal mode */ con = readl(&pll->con0); - postdiv1 = (con >> PLL_POSTDIV1_SHIFT) & PLL_POSTDIV1_MASK; - fbdiv = (con >> PLL_FBDIV_SHIFT) & PLL_FBDIV_MASK; + postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; + fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; con = readl(&pll->con1); - postdiv2 = (con >> PLL_POSTDIV2_SHIFT) & PLL_POSTDIV2_MASK; - refdiv = (con >> PLL_REFDIV_SHIFT) & PLL_REFDIV_MASK; + postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; + refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; case GPLL_MODE_DEEP: default: @@ -230,14 +221,14 @@ static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate, case HCLK_EMMC: case SCLK_EMMC: con = readl(&cru->cru_clksel_con[12]); - mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK; - div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK; + mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; + div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; break; case HCLK_SDIO: case SCLK_SDIO: con = readl(&cru->cru_clksel_con[12]); - mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK; - div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK; + mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; + div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; break; default: return -EINVAL; @@ -269,16 +260,14 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate, case HCLK_EMMC: case SCLK_EMMC: rk_clrsetreg(&cru->cru_clksel_con[12], - EMMC_PLL_MASK << EMMC_PLL_SHIFT | - EMMC_DIV_MASK << EMMC_DIV_SHIFT, + EMMC_PLL_MASK | EMMC_DIV_MASK, mux << EMMC_PLL_SHIFT | (src_clk_div - 1) << EMMC_DIV_SHIFT); break; case HCLK_SDIO: case SCLK_SDIO: rk_clrsetreg(&cru->cru_clksel_con[11], - MMC0_PLL_MASK << MMC0_PLL_SHIFT | - MMC0_DIV_MASK << MMC0_DIV_SHIFT, + MMC0_PLL_MASK | MMC0_DIV_MASK, mux << MMC0_PLL_SHIFT | (src_clk_div - 1) << MMC0_DIV_SHIFT); break; @@ -331,7 +320,7 @@ static int rk3036_clk_probe(struct udevice *dev) { struct rk3036_clk_priv *priv = dev_get_priv(dev); - priv->cru = (struct rk3036_cru *)dev_get_addr(dev); + priv->cru = (struct rk3036_cru *)devfdt_get_addr(dev); rkclk_init(priv->cru); return 0; diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c index b32491d..6f30332 100644 --- a/drivers/clk/rockchip/clk_rk3188.c +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -542,7 +542,7 @@ static int rk3188_clk_ofdata_to_platdata(struct udevice *dev) #if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3188_clk_priv *priv = dev_get_priv(dev); - priv->cru = (struct rk3188_cru *)dev_get_addr(dev); + priv->cru = (struct rk3188_cru *)devfdt_get_addr(dev); #endif return 0; diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index fc369dd..792ee76 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -59,14 +59,14 @@ enum { PLL_RESET_SHIFT = 5, /* CLKSEL0 */ - CORE_SEL_PLL_MASK = 1, CORE_SEL_PLL_SHIFT = 15, - A17_DIV_MASK = 0x1f, + CORE_SEL_PLL_MASK = 1 << CORE_SEL_PLL_SHIFT, A17_DIV_SHIFT = 8, - MP_DIV_MASK = 0xf, + A17_DIV_MASK = 0x1f << A17_DIV_SHIFT, MP_DIV_SHIFT = 4, - M0_DIV_MASK = 0xf, + MP_DIV_MASK = 0xf << MP_DIV_SHIFT, M0_DIV_SHIFT = 0, + M0_DIV_MASK = 0xf << M0_DIV_SHIFT, /* CLKSEL1: pd bus clk pll sel: codec or general */ PD_BUS_SEL_PLL_MASK = 15, @@ -75,41 +75,41 @@ enum { /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */ PD_BUS_PCLK_DIV_SHIFT = 12, - PD_BUS_PCLK_DIV_MASK = 7, + PD_BUS_PCLK_DIV_MASK = 7 << PD_BUS_PCLK_DIV_SHIFT, /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */ PD_BUS_HCLK_DIV_SHIFT = 8, - PD_BUS_HCLK_DIV_MASK = 3, + PD_BUS_HCLK_DIV_MASK = 3 << PD_BUS_HCLK_DIV_SHIFT, /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */ PD_BUS_ACLK_DIV0_SHIFT = 3, - PD_BUS_ACLK_DIV0_MASK = 0x1f, + PD_BUS_ACLK_DIV0_MASK = 0x1f << PD_BUS_ACLK_DIV0_SHIFT, PD_BUS_ACLK_DIV1_SHIFT = 0, - PD_BUS_ACLK_DIV1_MASK = 0x7, + PD_BUS_ACLK_DIV1_MASK = 0x7 << PD_BUS_ACLK_DIV1_SHIFT, /* * CLKSEL10 * peripheral bus pclk div: * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1 */ - PERI_SEL_PLL_MASK = 1, PERI_SEL_PLL_SHIFT = 15, + PERI_SEL_PLL_MASK = 1 << PERI_SEL_PLL_SHIFT, PERI_SEL_CPLL = 0, PERI_SEL_GPLL, PERI_PCLK_DIV_SHIFT = 12, - PERI_PCLK_DIV_MASK = 3, + PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */ PERI_HCLK_DIV_SHIFT = 8, - PERI_HCLK_DIV_MASK = 3, + PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, /* * peripheral bus aclk div: * aclk_periph = periph_clk_src / (peri_aclk_div_con + 1) */ PERI_ACLK_DIV_SHIFT = 0, - PERI_ACLK_DIV_MASK = 0x1f, + PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, SOCSTS_DPLL_LOCK = 1 << 5, SOCSTS_APLL_LOCK = 1 << 6, @@ -131,10 +131,8 @@ enum { /* Keep divisors as low as possible to reduce jitter and power usage */ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1); -#ifdef CONFIG_SPL_BUILD static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); -#endif static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, const struct pll_div *div) @@ -154,8 +152,7 @@ static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, /* enter reset */ rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); - rk_clrsetreg(&pll->con0, - CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK, + rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK, ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); @@ -198,7 +195,7 @@ static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf, } /* pll enter slow-mode */ - rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, + rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, DPLL_MODE_SLOW << DPLL_MODE_SHIFT); rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]); @@ -208,7 +205,7 @@ static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf, udelay(1); /* PLL enter normal-mode */ - rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, + rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, DPLL_MODE_NORMAL << DPLL_MODE_SHIFT); return 0; @@ -296,7 +293,7 @@ static int rockchip_mac_set_clk(struct rk3288_cru *cru, { /* Assuming mac_clk is fed by an external clock */ rk_clrsetreg(&cru->cru_clksel_con[21], - RMII_EXTCLK_MASK << RMII_EXTCLK_SHIFT, + RMII_EXTCLK_MASK, RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT); return 0; @@ -313,7 +310,7 @@ static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf, if (ret) return ret; - rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT, + rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, NPLL_MODE_SLOW << NPLL_MODE_SHIFT); rkclk_set_pll(cru, CLK_NEW, &npll_config); @@ -324,7 +321,7 @@ static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf, udelay(1); } - rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT, + rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, NPLL_MODE_NORMAL << NPLL_MODE_SHIFT); /* vop dclk source clk: npll,dclk_div: 1 */ @@ -341,9 +338,8 @@ static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf, return 0; } -#endif +#endif /* CONFIG_SPL_BUILD */ -#ifdef CONFIG_SPL_BUILD static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) { u32 aclk_div; @@ -352,8 +348,7 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) /* pll enter slow-mode */ rk_clrsetreg(&cru->cru_mode_con, - GPLL_MODE_MASK << GPLL_MODE_SHIFT | - CPLL_MODE_MASK << CPLL_MODE_SHIFT, + GPLL_MODE_MASK | CPLL_MODE_MASK, GPLL_MODE_SLOW << GPLL_MODE_SHIFT | CPLL_MODE_SLOW << CPLL_MODE_SHIFT); @@ -382,10 +377,8 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) PD_BUS_ACLK_HZ && pclk_div < 0x7); rk_clrsetreg(&cru->cru_clksel_con[1], - PD_BUS_PCLK_DIV_MASK << PD_BUS_PCLK_DIV_SHIFT | - PD_BUS_HCLK_DIV_MASK << PD_BUS_HCLK_DIV_SHIFT | - PD_BUS_ACLK_DIV0_MASK << PD_BUS_ACLK_DIV0_SHIFT | - PD_BUS_ACLK_DIV1_MASK << PD_BUS_ACLK_DIV1_SHIFT, + PD_BUS_PCLK_DIV_MASK | PD_BUS_HCLK_DIV_MASK | + PD_BUS_ACLK_DIV0_MASK | PD_BUS_ACLK_DIV1_MASK, pclk_div << PD_BUS_PCLK_DIV_SHIFT | hclk_div << PD_BUS_HCLK_DIV_SHIFT | aclk_div << PD_BUS_ACLK_DIV0_SHIFT | @@ -407,9 +400,8 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) PERI_ACLK_HZ && (pclk_div < 0x4)); rk_clrsetreg(&cru->cru_clksel_con[10], - PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT | - PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT | - PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT, + PERI_PCLK_DIV_MASK | PERI_HCLK_DIV_MASK | + PERI_ACLK_DIV_MASK, PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT | pclk_div << PERI_PCLK_DIV_SHIFT | hclk_div << PERI_HCLK_DIV_SHIFT | @@ -417,18 +409,15 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) /* PLL enter normal-mode */ rk_clrsetreg(&cru->cru_mode_con, - GPLL_MODE_MASK << GPLL_MODE_SHIFT | - CPLL_MODE_MASK << CPLL_MODE_SHIFT, + GPLL_MODE_MASK | CPLL_MODE_MASK, GPLL_MODE_NORMAL << GPLL_MODE_SHIFT | CPLL_MODE_NORMAL << CPLL_MODE_SHIFT); } -#endif void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) { /* pll enter slow-mode */ - rk_clrsetreg(&cru->cru_mode_con, - APLL_MODE_MASK << APLL_MODE_SHIFT, + rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, APLL_MODE_SLOW << APLL_MODE_SHIFT); rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); @@ -444,10 +433,8 @@ void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz */ rk_clrsetreg(&cru->cru_clksel_con[0], - CORE_SEL_PLL_MASK << CORE_SEL_PLL_SHIFT | - A17_DIV_MASK << A17_DIV_SHIFT | - MP_DIV_MASK << MP_DIV_SHIFT | - M0_DIV_MASK << M0_DIV_SHIFT, + CORE_SEL_PLL_MASK | A17_DIV_MASK | MP_DIV_MASK | + M0_DIV_MASK, 0 << A17_DIV_SHIFT | 3 << MP_DIV_SHIFT | 1 << M0_DIV_SHIFT); @@ -457,16 +444,14 @@ void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz */ rk_clrsetreg(&cru->cru_clksel_con[37], - CLK_L2RAM_DIV_MASK << CLK_L2RAM_DIV_SHIFT | - ATCLK_CORE_DIV_CON_MASK << ATCLK_CORE_DIV_CON_SHIFT | - PCLK_CORE_DBG_DIV_MASK >> PCLK_CORE_DBG_DIV_SHIFT, + CLK_L2RAM_DIV_MASK | ATCLK_CORE_DIV_CON_MASK | + PCLK_CORE_DBG_DIV_MASK, 1 << CLK_L2RAM_DIV_SHIFT | 3 << ATCLK_CORE_DIV_CON_SHIFT | 3 << PCLK_CORE_DBG_DIV_SHIFT); /* PLL enter normal-mode */ - rk_clrsetreg(&cru->cru_mode_con, - APLL_MODE_MASK << APLL_MODE_SHIFT, + rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, APLL_MODE_NORMAL << APLL_MODE_SHIFT); } @@ -486,16 +471,16 @@ static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru, con = readl(&cru->cru_mode_con); shift = clk_shift[clk_id]; - switch ((con >> shift) & APLL_MODE_MASK) { + switch ((con >> shift) & CRU_MODE_MASK) { case APLL_MODE_SLOW: return OSC_HZ; case APLL_MODE_NORMAL: /* normal mode */ con = readl(&pll->con0); - no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1; - nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1; + no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1; + nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1; con = readl(&pll->con1); - nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1; + nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1; return (24 * nf / (nr * no)) * 1000000; case APLL_MODE_DEEP: @@ -515,20 +500,20 @@ static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate, case HCLK_EMMC: case SCLK_EMMC: con = readl(&cru->cru_clksel_con[12]); - mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK; - div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK; + mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; + div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; break; case HCLK_SDMMC: case SCLK_SDMMC: con = readl(&cru->cru_clksel_con[11]); - mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK; - div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK; + mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; + div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; break; case HCLK_SDIO0: case SCLK_SDIO0: con = readl(&cru->cru_clksel_con[12]); - mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK; - div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK; + mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT; + div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT; break; default: return -EINVAL; @@ -561,24 +546,21 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate, case HCLK_EMMC: case SCLK_EMMC: rk_clrsetreg(&cru->cru_clksel_con[12], - EMMC_PLL_MASK << EMMC_PLL_SHIFT | - EMMC_DIV_MASK << EMMC_DIV_SHIFT, + EMMC_PLL_MASK | EMMC_DIV_MASK, mux << EMMC_PLL_SHIFT | (src_clk_div - 1) << EMMC_DIV_SHIFT); break; case HCLK_SDMMC: case SCLK_SDMMC: rk_clrsetreg(&cru->cru_clksel_con[11], - MMC0_PLL_MASK << MMC0_PLL_SHIFT | - MMC0_DIV_MASK << MMC0_DIV_SHIFT, + MMC0_PLL_MASK | MMC0_DIV_MASK, mux << MMC0_PLL_SHIFT | (src_clk_div - 1) << MMC0_DIV_SHIFT); break; case HCLK_SDIO0: case SCLK_SDIO0: rk_clrsetreg(&cru->cru_clksel_con[12], - SDIO0_PLL_MASK << SDIO0_PLL_SHIFT | - SDIO0_DIV_MASK << SDIO0_DIV_SHIFT, + SDIO0_PLL_MASK | SDIO0_DIV_MASK, mux << SDIO0_PLL_SHIFT | (src_clk_div - 1) << SDIO0_DIV_SHIFT); break; @@ -598,18 +580,18 @@ static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate, switch (periph) { case SCLK_SPI0: con = readl(&cru->cru_clksel_con[25]); - mux = (con >> SPI0_PLL_SHIFT) & SPI0_PLL_MASK; - div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK; + mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT; + div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT; break; case SCLK_SPI1: con = readl(&cru->cru_clksel_con[25]); - mux = (con >> SPI1_PLL_SHIFT) & SPI1_PLL_MASK; - div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK; + mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT; + div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT; break; case SCLK_SPI2: con = readl(&cru->cru_clksel_con[39]); - mux = (con >> SPI2_PLL_SHIFT) & SPI2_PLL_MASK; - div = (con >> SPI2_DIV_SHIFT) & SPI2_DIV_MASK; + mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT; + div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT; break; default: return -EINVAL; @@ -629,22 +611,19 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate, switch (periph) { case SCLK_SPI0: rk_clrsetreg(&cru->cru_clksel_con[25], - SPI0_PLL_MASK << SPI0_PLL_SHIFT | - SPI0_DIV_MASK << SPI0_DIV_SHIFT, + SPI0_PLL_MASK | SPI0_DIV_MASK, SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT | src_clk_div << SPI0_DIV_SHIFT); break; case SCLK_SPI1: rk_clrsetreg(&cru->cru_clksel_con[25], - SPI1_PLL_MASK << SPI1_PLL_SHIFT | - SPI1_DIV_MASK << SPI1_DIV_SHIFT, + SPI1_PLL_MASK | SPI1_DIV_MASK, SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT | src_clk_div << SPI1_DIV_SHIFT); break; case SCLK_SPI2: rk_clrsetreg(&cru->cru_clksel_con[39], - SPI2_PLL_MASK << SPI2_PLL_SHIFT | - SPI2_DIV_MASK << SPI2_DIV_SHIFT, + SPI2_PLL_MASK | SPI2_DIV_MASK, SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT | src_clk_div << SPI2_DIV_SHIFT); break; @@ -794,7 +773,7 @@ static int rk3288_clk_ofdata_to_platdata(struct udevice *dev) #if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3288_clk_priv *priv = dev_get_priv(dev); - priv->cru = (struct rk3288_cru *)dev_get_addr(dev); + priv->cru = (struct rk3288_cru *)devfdt_get_addr(dev); #endif return 0; @@ -803,6 +782,7 @@ static int rk3288_clk_ofdata_to_platdata(struct udevice *dev) static int rk3288_clk_probe(struct udevice *dev) { struct rk3288_clk_priv *priv = dev_get_priv(dev); + bool init_clocks = false; priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); if (IS_ERR(priv->grf)) @@ -813,8 +793,24 @@ static int rk3288_clk_probe(struct udevice *dev) priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); #endif - rkclk_init(priv->cru, priv->grf); + init_clocks = true; #endif + if (!(gd->flags & GD_FLG_RELOC)) { + u32 reg; + + /* + * Init clocks in U-Boot proper if the NPLL is runnning. This + * indicates that a previous boot loader set up the clocks, so + * we need to redo it. U-Boot's SPL does not set this clock. + */ + reg = readl(&priv->cru->cru_mode_con); + if (((reg & NPLL_MODE_MASK) >> NPLL_MODE_SHIFT) == + NPLL_MODE_NORMAL) + init_clocks = true; + } + + if (init_clocks) + rkclk_init(priv->cru, priv->grf); return 0; } diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index 8ec1574..2065a8a 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -555,7 +555,7 @@ static int rk3328_clk_ofdata_to_platdata(struct udevice *dev) { struct rk3328_clk_priv *priv = dev_get_priv(dev); - priv->cru = (struct rk3328_cru *)dev_get_addr(dev); + priv->cru = (struct rk3328_cru *)devfdt_get_addr(dev); return 0; } diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c new file mode 100644 index 0000000..52cad38 --- /dev/null +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -0,0 +1,291 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * Author: Andy Yan <andy.yan@rock-chips.com> + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3368.h> +#include <asm/arch/hardware.h> +#include <asm/io.h> +#include <dm/lists.h> +#include <dt-bindings/clock/rk3368-cru.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct pll_div { + u32 nr; + u32 nf; + u32 no; +}; + +#define OSC_HZ (24 * 1000 * 1000) +#define APLL_L_HZ (800 * 1000 * 1000) +#define APLL_B_HZ (816 * 1000 * 1000) +#define GPLL_HZ (576 * 1000 * 1000) +#define CPLL_HZ (400 * 1000 * 1000) + +#define RATE_TO_DIV(input_rate, output_rate) \ + ((input_rate) / (output_rate) - 1); + +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + +#define PLL_DIVISORS(hz, _nr, _no) { \ + .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \ + _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\ + (_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \ + "divisors on line " __stringify(__LINE__)); + +static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); +static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); +static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6); + +/* Get pll rate by id */ +static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru, + enum rk3368_pll_id pll_id) +{ + uint32_t nr, no, nf; + uint32_t con; + struct rk3368_pll *pll = &cru->pll[pll_id]; + + con = readl(&pll->con3); + + switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) { + case PLL_MODE_SLOW: + return OSC_HZ; + case PLL_MODE_NORMAL: + con = readl(&pll->con0); + no = ((con & PLL_OD_MASK) >> PLL_OD_SHIFT) + 1; + nr = ((con & PLL_NR_MASK) >> PLL_NR_SHIFT) + 1; + con = readl(&pll->con1); + nf = ((con & PLL_NF_MASK) >> PLL_NF_SHIFT) + 1; + + return (24 * nf / (nr * no)) * 1000000; + case PLL_MODE_DEEP_SLOW: + default: + return 32768; + } +} + +static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id, + const struct pll_div *div, bool has_bwadj) +{ + struct rk3368_pll *pll = &cru->pll[pll_id]; + /* All PLLs have same VCO and output frequency range restrictions*/ + uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; + uint output_hz = vco_hz / div->no; + + debug("PLL at %p: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n", + pll, div->nf, div->nr, div->no, vco_hz, output_hz); + + /* enter slow mode and reset pll */ + rk_clrsetreg(&pll->con3, PLL_MODE_MASK | PLL_RESET_MASK, + PLL_RESET << PLL_RESET_SHIFT); + + rk_clrsetreg(&pll->con0, PLL_NR_MASK | PLL_OD_MASK, + ((div->nr - 1) << PLL_NR_SHIFT) | + ((div->no - 1) << PLL_OD_SHIFT)); + writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1); + udelay(10); + + /* return from reset */ + rk_clrreg(&pll->con3, PLL_RESET_MASK); + + /* waiting for pll lock */ + while (!(readl(&pll->con1) & PLL_LOCK_STA)) + udelay(1); + + rk_clrsetreg(&pll->con3, PLL_MODE_MASK, + PLL_MODE_NORMAL << PLL_MODE_SHIFT); + + return 0; +} + +static void rkclk_init(struct rk3368_cru *cru) +{ + u32 apllb, aplll, dpll, cpll, gpll; + + rkclk_set_pll(cru, APLLB, &apll_b_init_cfg, false); + rkclk_set_pll(cru, APLLL, &apll_l_init_cfg, false); + rkclk_set_pll(cru, GPLL, &gpll_init_cfg, false); + rkclk_set_pll(cru, CPLL, &cpll_init_cfg, false); + + apllb = rkclk_pll_get_rate(cru, APLLB); + aplll = rkclk_pll_get_rate(cru, APLLL); + dpll = rkclk_pll_get_rate(cru, DPLL); + cpll = rkclk_pll_get_rate(cru, CPLL); + gpll = rkclk_pll_get_rate(cru, GPLL); + + debug("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n", + __func__, apllb, aplll, dpll, cpll, gpll); +} + +static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id) +{ + u32 div, con, con_id, rate; + u32 pll_rate; + + switch (clk_id) { + case SCLK_SDMMC: + con_id = 50; + break; + case SCLK_EMMC: + con_id = 51; + break; + case SCLK_SDIO0: + con_id = 48; + break; + default: + return -EINVAL; + } + + con = readl(&cru->clksel_con[con_id]); + switch ((con & MMC_PLL_SEL_MASK) >> MMC_PLL_SEL_SHIFT) { + case MMC_PLL_SEL_GPLL: + pll_rate = rkclk_pll_get_rate(cru, GPLL); + break; + case MMC_PLL_SEL_24M: + pll_rate = OSC_HZ; + break; + case MMC_PLL_SEL_CPLL: + case MMC_PLL_SEL_USBPHY_480M: + default: + return -EINVAL; + } + div = (con & MMC_CLK_DIV_MASK) >> MMC_CLK_DIV_SHIFT; + rate = DIV_TO_RATE(pll_rate, div); + + return rate >> 1; +} + +static ulong rk3368_mmc_set_clk(struct rk3368_cru *cru, + ulong clk_id, ulong rate) +{ + u32 div; + u32 con_id; + u32 gpll_rate = rkclk_pll_get_rate(cru, GPLL); + + div = RATE_TO_DIV(gpll_rate, rate << 1); + + switch (clk_id) { + case SCLK_SDMMC: + con_id = 50; + break; + case SCLK_EMMC: + con_id = 51; + break; + case SCLK_SDIO0: + con_id = 48; + break; + default: + return -EINVAL; + } + + if (div > 0x3f) { + div = RATE_TO_DIV(OSC_HZ, rate); + rk_clrsetreg(&cru->clksel_con[con_id], + MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK, + (MMC_PLL_SEL_24M << MMC_PLL_SEL_SHIFT) | + (div << MMC_CLK_DIV_SHIFT)); + } else { + rk_clrsetreg(&cru->clksel_con[con_id], + MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK, + (MMC_PLL_SEL_GPLL << MMC_PLL_SEL_SHIFT) | + div << MMC_CLK_DIV_SHIFT); + } + + return rk3368_mmc_get_clk(cru, clk_id); +} + +static ulong rk3368_clk_get_rate(struct clk *clk) +{ + struct rk3368_clk_priv *priv = dev_get_priv(clk->dev); + ulong rate = 0; + + debug("%s id:%ld\n", __func__, clk->id); + switch (clk->id) { + case HCLK_SDMMC: + case HCLK_EMMC: + rate = rk3368_mmc_get_clk(priv->cru, clk->id); + break; + default: + return -ENOENT; + } + + return rate; +} + +static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate) +{ + struct rk3368_clk_priv *priv = dev_get_priv(clk->dev); + ulong ret = 0; + + debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate); + switch (clk->id) { + case SCLK_SDMMC: + case SCLK_EMMC: + ret = rk3368_mmc_set_clk(priv->cru, clk->id, rate); + break; + default: + return -ENOENT; + } + + return ret; +} + +static struct clk_ops rk3368_clk_ops = { + .get_rate = rk3368_clk_get_rate, + .set_rate = rk3368_clk_set_rate, +}; + +static int rk3368_clk_probe(struct udevice *dev) +{ + struct rk3368_clk_priv *priv = dev_get_priv(dev); + + rkclk_init(priv->cru); + + return 0; +} + +static int rk3368_clk_ofdata_to_platdata(struct udevice *dev) +{ + struct rk3368_clk_priv *priv = dev_get_priv(dev); + + priv->cru = (struct rk3368_cru *)devfdt_get_addr(dev); + + return 0; +} + +static int rk3368_clk_bind(struct udevice *dev) +{ + int ret; + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(gd->dm_root, "rk3368_sysreset", "reset", &dev); + if (ret) + error("bind RK3368 reset driver failed: ret=%d\n", ret); + + return ret; +} + +static const struct udevice_id rk3368_clk_ids[] = { + { .compatible = "rockchip,rk3368-cru" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3368_cru) = { + .name = "rockchip_rk3368_cru", + .id = UCLASS_CLK, + .of_match = rk3368_clk_ids, + .priv_auto_alloc_size = sizeof(struct rk3368_cru), + .ofdata_to_platdata = rk3368_clk_ofdata_to_platdata, + .ops = &rk3368_clk_ops, + .bind = rk3368_clk_bind, + .probe = rk3368_clk_probe, +}; diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 026ed4d..53d2a3f 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -970,7 +970,7 @@ static int rk3399_clk_ofdata_to_platdata(struct udevice *dev) #if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3399_clk_priv *priv = dev_get_priv(dev); - priv->cru = (struct rk3399_cru *)dev_get_addr(dev); + priv->cru = (struct rk3399_cru *)devfdt_get_addr(dev); #endif return 0; } @@ -1154,7 +1154,7 @@ static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev) #if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); - priv->pmucru = (struct rk3399_pmucru *)dev_get_addr(dev); + priv->pmucru = (struct rk3399_pmucru *)devfdt_get_addr(dev); #endif return 0; } diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c new file mode 100644 index 0000000..818293d --- /dev/null +++ b/drivers/clk/rockchip/clk_rv1108.c @@ -0,0 +1,220 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * Author: Andy Yan <andy.yan@rock-chips.com> + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rv1108.h> +#include <asm/arch/hardware.h> +#include <dm/lists.h> +#include <dt-bindings/clock/rv1108-cru.h> + +DECLARE_GLOBAL_DATA_PTR; + +enum { + VCO_MAX_HZ = 2400U * 1000000, + VCO_MIN_HZ = 600 * 1000000, + OUTPUT_MAX_HZ = 2400U * 1000000, + OUTPUT_MIN_HZ = 24 * 1000000, +}; + +#define RATE_TO_DIV(input_rate, output_rate) \ + ((input_rate) / (output_rate) - 1); + +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + +#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ + .refdiv = _refdiv,\ + .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ + .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\ + _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\ + OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\ + #hz "Hz cannot be hit with PLL "\ + "divisors on line " __stringify(__LINE__)); + +/* use interge mode*/ +static inline int rv1108_pll_id(enum rk_clk_id clk_id) +{ + int id = 0; + + switch (clk_id) { + case CLK_ARM: + case CLK_DDR: + id = clk_id - 1; + break; + case CLK_GENERAL: + id = 2; + break; + default: + printf("invalid pll id:%d\n", clk_id); + id = -1; + break; + } + + return id; +} + +static uint32_t rkclk_pll_get_rate(struct rv1108_cru *cru, + enum rk_clk_id clk_id) +{ + uint32_t refdiv, fbdiv, postdiv1, postdiv2; + uint32_t con0, con1, con3; + int pll_id = rv1108_pll_id(clk_id); + struct rv1108_pll *pll = &cru->pll[pll_id]; + uint32_t freq; + + con3 = readl(&pll->con3); + + if (con3 & WORK_MODE_MASK) { + con0 = readl(&pll->con0); + con1 = readl(&pll->con1); + fbdiv = (con0 >> FBDIV_SHIFT) & FBDIV_MASK; + postdiv1 = (con1 & POSTDIV1_MASK) >> POSTDIV1_SHIFT; + postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT; + refdiv = (con1 & REFDIV_MASK) >> REFDIV_SHIFT; + freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; + } else { + freq = OSC_HZ; + } + + return freq; +} + +static int rv1108_mac_set_clk(struct rv1108_cru *cru, ulong rate) +{ + uint32_t con = readl(&cru->clksel_con[24]); + ulong pll_rate; + uint8_t div; + + if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_GPLL) + pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); + else + pll_rate = rkclk_pll_get_rate(cru, CLK_ARM); + + /*default set 50MHZ for gmac*/ + if (!rate) + rate = 50000000; + + div = DIV_ROUND_UP(pll_rate, rate) - 1; + if (div <= 0x1f) + rk_clrsetreg(&cru->clksel_con[24], MAC_CLK_DIV_MASK, + div << MAC_CLK_DIV_SHIFT); + else + debug("Unsupported div for gmac:%d\n", div); + + return DIV_TO_RATE(pll_rate, div); +} + +static int rv1108_sfc_set_clk(struct rv1108_cru *cru, uint rate) +{ + u32 con = readl(&cru->clksel_con[27]); + u32 pll_rate; + u32 div; + + if ((con >> SFC_PLL_SEL_SHIFT) && SFC_PLL_SEL_GPLL) + pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); + else + pll_rate = rkclk_pll_get_rate(cru, CLK_DDR); + + div = DIV_ROUND_UP(pll_rate, rate) - 1; + if (div <= 0x3f) + rk_clrsetreg(&cru->clksel_con[27], SFC_CLK_DIV_MASK, + div << SFC_CLK_DIV_SHIFT); + else + debug("Unsupported sfc clk rate:%d\n", rate); + + return DIV_TO_RATE(pll_rate, div); +} + +static ulong rv1108_clk_get_rate(struct clk *clk) +{ + struct rv1108_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case 0 ... 63: + return rkclk_pll_get_rate(priv->cru, clk->id); + default: + return -ENOENT; + } +} + +static ulong rv1108_clk_set_rate(struct clk *clk, ulong rate) +{ + struct rv1108_clk_priv *priv = dev_get_priv(clk->dev); + ulong new_rate; + + switch (clk->id) { + case SCLK_MAC: + new_rate = rv1108_mac_set_clk(priv->cru, rate); + break; + case SCLK_SFC: + new_rate = rv1108_sfc_set_clk(priv->cru, rate); + break; + default: + return -ENOENT; + } + + return new_rate; +} + +static const struct clk_ops rv1108_clk_ops = { + .get_rate = rv1108_clk_get_rate, + .set_rate = rv1108_clk_set_rate, +}; + +static void rkclk_init(struct rv1108_cru *cru) +{ + unsigned int apll = rkclk_pll_get_rate(cru, CLK_ARM); + unsigned int dpll = rkclk_pll_get_rate(cru, CLK_DDR); + unsigned int gpll = rkclk_pll_get_rate(cru, CLK_GENERAL); + + rk_clrsetreg(&cru->clksel_con[0], CORE_CLK_DIV_MASK, + 0 << MAC_CLK_DIV_SHIFT); + + printf("APLL: %d DPLL:%d GPLL:%d\n", apll, dpll, gpll); +} + +static int rv1108_clk_probe(struct udevice *dev) +{ + struct rv1108_clk_priv *priv = dev_get_priv(dev); + + priv->cru = (struct rv1108_cru *)devfdt_get_addr(dev); + + rkclk_init(priv->cru); + + return 0; +} + +static int rv1108_clk_bind(struct udevice *dev) +{ + int ret; + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(gd->dm_root, "rv1108_sysreset", "reset", &dev); + if (ret) + error("No Rv1108 reset driver: ret=%d\n", ret); + + return 0; +} + +static const struct udevice_id rv1108_clk_ids[] = { + { .compatible = "rockchip,rv1108-cru" }, + { } +}; + +U_BOOT_DRIVER(clk_rv1108) = { + .name = "clk_rv1108", + .id = UCLASS_CLK, + .of_match = rv1108_clk_ids, + .priv_auto_alloc_size = sizeof(struct rv1108_clk_priv), + .ops = &rv1108_clk_ops, + .bind = rv1108_clk_bind, + .probe = rv1108_clk_probe, +}; diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c index bcb2d2e..0fb4854 100644 --- a/drivers/clk/uniphier/clk-uniphier-core.c +++ b/drivers/clk/uniphier/clk-uniphier-core.c @@ -7,7 +7,7 @@ #include <common.h> #include <clk-uclass.h> -#include <dm/device.h> +#include <dm.h> #include <linux/bitops.h> #include <linux/io.h> #include <linux/sizes.h> @@ -121,7 +121,7 @@ static ulong uniphier_clk_set_rate(struct clk *clk, ulong rate) return best_rate; } -const struct clk_ops uniphier_clk_ops = { +static const struct clk_ops uniphier_clk_ops = { .enable = uniphier_clk_enable, .get_rate = uniphier_clk_get_rate, .set_rate = uniphier_clk_set_rate, @@ -132,7 +132,7 @@ static int uniphier_clk_probe(struct udevice *dev) struct uniphier_clk_priv *priv = dev_get_priv(dev); fdt_addr_t addr; - addr = dev_get_addr(dev->parent); + addr = devfdt_get_addr(dev->parent); if (addr == FDT_ADDR_T_NONE) return -EINVAL; |