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-rw-r--r--drivers/i2c/intel_i2c.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/i2c/intel_i2c.c b/drivers/i2c/intel_i2c.c
index 1082d1a..3d777ff 100644
--- a/drivers/i2c/intel_i2c.c
+++ b/drivers/i2c/intel_i2c.c
@@ -9,6 +9,7 @@
#include <dm.h>
#include <i2c.h>
#include <asm/io.h>
+#include <asm/arch/pch.h>
int intel_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
{
@@ -27,6 +28,29 @@ int intel_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
static int intel_i2c_probe(struct udevice *dev)
{
+ /*
+ * So far this is just setup code for ivybridge SMbus. When we have
+ * a full I2C driver this may need to be moved, generalised or made
+ * dependant on a particular compatible string.
+ *
+ * Set SMBus I/O base
+ */
+ dm_pci_write_config32(dev, SMB_BASE,
+ SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
+
+ /* Set SMBus enable. */
+ dm_pci_write_config8(dev, HOSTC, HST_EN);
+
+ /* Set SMBus I/O space enable. */
+ dm_pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
+
+ /* Disable interrupt generation. */
+ outb(0, SMBUS_IO_BASE + SMBHSTCTL);
+
+ /* Clear any lingering errors, so transactions can run. */
+ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+ debug("SMBus controller enabled\n");
+
return 0;
}