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path: root/drivers/mmc/fsl_esdhc.c
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Diffstat (limited to 'drivers/mmc/fsl_esdhc.c')
-rw-r--r--drivers/mmc/fsl_esdhc.c37
1 files changed, 24 insertions, 13 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index e665b5e..0f6f8b1 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2007, Freescale Semiconductor, Inc
+ * Copyright 2007,2010 Freescale Semiconductor, Inc
* Andy Fleming
*
* Based vaguely on the pxa mmc code:
@@ -110,8 +110,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
if (wml_value > 0x10)
wml_value = 0x10;
- wml_value = 0x100000 | wml_value;
-
+ esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
esdhc_write32(&regs->dsaddr, (u32)data->dest);
} else {
if (wml_value > 0x80)
@@ -120,12 +119,12 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
return TIMEOUT;
}
- wml_value = wml_value << 16 | 0x10;
+
+ esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
+ wml_value << 16);
esdhc_write32(&regs->dsaddr, (u32)data->src);
}
- esdhc_write32(&regs->wml, wml_value);
-
esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
/* Calculate the timeout period for data transactions */
@@ -265,18 +264,13 @@ void set_sysctl(struct mmc *mmc, uint clock)
clk = (pre_div << 8) | (div << 4);
- /* On imx the clock must be stopped before changing frequency */
- if (cfg->clk_enable)
- esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
+ esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
udelay(10000);
- clk = SYSCTL_PEREN;
- /* On imx systems the clock must be explicitely enabled */
- if (cfg->clk_enable)
- clk |= SYSCTL_CKEN;
+ clk = SYSCTL_PEREN | SYSCTL_CKEN;
esdhc_setbits32(&regs->sysctl, clk);
}
@@ -349,6 +343,20 @@ static int esdhc_init(struct mmc *mmc)
return ret;
}
+static void esdhc_reset(struct fsl_esdhc *regs)
+{
+ unsigned long timeout = 100; /* wait max 100 ms */
+
+ /* reset the controller */
+ esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
+
+ /* hardware clears the bit when it is done */
+ while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
+ udelay(1000);
+ if (!timeout)
+ printf("MMC/SD: Reset never completed.\n");
+}
+
int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
{
struct fsl_esdhc *regs;
@@ -363,6 +371,9 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
sprintf(mmc->name, "FSL_ESDHC");
regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ /* First reset the eSDHC controller */
+ esdhc_reset(regs);
+
mmc->priv = cfg;
mmc->send_cmd = esdhc_send_cmd;
mmc->set_ios = esdhc_set_ios;