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-rw-r--r--drivers/usb/host/Kconfig9
-rw-r--r--drivers/usb/host/Makefile1
-rw-r--r--drivers/usb/host/ehci-marvell.c59
-rw-r--r--drivers/usb/host/ehci-tegra.c13
-rw-r--r--drivers/usb/host/xhci-mvebu.c97
5 files changed, 170 insertions, 9 deletions
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 61e13d7..b9c5fbe 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -21,6 +21,15 @@ config USB_XHCI_DWC3
Say Y or if your system has a Dual Role SuperSpeed
USB controller based on the DesignWare USB3 IP Core.
+config USB_XHCI_MVEBU
+ bool "MVEBU USB 3.0 support"
+ default y
+ depends on ARCH_MVEBU
+ help
+ Choose this option to add support for USB 3.0 driver on mvebu
+ SoCs, which includes Armada8K, Armada3700 and other Armada
+ family SoCs.
+
config USB_XHCI_ROCKCHIP
bool "Support for Rockchip on-chip xHCI USB controller"
depends on ARCH_ROCKCHIP
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index de25328..58c0cf5 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -61,6 +61,7 @@ obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o
obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
+obj-$(CONFIG_USB_XHCI_MVEBU) += xhci-mvebu.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c
index 253fcb3..4642470 100644
--- a/drivers/usb/host/ehci-marvell.c
+++ b/drivers/usb/host/ehci-marvell.c
@@ -26,6 +26,16 @@ DECLARE_GLOBAL_DATA_PTR;
#define USB_WINDOW_BASE(i) (0x324 + ((i) << 4))
#define USB_TARGET_DRAM 0x0
+#define USB2_SBUSCFG_OFF 0x90
+
+#define USB_SBUSCFG_BAWR_OFF 0x6
+#define USB_SBUSCFG_BARD_OFF 0x3
+#define USB_SBUSCFG_AHBBRST_OFF 0x0
+
+#define USB_SBUSCFG_BAWR_ALIGN_64B 0x4
+#define USB_SBUSCFG_BARD_ALIGN_64B 0x4
+#define USB_SBUSCFG_AHBBRST_INCR16 0x7
+
/*
* USB 2.0 Bridge Address Decoding registers setup
*/
@@ -41,7 +51,7 @@ struct ehci_mvebu_priv {
* to the common mvebu archticture including the mbus setup, this
* will be the only function needed to configure the access windows
*/
-static void usb_brg_adrdec_setup(u32 base)
+static void usb_brg_adrdec_setup(void *base)
{
const struct mbus_dram_target_info *dram;
int i;
@@ -66,6 +76,29 @@ static void usb_brg_adrdec_setup(u32 base)
}
}
+static void marvell_ehci_powerup_fixup(struct ehci_ctrl *ctrl,
+ uint32_t *status_reg, uint32_t *reg)
+{
+ struct ehci_mvebu_priv *priv = ctrl->priv;
+
+ /*
+ * Set default value for reg SBUSCFG, which is Control for the AMBA
+ * system bus interface:
+ * BAWR = BARD = 4 : Align rd/wr bursts packets larger than 64 bytes
+ * AHBBRST = 7 : Align AHB burst for packets larger than 64 bytes
+ */
+ writel((USB_SBUSCFG_BAWR_ALIGN_64B << USB_SBUSCFG_BAWR_OFF) |
+ (USB_SBUSCFG_BARD_ALIGN_64B << USB_SBUSCFG_BARD_OFF) |
+ (USB_SBUSCFG_AHBBRST_INCR16 << USB_SBUSCFG_AHBBRST_OFF),
+ priv->hcd_base + USB2_SBUSCFG_OFF);
+
+ mdelay(50);
+}
+
+static struct ehci_ops marvell_ehci_ops = {
+ .powerup_fixup = NULL,
+};
+
static int ehci_mvebu_probe(struct udevice *dev)
{
struct ehci_mvebu_priv *priv = dev_get_priv(dev);
@@ -81,21 +114,33 @@ static int ehci_mvebu_probe(struct udevice *dev)
return -ENXIO;
}
- usb_brg_adrdec_setup(priv->hcd_base);
+ /*
+ * For SoCs without hlock like Armada3700 we need to program the sbuscfg
+ * reg to guarantee AHB master's burst will not overrun or underrun
+ * the FIFO. Otherwise all USB2 write option will fail.
+ * Also, the address decoder doesn't need to get setup with this
+ * SoC, so don't call usb_brg_adrdec_setup().
+ */
+ if (of_device_is_compatible(dev, "marvell,armada3700-ehci"))
+ marvell_ehci_ops.powerup_fixup = marvell_ehci_powerup_fixup;
+ else
+ usb_brg_adrdec_setup((void *)priv->hcd_base);
hccr = (struct ehci_hccr *)(priv->hcd_base + 0x100);
hcor = (struct ehci_hcor *)
- ((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ ((uintptr_t)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
- debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n",
- (u32)hccr, (u32)hcor,
- (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ debug("ehci-marvell: init hccr %lx and hcor %lx hc_length %ld\n",
+ (uintptr_t)hccr, (uintptr_t)hcor,
+ (uintptr_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
- return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
+ return ehci_register(dev, hccr, hcor, &marvell_ehci_ops, 0,
+ USB_INIT_HOST);
}
static const struct udevice_id ehci_usb_ids[] = {
{ .compatible = "marvell,orion-ehci", },
+ { .compatible = "marvell,armada3700-ehci", },
{ }
};
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index eb54df4..e3620da 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -600,9 +600,18 @@ static int init_ulpi_usb_controller(struct fdt_usb *config,
/* reset ULPI phy */
if (dm_gpio_is_valid(&config->phy_reset_gpio)) {
- dm_gpio_set_value(&config->phy_reset_gpio, 0);
- mdelay(5);
+ /*
+ * This GPIO is typically active-low, and marked as such in
+ * device tree. dm_gpio_set_value() takes this into account
+ * and inverts the value we pass here if required. In other
+ * words, this first call logically asserts the reset signal,
+ * which typically results in driving the physical GPIO low,
+ * and the second call logically de-asserts the reset signal,
+ * which typically results in driver the GPIO high.
+ */
dm_gpio_set_value(&config->phy_reset_gpio, 1);
+ mdelay(5);
+ dm_gpio_set_value(&config->phy_reset_gpio, 0);
}
/* Reset the usb controller */
diff --git a/drivers/usb/host/xhci-mvebu.c b/drivers/usb/host/xhci-mvebu.c
new file mode 100644
index 0000000..23c241a
--- /dev/null
+++ b/drivers/usb/host/xhci-mvebu.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2015 Marvell International Ltd.
+ *
+ * MVEBU USB HOST xHCI Controller
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <usb.h>
+#include <asm/gpio.h>
+
+#include "xhci.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mvebu_xhci_platdata {
+ fdt_addr_t hcd_base;
+};
+
+/**
+ * Contains pointers to register base addresses
+ * for the usb controller.
+ */
+struct mvebu_xhci {
+ struct xhci_ctrl ctrl; /* Needs to come first in this struct! */
+ struct usb_platdata usb_plat;
+ struct xhci_hccr *hcd;
+};
+
+/*
+ * Dummy implementation that can be overwritten by a board
+ * specific function
+ */
+__weak int board_xhci_enable(void)
+{
+ return 0;
+}
+
+static int xhci_usb_probe(struct udevice *dev)
+{
+ struct mvebu_xhci_platdata *plat = dev_get_platdata(dev);
+ struct mvebu_xhci *ctx = dev_get_priv(dev);
+ struct xhci_hcor *hcor;
+ int len;
+
+ ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
+ len = HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase));
+ hcor = (struct xhci_hcor *)((uintptr_t)ctx->hcd + len);
+
+ /* Enable USB xHCI (VBUS, reset etc) in board specific code */
+ board_xhci_enable();
+
+ return xhci_register(dev, ctx->hcd, hcor);
+}
+
+static int xhci_usb_remove(struct udevice *dev)
+{
+ return xhci_deregister(dev);
+}
+
+static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
+{
+ struct mvebu_xhci_platdata *plat = dev_get_platdata(dev);
+
+ /*
+ * Get the base address for XHCI controller from the device node
+ */
+ plat->hcd_base = dev_get_addr(dev);
+ if (plat->hcd_base == FDT_ADDR_T_NONE) {
+ debug("Can't get the XHCI register base address\n");
+ return -ENXIO;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id xhci_usb_ids[] = {
+ { .compatible = "marvell,armada3700-xhci" },
+ { .compatible = "marvell,armada-8k-xhci" },
+ { }
+};
+
+U_BOOT_DRIVER(usb_xhci) = {
+ .name = "xhci_mvebu",
+ .id = UCLASS_USB,
+ .of_match = xhci_usb_ids,
+ .ofdata_to_platdata = xhci_usb_ofdata_to_platdata,
+ .probe = xhci_usb_probe,
+ .remove = xhci_usb_remove,
+ .ops = &xhci_usb_ops,
+ .platdata_auto_alloc_size = sizeof(struct mvebu_xhci_platdata),
+ .priv_auto_alloc_size = sizeof(struct mvebu_xhci),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};