diff options
Diffstat (limited to 'drivers')
46 files changed, 1521 insertions, 313 deletions
diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index b8870ec..d73d510 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -16,9 +16,20 @@ #include <linux/list.h> #include <linux/compiler.h> +static bool dfu_reset_request; static LIST_HEAD(dfu_list); static int dfu_alt_num; +bool dfu_reset(void) +{ + return dfu_reset_request; +} + +void dfu_trigger_reset() +{ + dfu_reset_request = true; +} + static int dfu_find_alt_num(const char *s) { int i = 0; diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c index 96d4c9b..22defcd 100644 --- a/drivers/dma/apbh_dma.c +++ b/drivers/dma/apbh_dma.c @@ -545,6 +545,28 @@ int mxs_dma_go(int chan) } /* + * Execute a continuously running circular DMA descriptor. + * NOTE: This is not intended for general use, but rather + * for the LCD driver in Smart-LCD mode. It allows + * continuous triggering of the RUN bit there. + */ +void mxs_dma_circ_start(int chan, struct mxs_dma_desc *pdesc) +{ + struct mxs_apbh_regs *apbh_regs = + (struct mxs_apbh_regs *)MXS_APBH_BASE; + + mxs_dma_flush_desc(pdesc); + + mxs_dma_enable_irq(chan, 1); + + writel(mxs_dma_cmd_address(pdesc), + &apbh_regs->ch[chan].hw_apbh_ch_nxtcmdar); + writel(1, &apbh_regs->ch[chan].hw_apbh_ch_sema); + writel(1 << (chan + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET), + &apbh_regs->hw_apbh_ctrl0_clr); +} + +/* * Initialize the DMA hardware */ void mxs_dma_init(void) diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 8cc16fd..14363c9 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -23,6 +23,7 @@ #define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000 #define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 #define DEVCFG_STATUS_PCFG_INIT 0x00000010 +#define DEVCFG_MCTRL_PCAP_LPBK 0x00000010 #define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002 #define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001 @@ -31,7 +32,7 @@ #endif #ifndef CONFIG_SYS_FPGA_PROG_TIME -#define CONFIG_SYS_FPGA_PROG_TIME CONFIG_SYS_HZ /* 1 s */ +#define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */ #endif int zynq_info(Xilinx_desc *desc) @@ -200,6 +201,9 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) swap = SWAP_DONE; } + /* Clear loopback bit */ + clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK); + if (!partialbit) { zynq_slcr_devcfg_disable(); diff --git a/drivers/gpio/adi_gpio2.c b/drivers/gpio/adi_gpio2.c index 7a034eb..051073c 100644 --- a/drivers/gpio/adi_gpio2.c +++ b/drivers/gpio/adi_gpio2.c @@ -352,8 +352,8 @@ void special_gpio_free(unsigned gpio) return; } - reserve(special_gpio, gpio); - reserve(peri, gpio); + unreserve(special_gpio, gpio); + unreserve(peri, gpio); set_label(gpio, "free"); } #endif diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c index be13745..7371cd4 100644 --- a/drivers/gpio/pca953x.c +++ b/drivers/gpio/pca953x.c @@ -47,9 +47,6 @@ struct pca953x_chip_ngpio { static struct pca953x_chip_ngpio pca953x_chip_ngpios[] = CONFIG_SYS_I2C_PCA953X_WIDTH; -#define NUM_CHIP_GPIOS (sizeof(pca953x_chip_ngpios) / \ - sizeof(struct pca953x_chip_ngpio)) - /* * Determine the number of GPIO pins supported. If we don't know we assume * 8 pins. @@ -58,7 +55,7 @@ static int pca953x_ngpio(uint8_t chip) { int i; - for (i = 0; i < NUM_CHIP_GPIOS; i++) + for (i = 0; i < ARRAY_SIZE(pca953x_chip_ngpios); i++) if (pca953x_chip_ngpios[i].chip == chip) return pca953x_chip_ngpios[i].ngpio; diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index a2baec0..396fea8 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -105,11 +105,11 @@ DECLARE_GLOBAL_DATA_PTR; # endif #endif -#if !defined(CONFIG_SYS_SOFT_I2C_SPEED) -#define CONFIG_SYS_SOFT_I2C_SPEED CONFIG_SYS_I2C_SPEED +#if !defined(CONFIG_SYS_I2C_SOFT_SPEED) +#define CONFIG_SYS_I2C_SOFT_SPEED CONFIG_SYS_I2C_SPEED #endif -#if !defined(CONFIG_SYS_SOFT_I2C_SLAVE) -#define CONFIG_SYS_SOFT_I2C_SLAVE CONFIG_SYS_I2C_SLAVE +#if !defined(CONFIG_SYS_I2C_SOFT_SLAVE) +#define CONFIG_SYS_I2C_SOFT_SLAVE CONFIG_SYS_I2C_SLAVE #endif /*----------------------------------------------------------------------- diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c index 9ac3969..9847cf1 100644 --- a/drivers/i2c/tegra_i2c.c +++ b/drivers/i2c/tegra_i2c.c @@ -453,6 +453,10 @@ void i2c_init_board(void) static void tegra_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) { + /* No i2c support prior to relocation */ + if (!(gd->flags & GD_FLG_RELOC)) + return; + /* This will override the speed selected in the fdt for that port */ debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr); i2c_set_bus_speed(speed); diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index a37663e..a389cd1 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -1803,7 +1803,7 @@ static int flash_detect_legacy(phys_addr_t base, int banknum) break; else unmap_physmem((void *)info->start[0], - MAP_NOCACHE); + info->portwidth); } } diff --git a/drivers/mtd/spi/atmel.c b/drivers/mtd/spi/atmel.c index 6a92c4b..f34df43 100644 --- a/drivers/mtd/spi/atmel.c +++ b/drivers/mtd/spi/atmel.c @@ -252,7 +252,7 @@ static int dataflash_write_p2(struct spi_flash *flash, } debug("SF: AT45: Successfully programmed %zu bytes @ 0x%x\n", - len, offset); + len, offset); ret = 0; out: @@ -325,7 +325,7 @@ static int dataflash_write_at45(struct spi_flash *flash, } debug("SF: AT45: Successfully programmed %zu bytes @ 0x%x\n", - len, offset); + len, offset); ret = 0; out: @@ -387,7 +387,7 @@ static int dataflash_erase_p2(struct spi_flash *flash, u32 offset, size_t len) } debug("SF: AT45: Successfully erased %zu bytes @ 0x%x\n", - len, offset); + len, offset); ret = 0; out: @@ -450,7 +450,7 @@ static int dataflash_erase_at45(struct spi_flash *flash, u32 offset, size_t len) } debug("SF: AT45: Successfully erased %zu bytes @ 0x%x\n", - len, offset); + len, offset); ret = 0; out: @@ -476,7 +476,7 @@ struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode) if (i == ARRAY_SIZE(atmel_spi_flash_table)) { debug("SF: Unsupported DataFlash ID %02x\n", - idcode[1]); + idcode[1]); return NULL; } diff --git a/drivers/mtd/spi/eon.c b/drivers/mtd/spi/eon.c index b16e7ab..25cfc12 100644 --- a/drivers/mtd/spi/eon.c +++ b/drivers/mtd/spi/eon.c @@ -54,8 +54,7 @@ struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode) flash->page_size = 256; flash->sector_size = 256 * 16 * 16; - flash->size = 256 * 16 - * params->nr_sectors; + flash->size = 256 * 16 * params->nr_sectors; return flash; } diff --git a/drivers/mtd/spi/gigadevice.c b/drivers/mtd/spi/gigadevice.c index 950c777..b42581a 100644 --- a/drivers/mtd/spi/gigadevice.c +++ b/drivers/mtd/spi/gigadevice.c @@ -45,7 +45,7 @@ struct spi_flash *spi_flash_probe_gigadevice(struct spi_slave *spi, u8 *idcode) if (i == ARRAY_SIZE(gigadevice_spi_flash_table)) { debug("SF: Unsupported Gigadevice ID %02x%02x\n", - idcode[1], idcode[2]); + idcode[1], idcode[2]); return NULL; } diff --git a/drivers/mtd/spi/ramtron.c b/drivers/mtd/spi/ramtron.c index f67ddd6..38f9d69 100644 --- a/drivers/mtd/spi/ramtron.c +++ b/drivers/mtd/spi/ramtron.c @@ -230,7 +230,8 @@ struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode) /* JEDEC conformant RAMTRON id */ for (i = 0; i < ARRAY_SIZE(ramtron_spi_fram_table); i++) { params = &ramtron_spi_fram_table[i]; - if (idcode[1] == params->id1 && idcode[2] == params->id2) + if (idcode[1] == params->id1 && + idcode[2] == params->id2) goto found; } break; @@ -251,7 +252,8 @@ struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode) /* now find the device */ for (i = 0; i < ARRAY_SIZE(ramtron_spi_fram_table); i++) { params = &ramtron_spi_fram_table[i]; - if (!strcmp(params->name, CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC)) + if (!strcmp(params->name, + CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC)) goto found; } debug("SF: Unsupported non-JEDEC RAMTRON device " @@ -264,7 +266,7 @@ struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode) /* arriving here means no method has found a device we can handle */ debug("SF/ramtron: unsupported device id0=%02x id1=%02x id2=%02x\n", - idcode[0], idcode[1], idcode[2]); + idcode[0], idcode[1], idcode[2]); return NULL; found: diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c index 47a4897..fa7ac8c 100644 --- a/drivers/mtd/spi/spansion.c +++ b/drivers/mtd/spi/spansion.c @@ -6,7 +6,7 @@ * TsiChung Liew (Tsi-Chung.Liew@freescale.com), * and Jason McMullan (mcmullan@netapp.com) * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> @@ -122,7 +122,8 @@ struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode) } if (i == ARRAY_SIZE(spansion_spi_flash_table)) { - debug("SF: Unsupported SPANSION ID %04x %04x\n", jedec, ext_jedec); + debug("SF: Unsupported SPANSION ID %04x %04x\n", + jedec, ext_jedec); return NULL; } diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 6a6fe37..9814395 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -40,12 +40,13 @@ static int spi_flash_read_write(struct spi_slave *spi, ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags); if (ret) { debug("SF: Failed to send command (%zu bytes): %d\n", - cmd_len, ret); + cmd_len, ret); } else if (data_len != 0) { - ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END); + ret = spi_xfer(spi, data_len * 8, data_out, data_in, + SPI_XFER_END); if (ret) debug("SF: Failed to transfer %zu bytes of data: %d\n", - data_len, ret); + data_len, ret); } return ret; @@ -86,7 +87,7 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN); if (ret) { debug("SF: fail to read %s status register\n", - cmd == CMD_READ_STATUS ? "read" : "flag"); + cmd == CMD_READ_STATUS ? "read" : "flag"); return ret; } @@ -144,7 +145,7 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, ret = spi_flash_cmd_wait_ready(flash, timeout); if (ret < 0) { debug("SF: write %s timed out\n", - timeout == SPI_FLASH_PROG_TIMEOUT ? + timeout == SPI_FLASH_PROG_TIMEOUT ? "program" : "page erase"); return ret; } diff --git a/drivers/mtd/spi/spi_spl_load.c b/drivers/mtd/spi/spi_spl_load.c index 7c799ca..2935530 100644 --- a/drivers/mtd/spi/spi_spl_load.c +++ b/drivers/mtd/spi/spi_spl_load.c @@ -39,7 +39,7 @@ void spl_spi_load_image(void) /* Load u-boot, mkimage header is 64 bytes. */ spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40, - (void *) header); + (void *)header); spl_parse_image_header(header); spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS, spl_image.size, (void *)spl_image.load_addr); diff --git a/drivers/mtd/spi/sst.c b/drivers/mtd/spi/sst.c index 95f5490..256867c 100644 --- a/drivers/mtd/spi/sst.c +++ b/drivers/mtd/spi/sst.c @@ -19,7 +19,7 @@ #include "spi_flash_internal.h" #define CMD_SST_BP 0x02 /* Byte Program */ -#define CMD_SST_AAI_WP 0xAD /* Auto Address Increment Word Program */ +#define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */ #define SST_SR_WIP (1 << 0) /* Write-in-Progress */ #define SST_SR_WEL (1 << 1) /* Write enable */ @@ -50,47 +50,61 @@ static const struct sst_spi_flash_params sst_spi_flash_table[] = { .flags = SST_FEAT_WP, .nr_sectors = 128, .name = "SST25VF040B", - },{ + }, + { .idcode1 = 0x8e, .flags = SST_FEAT_WP, .nr_sectors = 256, .name = "SST25VF080B", - },{ + }, + { .idcode1 = 0x41, .flags = SST_FEAT_WP, .nr_sectors = 512, .name = "SST25VF016B", - },{ + }, + { .idcode1 = 0x4a, .flags = SST_FEAT_WP, .nr_sectors = 1024, .name = "SST25VF032B", - },{ + }, + { .idcode1 = 0x4b, .flags = SST_FEAT_MBP, .nr_sectors = 2048, .name = "SST25VF064C", - },{ + }, + { .idcode1 = 0x01, .flags = SST_FEAT_WP, .nr_sectors = 16, .name = "SST25WF512", - },{ + }, + { .idcode1 = 0x02, .flags = SST_FEAT_WP, .nr_sectors = 32, .name = "SST25WF010", - },{ + }, + { .idcode1 = 0x03, .flags = SST_FEAT_WP, .nr_sectors = 64, .name = "SST25WF020", - },{ + }, + { .idcode1 = 0x04, .flags = SST_FEAT_WP, .nr_sectors = 128, .name = "SST25WF040", }, + { + .idcode1 = 0x05, + .flags = SST_FEAT_WP, + .nr_sectors = 256, + .name = "SST25WF080", + }, }; static int @@ -105,7 +119,7 @@ sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) }; debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", - spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset); + spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset); ret = spi_flash_cmd_write_enable(flash); if (ret) @@ -152,11 +166,11 @@ sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, const void *buf) for (; actual < len - 1; actual += 2) { debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", - spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual, cmd[0], - offset); + spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual, + cmd[0], offset); ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, - buf + actual, 2); + buf + actual, 2); if (ret) { debug("SF: sst word program failed\n"); break; diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c index 0ca00f1..c5fa64e 100644 --- a/drivers/mtd/spi/stmicro.c +++ b/drivers/mtd/spi/stmicro.c @@ -8,7 +8,7 @@ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> @@ -18,7 +18,7 @@ #include "spi_flash_internal.h" /* M25Pxx-specific commands */ -#define CMD_M25PXX_RES 0xab /* Release from DP, and Read Signature */ +#define CMD_M25PXX_RES 0xab /* Release from DP, and Read Signature */ struct stmicro_spi_flash_params { u16 id; @@ -150,7 +150,7 @@ static const struct stmicro_spi_flash_params stmicro_spi_flash_table[] = { }, }; -struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode) +struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode) { const struct stmicro_spi_flash_params *params; struct spi_flash *flash; @@ -166,17 +166,17 @@ struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode) idcode[0] = 0x20; idcode[1] = 0x20; idcode[2] = idcode[3] + 1; - } else + } else { return NULL; + } } id = ((idcode[1] << 8) | idcode[2]); for (i = 0; i < ARRAY_SIZE(stmicro_spi_flash_table); i++) { params = &stmicro_spi_flash_table[i]; - if (params->id == id) { + if (params->id == id) break; - } } if (i == ARRAY_SIZE(stmicro_spi_flash_table)) { diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c index c399bf1..b31911a 100644 --- a/drivers/mtd/spi/winbond.c +++ b/drivers/mtd/spi/winbond.c @@ -123,7 +123,7 @@ struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode) if (i == ARRAY_SIZE(winbond_spi_flash_table)) { debug("SF: Unsupported Winbond ID %02x%02x\n", - idcode[1], idcode[2]); + idcode[1], idcode[2]); return NULL; } diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index 4bc8f35..bca20b3 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -396,6 +396,8 @@ int fm_init_common(int index, struct ccsr_fman *reg) } #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE) void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR; +#else + void *addr = NULL; #endif /* Upload the Fman microcode if it's present */ diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 17ca961..d55db1a 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -28,12 +28,6 @@ DECLARE_GLOBAL_DATA_PTR; #include <asm/io.h> #include <asm/fsl_pci.h> -/* Freescale-specific PCI config registers */ -#define FSL_PCI_PBFR 0x44 -#define FSL_PCIE_CAP_ID 0x4c -#define FSL_PCIE_CFG_RDY 0x4b0 -#define FSL_PROG_IF_AGENT 0x1 - #ifndef CONFIG_SYS_PCI_MEMORY_BUS #define CONFIG_SYS_PCI_MEMORY_BUS 0 #endif @@ -424,6 +418,15 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) udelay(1); #endif if (pcie_cap == PCI_CAP_ID_EXP) { + if (block_rev >= PEX_IP_BLK_REV_3_0) { +#define PEX_CSR0_LTSSM_MASK 0xFC +#define PEX_CSR0_LTSSM_SHIFT 2 + ltssm = (in_be32(&pci->pex_csr0) + & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT; + enabled = (ltssm == 0x11) ? 1 : 0; + } else { + /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); */ + /* enabled = ltssm >= PCI_LTSSM_L0; */ pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); enabled = ltssm >= PCI_LTSSM_L0; @@ -456,6 +459,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) PCI_BASE_ADDRESS_0, pcicsrbar); } #endif + } #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003 if (enabled == 0) { @@ -564,6 +568,10 @@ int fsl_is_pci_agent(struct pci_controller *hose) u8 prog_if; pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if); + /* Programming Interface (PCI_CLASS_PROG) + * 0 == pci host or pcie root-complex, + * 1 == pci agent or pcie end-point + */ return (prog_if == FSL_PROG_IF_AGENT); } } diff --git a/drivers/serial/arm_dcc.c b/drivers/serial/arm_dcc.c index c217c88..29d9295 100644 --- a/drivers/serial/arm_dcc.c +++ b/drivers/serial/arm_dcc.c @@ -27,7 +27,7 @@ */ #include <common.h> -#include <stdio_dev.h> +#include <serial.h> #if defined(CONFIG_CPU_V6) /* @@ -89,12 +89,12 @@ #define TIMEOUT_COUNT 0x4000000 -int arm_dcc_init(void) +static int arm_dcc_init(void) { return 0; } -int arm_dcc_getc(void) +static int arm_dcc_getc(void) { int ch; register unsigned int reg; @@ -107,7 +107,7 @@ int arm_dcc_getc(void) return ch; } -void arm_dcc_putc(char ch) +static void arm_dcc_putc(char ch) { register unsigned int reg; unsigned int timeout_count = TIMEOUT_COUNT; @@ -123,13 +123,13 @@ void arm_dcc_putc(char ch) write_dcc(ch); } -void arm_dcc_puts(const char *s) +static void arm_dcc_puts(const char *s) { while (*s) arm_dcc_putc(*s++); } -int arm_dcc_tstc(void) +static int arm_dcc_tstc(void) { register unsigned int reg; @@ -138,22 +138,27 @@ int arm_dcc_tstc(void) return reg; } -static struct stdio_dev arm_dcc_dev; +static void arm_dcc_setbrg(void) +{ +} -int drv_arm_dcc_init(void) +static struct serial_device arm_dcc_drv = { + .name = "arm_dcc", + .start = arm_dcc_init, + .stop = NULL, + .setbrg = arm_dcc_setbrg, + .putc = arm_dcc_putc, + .puts = arm_dcc_puts, + .getc = arm_dcc_getc, + .tstc = arm_dcc_tstc, +}; + +void arm_dcc_initialize(void) { - strcpy(arm_dcc_dev.name, "dcc"); - arm_dcc_dev.ext = 0; /* No extensions */ - arm_dcc_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_OUTPUT; - arm_dcc_dev.tstc = arm_dcc_tstc; /* 'tstc' function */ - arm_dcc_dev.getc = arm_dcc_getc; /* 'getc' function */ - arm_dcc_dev.putc = arm_dcc_putc; /* 'putc' function */ - arm_dcc_dev.puts = arm_dcc_puts; /* 'puts' function */ - - return stdio_register(&arm_dcc_dev); + serial_register(&arm_dcc_drv); } __weak struct serial_device *default_serial_console(void) { - return NULL; + return &arm_dcc_drv; } diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 6730135..118fbc3 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -159,6 +159,7 @@ serial_initfunc(pl01x_serial_initialize); serial_initfunc(s3c44b0_serial_initialize); serial_initfunc(sa1100_serial_initialize); serial_initfunc(sh_serial_initialize); +serial_initfunc(arm_dcc_initialize); /** * serial_register() - Register serial driver with serial driver core @@ -251,6 +252,7 @@ void serial_initialize(void) s3c44b0_serial_initialize(); sa1100_serial_initialize(); sh_serial_initialize(); + arm_dcc_initialize(); serial_assign(default_serial_console()->name); } diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h index bbabb32..e243a8e 100644 --- a/drivers/serial/usbtty.h +++ b/drivers/serial/usbtty.h @@ -22,6 +22,8 @@ #include <usb/pxa27x_udc.h> #elif defined(CONFIG_DW_UDC) #include <usb/designware_udc.h> +#elif defined(CONFIG_MV_UDC) +#include <usb/mv_udc.h> #endif #include <version.h> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 019132e..91d24ce 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -39,6 +39,7 @@ COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o +COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/spi/bfin_spi.c b/drivers/spi/bfin_spi.c index a9a4d92..f7192c2 100644 --- a/drivers/spi/bfin_spi.c +++ b/drivers/spi/bfin_spi.c @@ -144,10 +144,8 @@ void spi_set_speed(struct spi_slave *slave, uint hz) u32 baud; sclk = get_sclk(); - baud = sclk / (2 * hz); /* baud should be rounded up */ - if (sclk % (2 * hz)) - baud += 1; + baud = DIV_ROUND_UP(sclk, 2 * hz); if (baud < 2) baud = 2; else if (baud > (u16)-1) diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index fc0a58b..c883d3c 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -221,15 +221,13 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, slave->bus, slave->cs, *(uint *) dout, dout, *(uint *) din, din, len); - num_chunks = data_len / max_tran_len + - (data_len % max_tran_len ? 1 : 0); + num_chunks = DIV_ROUND_UP(data_len, max_tran_len); while (num_chunks--) { if (data_in) din = buffer + rx_offset; dout = buffer; tran_len = min(data_len , max_tran_len); - num_blks = (tran_len + cmd_len) / 4 + - ((tran_len + cmd_len) % 4 ? 1 : 0); + num_blks = DIV_ROUND_UP(tran_len + cmd_len, 4); num_bytes = (tran_len + cmd_len) % 4; fsl->data_len = tran_len + cmd_len; spi_cs_activate(slave); diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c index bbfc259..348361a 100644 --- a/drivers/spi/mpc8xxx_spi.c +++ b/drivers/spi/mpc8xxx_spi.c @@ -77,7 +77,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, { volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi; unsigned int tmpdout, tmpdin, event; - int numBlks = bitlen / 32 + (bitlen % 32 ? 1 : 0); + int numBlks = DIV_ROUND_UP(bitlen, 32); int tm, isRead = 0; unsigned char charSize = 32; diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c new file mode 100644 index 0000000..5da8759 --- /dev/null +++ b/drivers/spi/zynq_spi.c @@ -0,0 +1,280 @@ +/* + * (C) Copyright 2013 Inc. + * + * Xilinx Zynq PS SPI controller driver (master mode only) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <malloc.h> +#include <spi.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> + +/* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */ +#define ZYNQ_SPI_CR_MSA_MASK (1 << 15) /* Manual start enb */ +#define ZYNQ_SPI_CR_MCS_MASK (1 << 14) /* Manual chip select */ +#define ZYNQ_SPI_CR_CS_MASK (0xF << 10) /* Chip select */ +#define ZYNQ_SPI_CR_BRD_MASK (0x7 << 3) /* Baud rate div */ +#define ZYNQ_SPI_CR_CPHA_MASK (1 << 2) /* Clock phase */ +#define ZYNQ_SPI_CR_CPOL_MASK (1 << 1) /* Clock polarity */ +#define ZYNQ_SPI_CR_MSTREN_MASK (1 << 0) /* Mode select */ +#define ZYNQ_SPI_IXR_RXNEMPTY_MASK (1 << 4) /* RX_FIFO_not_empty */ +#define ZYNQ_SPI_IXR_TXOW_MASK (1 << 2) /* TX_FIFO_not_full */ +#define ZYNQ_SPI_IXR_ALL_MASK 0x7F /* All IXR bits */ +#define ZYNQ_SPI_ENR_SPI_EN_MASK (1 << 0) /* SPI Enable */ + +#define ZYNQ_SPI_FIFO_DEPTH 128 +#ifndef CONFIG_SYS_ZYNQ_SPI_WAIT +#define CONFIG_SYS_ZYNQ_SPI_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */ +#endif + +/* zynq spi register set */ +struct zynq_spi_regs { + u32 cr; /* 0x00 */ + u32 isr; /* 0x04 */ + u32 ier; /* 0x08 */ + u32 idr; /* 0x0C */ + u32 imr; /* 0x10 */ + u32 enr; /* 0x14 */ + u32 dr; /* 0x18 */ + u32 txdr; /* 0x1C */ + u32 rxdr; /* 0x20 */ +}; + +/* zynq spi slave */ +struct zynq_spi_slave { + struct spi_slave slave; + struct zynq_spi_regs *base; + u8 mode; + u8 fifo_depth; + u32 speed_hz; + u32 input_hz; + u32 req_hz; +}; + +static inline struct zynq_spi_slave *to_zynq_spi_slave(struct spi_slave *slave) +{ + return container_of(slave, struct zynq_spi_slave, slave); +} + +static inline struct zynq_spi_regs *get_zynq_spi_base(int dev) +{ + if (dev) + return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR1; + else + return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR0; +} + +static void zynq_spi_init_hw(struct zynq_spi_slave *zslave) +{ + u32 confr; + + /* Disable SPI */ + writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr); + + /* Disable Interrupts */ + writel(ZYNQ_SPI_IXR_ALL_MASK, &zslave->base->idr); + + /* Clear RX FIFO */ + while (readl(&zslave->base->isr) & + ZYNQ_SPI_IXR_RXNEMPTY_MASK) + readl(&zslave->base->rxdr); + + /* Clear Interrupts */ + writel(ZYNQ_SPI_IXR_ALL_MASK, &zslave->base->isr); + + /* Manual slave select and Auto start */ + confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK | + ZYNQ_SPI_CR_MSTREN_MASK; + confr &= ~ZYNQ_SPI_CR_MSA_MASK; + writel(confr, &zslave->base->cr); + + /* Enable SPI */ + writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr); +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + /* 2 bus with 3 chipselect */ + return bus < 2 && cs < 3; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave); + u32 cr; + + debug("spi_cs_activate: 0x%08x\n", (u32)slave); + + clrbits_le32(&zslave->base->cr, ZYNQ_SPI_CR_CS_MASK); + cr = readl(&zslave->base->cr); + /* + * CS cal logic: CS[13:10] + * xxx0 - cs0 + * xx01 - cs1 + * x011 - cs2 + */ + cr |= (~(0x1 << slave->cs) << 10) & ZYNQ_SPI_CR_CS_MASK; + writel(cr, &zslave->base->cr); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave); + + debug("spi_cs_deactivate: 0x%08x\n", (u32)slave); + + setbits_le32(&zslave->base->cr, ZYNQ_SPI_CR_CS_MASK); +} + +void spi_init() +{ + /* nothing to do */ +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct zynq_spi_slave *zslave; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + zslave = spi_alloc_slave(struct zynq_spi_slave, bus, cs); + if (!zslave) { + printf("SPI_error: Fail to allocate zynq_spi_slave\n"); + return NULL; + } + + zslave->base = get_zynq_spi_base(bus); + zslave->mode = mode; + zslave->fifo_depth = ZYNQ_SPI_FIFO_DEPTH; + zslave->input_hz = 166666700; + zslave->speed_hz = zslave->input_hz / 2; + zslave->req_hz = max_hz; + + /* init the zynq spi hw */ + zynq_spi_init_hw(zslave); + + return &zslave->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave); + + debug("spi_free_slave: 0x%08x\n", (u32)slave); + free(zslave); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave); + u32 confr = 0; + u8 baud_rate_val = 0; + + writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr); + + /* Set the SPI Clock phase and polarities */ + confr = readl(&zslave->base->cr); + confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK); + if (zslave->mode & SPI_CPHA) + confr |= ZYNQ_SPI_CR_CPHA_MASK; + if (zslave->mode & SPI_CPOL) + confr |= ZYNQ_SPI_CR_CPOL_MASK; + + /* Set the clock frequency */ + if (zslave->req_hz == 0) { + /* Set baudrate x8, if the req_hz is 0 */ + baud_rate_val = 0x2; + } else if (zslave->speed_hz != zslave->req_hz) { + while ((baud_rate_val < 8) && + ((zslave->input_hz / + (2 << baud_rate_val)) > zslave->req_hz)) + baud_rate_val++; + zslave->speed_hz = zslave->req_hz / (2 << baud_rate_val); + } + confr &= ~ZYNQ_SPI_CR_BRD_MASK; + confr |= (baud_rate_val << 3); + writel(confr, &zslave->base->cr); + + writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave); + + debug("spi_release_bus: 0x%08x\n", (u32)slave); + writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave); + u32 len = bitlen / 8; + u32 tx_len = len, rx_len = len, tx_tvl; + const u8 *tx_buf = dout; + u8 *rx_buf = din, buf; + u32 ts, status; + + debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n", + slave->bus, slave->cs, bitlen, len, flags); + + if (bitlen == 0) + return -1; + + if (bitlen % 8) { + debug("spi_xfer: Non byte aligned SPI transfer\n"); + return -1; + } + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + while (rx_len > 0) { + /* Write the data into TX FIFO - tx threshold is fifo_depth */ + tx_tvl = 0; + while ((tx_tvl < zslave->fifo_depth) && tx_len) { + if (tx_buf) + buf = *tx_buf++; + else + buf = 0; + writel(buf, &zslave->base->txdr); + tx_len--; + tx_tvl++; + } + + /* Check TX FIFO completion */ + ts = get_timer(0); + status = readl(&zslave->base->isr); + while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) { + if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) { + printf("spi_xfer: Timeout! TX FIFO not full\n"); + return -1; + } + status = readl(&zslave->base->isr); + } + + /* Read the data from RX FIFO */ + status = readl(&zslave->base->isr); + while (status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) { + buf = readl(&zslave->base->rxdr); + if (rx_buf) + *rx_buf++ = buf; + status = readl(&zslave->base->isr); + rx_len--; + } + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return 0; +} diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c index 5321a68..37d04a1 100644 --- a/drivers/usb/gadget/f_dfu.c +++ b/drivers/usb/gadget/f_dfu.c @@ -312,6 +312,8 @@ static int state_dfu_idle(struct f_dfu *f_dfu, DFU_STATE_dfuMANIFEST_WAIT_RST; to_runtime_mode(f_dfu); f_dfu->dfu_state = DFU_STATE_appIDLE; + + dfu_trigger_reset(); break; default: f_dfu->dfu_state = DFU_STATE_dfuERROR; diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index f038747..aa54b85 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -144,7 +144,7 @@ #define gadget_is_m66592(g) 0 #endif -#ifdef CONFIG_USB_GADGET_MV +#ifdef CONFIG_MV_UDC #define gadget_is_mv(g) (!strcmp("mv_udc", (g)->name)) #else #define gadget_is_mv(g) 0 diff --git a/drivers/usb/gadget/mv_udc.c b/drivers/usb/gadget/mv_udc.c index 7fa5288..7574e31 100644 --- a/drivers/usb/gadget/mv_udc.c +++ b/drivers/usb/gadget/mv_udc.c @@ -17,6 +17,20 @@ #include <linux/types.h> #include <usb/mv_udc.h> +#if CONFIG_USB_MAX_CONTROLLER_COUNT > 1 +#error This driver only supports one single controller. +#endif + +/* + * Check if the system has too long cachelines. If the cachelines are + * longer then 128b, the driver will not be able flush/invalidate data + * cache over separate QH entries. We use 128b because one QH entry is + * 64b long and there are always two QH list entries for each endpoint. + */ +#if ARCH_DMA_MINALIGN > 128 +#error This driver can not work on systems with caches longer than 128b +#endif + #ifndef DEBUG #define DBG(x...) do {} while (0) #else @@ -39,8 +53,6 @@ static const char *reqname(unsigned r) } #endif -#define PAGE_SIZE 4096 -#define QH_MAXNUM 32 static struct usb_endpoint_descriptor ep0_out_desc = { .bLength = sizeof(struct usb_endpoint_descriptor), .bDescriptorType = USB_DT_ENDPOINT, @@ -55,8 +67,6 @@ static struct usb_endpoint_descriptor ep0_in_desc = { .bmAttributes = USB_ENDPOINT_XFER_CONTROL, }; -struct ept_queue_head *epts; -struct ept_queue_item *items[2 * NUM_ENDPOINTS]; static int mv_pullup(struct usb_gadget *gadget, int is_on); static int mv_ep_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc); @@ -79,14 +89,115 @@ static struct usb_ep_ops mv_ep_ops = { .free_request = mv_ep_free_request, }; -static struct mv_ep ep[2 * NUM_ENDPOINTS]; +/* Init values for USB endpoints. */ +static const struct usb_ep mv_ep_init[2] = { + [0] = { /* EP 0 */ + .maxpacket = 64, + .name = "ep0", + .ops = &mv_ep_ops, + }, + [1] = { /* EP 1..n */ + .maxpacket = 512, + .name = "ep-", + .ops = &mv_ep_ops, + }, +}; + static struct mv_drv controller = { - .gadget = { - .ep0 = &ep[0].ep, - .name = "mv_udc", + .gadget = { + .name = "mv_udc", + .ops = &mv_udc_ops, }, }; +/** + * mv_get_qh() - return queue head for endpoint + * @ep_num: Endpoint number + * @dir_in: Direction of the endpoint (IN = 1, OUT = 0) + * + * This function returns the QH associated with particular endpoint + * and it's direction. + */ +static struct ept_queue_head *mv_get_qh(int ep_num, int dir_in) +{ + return &controller.epts[(ep_num * 2) + dir_in]; +} + +/** + * mv_get_qtd() - return queue item for endpoint + * @ep_num: Endpoint number + * @dir_in: Direction of the endpoint (IN = 1, OUT = 0) + * + * This function returns the QH associated with particular endpoint + * and it's direction. + */ +static struct ept_queue_item *mv_get_qtd(int ep_num, int dir_in) +{ + return controller.items[(ep_num * 2) + dir_in]; +} + +/** + * mv_flush_qh - flush cache over queue head + * @ep_num: Endpoint number + * + * This function flushes cache over QH for particular endpoint. + */ +static void mv_flush_qh(int ep_num) +{ + struct ept_queue_head *head = mv_get_qh(ep_num, 0); + const uint32_t start = (uint32_t)head; + const uint32_t end = start + 2 * sizeof(*head); + + flush_dcache_range(start, end); +} + +/** + * mv_invalidate_qh - invalidate cache over queue head + * @ep_num: Endpoint number + * + * This function invalidates cache over QH for particular endpoint. + */ +static void mv_invalidate_qh(int ep_num) +{ + struct ept_queue_head *head = mv_get_qh(ep_num, 0); + uint32_t start = (uint32_t)head; + uint32_t end = start + 2 * sizeof(*head); + + invalidate_dcache_range(start, end); +} + +/** + * mv_flush_qtd - flush cache over queue item + * @ep_num: Endpoint number + * + * This function flushes cache over qTD pair for particular endpoint. + */ +static void mv_flush_qtd(int ep_num) +{ + struct ept_queue_item *item = mv_get_qtd(ep_num, 0); + const uint32_t start = (uint32_t)item; + const uint32_t end_raw = start + 2 * sizeof(*item); + const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN); + + flush_dcache_range(start, end); +} + +/** + * mv_invalidate_qtd - invalidate cache over queue item + * @ep_num: Endpoint number + * + * This function invalidates cache over qTD pair for particular endpoint. + */ +static void mv_invalidate_qtd(int ep_num) +{ + struct ept_queue_item *item = mv_get_qtd(ep_num, 0); + const uint32_t start = (uint32_t)item; + const uint32_t end_raw = start + 2 * sizeof(*item); + const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN); + + invalidate_dcache_range(start, end); +} + static struct usb_request * mv_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags) { @@ -102,9 +213,9 @@ static void mv_ep_free_request(struct usb_ep *ep, struct usb_request *_req) static void ep_enable(int num, int in) { struct ept_queue_head *head; - struct mv_udc *udc = controller.udc; + struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; unsigned n; - head = epts + 2*num + in; + head = mv_get_qh(num, in); n = readl(&udc->epctrl[num]); if (in) @@ -112,8 +223,10 @@ static void ep_enable(int num, int in) else n |= (CTRL_RXE | CTRL_RXR | CTRL_RXT_BULK); - if (num != 0) + if (num != 0) { head->config = CONFIG_MAX_PKT(EP_MAX_PACKET_SIZE) | CONFIG_ZLT; + mv_flush_qh(num); + } writel(n, &udc->epctrl[num]); } @@ -134,40 +247,108 @@ static int mv_ep_disable(struct usb_ep *ep) return 0; } +static int mv_bounce(struct mv_ep *ep) +{ + uint32_t addr = (uint32_t)ep->req.buf; + uint32_t ba; + + /* Input buffer address is not aligned. */ + if (addr & (ARCH_DMA_MINALIGN - 1)) + goto align; + + /* Input buffer length is not aligned. */ + if (ep->req.length & (ARCH_DMA_MINALIGN - 1)) + goto align; + + /* The buffer is well aligned, only flush cache. */ + ep->b_len = ep->req.length; + ep->b_buf = ep->req.buf; + goto flush; + +align: + /* Use internal buffer for small payloads. */ + if (ep->req.length <= 64) { + ep->b_len = 64; + ep->b_buf = ep->b_fast; + } else { + ep->b_len = roundup(ep->req.length, ARCH_DMA_MINALIGN); + ep->b_buf = memalign(ARCH_DMA_MINALIGN, ep->b_len); + if (!ep->b_buf) + return -ENOMEM; + } + + memcpy(ep->b_buf, ep->req.buf, ep->req.length); + +flush: + ba = (uint32_t)ep->b_buf; + flush_dcache_range(ba, ba + ep->b_len); + + return 0; +} + +static void mv_debounce(struct mv_ep *ep) +{ + uint32_t addr = (uint32_t)ep->req.buf; + uint32_t ba = (uint32_t)ep->b_buf; + + invalidate_dcache_range(ba, ba + ep->b_len); + + /* Input buffer address is not aligned. */ + if (addr & (ARCH_DMA_MINALIGN - 1)) + goto copy; + + /* Input buffer length is not aligned. */ + if (ep->req.length & (ARCH_DMA_MINALIGN - 1)) + goto copy; + + /* The buffer is well aligned, only invalidate cache. */ + return; + +copy: + memcpy(ep->req.buf, ep->b_buf, ep->req.length); + + /* Large payloads use allocated buffer, free it. */ + if (ep->req.length > 64) + free(ep->b_buf); +} + static int mv_ep_queue(struct usb_ep *ep, struct usb_request *req, gfp_t gfp_flags) { struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep); - struct mv_udc *udc = controller.udc; + struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; struct ept_queue_item *item; struct ept_queue_head *head; - unsigned phys; - int bit, num, len, in; + int bit, num, len, in, ret; num = mv_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; in = (mv_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; - item = items[2 * num + in]; - head = epts + 2 * num + in; - phys = (unsigned)req->buf; + item = mv_get_qtd(num, in); + head = mv_get_qh(num, in); len = req->length; + ret = mv_bounce(mv_ep); + if (ret) + return ret; + item->next = TERMINATE; item->info = INFO_BYTES(len) | INFO_IOC | INFO_ACTIVE; - item->page0 = phys; - item->page1 = (phys & 0xfffff000) + 0x1000; + item->page0 = (uint32_t)mv_ep->b_buf; + item->page1 = ((uint32_t)mv_ep->b_buf & 0xfffff000) + 0x1000; head->next = (unsigned) item; head->info = 0; - DBG("ept%d %s queue len %x, buffer %x\n", - num, in ? "in" : "out", len, phys); + DBG("ept%d %s queue len %x, buffer %p\n", + num, in ? "in" : "out", len, mv_ep->b_buf); if (in) bit = EPT_TX(num); else bit = EPT_RX(num); - flush_cache(phys, len); - flush_cache((unsigned long)item, sizeof(struct ept_queue_item)); + mv_flush_qh(num); + mv_flush_qtd(num); + writel(bit, &udc->epprime); return 0; @@ -181,13 +362,17 @@ static void handle_ep_complete(struct mv_ep *ep) in = (ep->desc->bEndpointAddress & USB_DIR_IN) != 0; if (num == 0) ep->desc = &ep0_out_desc; - item = items[2 * num + in]; - + item = mv_get_qtd(num, in); + mv_invalidate_qtd(num); + if (item->info & 0xff) printf("EP%d/%s FAIL nfo=%x pg0=%x\n", num, in ? "in" : "out", item->info, item->page0); len = (item->info >> 16) & 0x7fff; + + mv_debounce(ep); + ep->req.length -= len; DBG("ept%d %s complete %x\n", num, in ? "in" : "out", len); @@ -203,16 +388,16 @@ static void handle_ep_complete(struct mv_ep *ep) static void handle_setup(void) { - struct usb_request *req = &ep[0].req; - struct mv_udc *udc = controller.udc; + struct usb_request *req = &controller.ep[0].req; + struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; struct ept_queue_head *head; struct usb_ctrlrequest r; int status = 0; int num, in, _num, _in, i; char *buf; - head = epts; + head = mv_get_qh(0, 0); /* EP0 OUT */ - flush_cache((unsigned long)head, sizeof(struct ept_queue_head)); + mv_invalidate_qh(0); memcpy(&r, head->setup_data, sizeof(struct usb_ctrlrequest)); writel(EPT_RX(0), &udc->epstat); DBG("handle setup %s, %x, %x index %x value %x\n", reqname(r.bRequest), @@ -226,11 +411,11 @@ static void handle_setup(void) if ((r.wValue == 0) && (r.wLength == 0)) { req->length = 0; for (i = 0; i < NUM_ENDPOINTS; i++) { - if (!ep[i].desc) + if (!controller.ep[i].desc) continue; - num = ep[i].desc->bEndpointAddress - & USB_ENDPOINT_NUMBER_MASK; - in = (ep[i].desc->bEndpointAddress + num = controller.ep[i].desc->bEndpointAddress + & USB_ENDPOINT_NUMBER_MASK; + in = (controller.ep[i].desc->bEndpointAddress & USB_DIR_IN) != 0; if ((num == _num) && (in == _in)) { ep_enable(num, in); @@ -277,7 +462,7 @@ static void stop_activity(void) { int i, num, in; struct ept_queue_head *head; - struct mv_udc *udc = controller.udc; + struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; writel(readl(&udc->epcomp), &udc->epcomp); writel(readl(&udc->epstat), &udc->epstat); writel(0xffffffff, &udc->epflush); @@ -286,19 +471,21 @@ static void stop_activity(void) for (i = 0; i < NUM_ENDPOINTS; i++) { if (i != 0) writel(0, &udc->epctrl[i]); - if (ep[i].desc) { - num = ep[i].desc->bEndpointAddress + if (controller.ep[i].desc) { + num = controller.ep[i].desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; - in = (ep[i].desc->bEndpointAddress & USB_DIR_IN) != 0; - head = epts + (num * 2) + (in); + in = (controller.ep[i].desc->bEndpointAddress + & USB_DIR_IN) != 0; + head = mv_get_qh(num, in); head->info = INFO_ACTIVE; + mv_flush_qh(num); } } } void udc_irq(void) { - struct mv_udc *udc = controller.udc; + struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; unsigned n = readl(&udc->usbsts); writel(n, &udc->usbsts); int bit, i, num, in; @@ -320,8 +507,8 @@ void udc_irq(void) if (bit == 2) { controller.gadget.speed = USB_SPEED_HIGH; for (i = 1; i < NUM_ENDPOINTS && n; i++) - if (ep[i].desc) - ep[i].ep.maxpacket = 512; + if (controller.ep[i].desc) + controller.ep[i].ep.maxpacket = 512; } else { controller.gadget.speed = USB_SPEED_FULL; } @@ -340,14 +527,14 @@ void udc_irq(void) writel(n, &udc->epcomp); for (i = 0; i < NUM_ENDPOINTS && n; i++) { - if (ep[i].desc) { - num = ep[i].desc->bEndpointAddress + if (controller.ep[i].desc) { + num = controller.ep[i].desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; - in = (ep[i].desc->bEndpointAddress + in = (controller.ep[i].desc->bEndpointAddress & USB_DIR_IN) != 0; bit = (in) ? EPT_TX(num) : EPT_RX(num); if (n & bit) - handle_ep_complete(&ep[i]); + handle_ep_complete(&controller.ep[i]); } } } @@ -356,7 +543,7 @@ void udc_irq(void) int usb_gadget_handle_interrupts(void) { u32 value; - struct mv_udc *udc = controller.udc; + struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; value = readl(&udc->usbsts); if (value) @@ -367,13 +554,13 @@ int usb_gadget_handle_interrupts(void) static int mv_pullup(struct usb_gadget *gadget, int is_on) { - struct mv_udc *udc = controller.udc; + struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; if (is_on) { /* RESET */ writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, &udc->usbcmd); udelay(200); - writel((unsigned) epts, &udc->epinitaddr); + writel((unsigned)controller.epts, &udc->epinitaddr); /* select DEVICE mode */ writel(USBMODE_DEVICE, &udc->usbmode); @@ -395,7 +582,7 @@ static int mv_pullup(struct usb_gadget *gadget, int is_on) void udc_disconnect(void) { - struct mv_udc *udc = controller.udc; + struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; /* disable pullup */ stop_activity(); writel(USBCMD_FS2, &udc->usbcmd); @@ -407,18 +594,48 @@ void udc_disconnect(void) static int mvudc_probe(void) { struct ept_queue_head *head; + uint8_t *imem; int i; - controller.gadget.ops = &mv_udc_ops; - controller.udc = (struct mv_udc *)CONFIG_USB_REG_BASE; - epts = memalign(PAGE_SIZE, QH_MAXNUM * sizeof(struct ept_queue_head)); - memset(epts, 0, QH_MAXNUM * sizeof(struct ept_queue_head)); + const int num = 2 * NUM_ENDPOINTS; + + const int eplist_min_align = 4096; + const int eplist_align = roundup(eplist_min_align, ARCH_DMA_MINALIGN); + const int eplist_raw_sz = num * sizeof(struct ept_queue_head); + const int eplist_sz = roundup(eplist_raw_sz, ARCH_DMA_MINALIGN); + + const int ilist_align = roundup(ARCH_DMA_MINALIGN, 32); + const int ilist_ent_raw_sz = 2 * sizeof(struct ept_queue_item); + const int ilist_ent_sz = roundup(ilist_ent_raw_sz, ARCH_DMA_MINALIGN); + const int ilist_sz = NUM_ENDPOINTS * ilist_ent_sz; + + /* The QH list must be aligned to 4096 bytes. */ + controller.epts = memalign(eplist_align, eplist_sz); + if (!controller.epts) + return -ENOMEM; + memset(controller.epts, 0, eplist_sz); + + /* + * Each qTD item must be 32-byte aligned, each qTD touple must be + * cacheline aligned. There are two qTD items for each endpoint and + * only one of them is used for the endpoint at time, so we can group + * them together. + */ + controller.items_mem = memalign(ilist_align, ilist_sz); + if (!controller.items_mem) { + free(controller.epts); + return -ENOMEM; + } + for (i = 0; i < 2 * NUM_ENDPOINTS; i++) { /* - * For item0 and item1, they are served as ep0 - * out&in seperately + * Configure QH for each endpoint. The structure of the QH list + * is such that each two subsequent fields, N and N+1 where N is + * even, in the QH list represent QH for one endpoint. The Nth + * entry represents OUT configuration and the N+1th entry does + * represent IN configuration of the endpoint. */ - head = epts + i; + head = controller.epts + i; if (i < 2) head->config = CONFIG_MAX_PKT(EP0_MAX_PACKET_SIZE) | CONFIG_ZLT | CONFIG_IOS; @@ -428,49 +645,65 @@ static int mvudc_probe(void) head->next = TERMINATE; head->info = 0; - items[i] = memalign(PAGE_SIZE, sizeof(struct ept_queue_item)); + imem = controller.items_mem + ((i >> 1) * ilist_ent_sz); + if (i & 1) + imem += sizeof(struct ept_queue_item); + + controller.items[i] = (struct ept_queue_item *)imem; + + if (i & 1) { + mv_flush_qh(i - 1); + mv_flush_qtd(i - 1); + } } INIT_LIST_HEAD(&controller.gadget.ep_list); - ep[0].ep.maxpacket = 64; - ep[0].ep.name = "ep0"; - ep[0].desc = &ep0_in_desc; + + /* Init EP 0 */ + memcpy(&controller.ep[0].ep, &mv_ep_init[0], sizeof(*mv_ep_init)); + controller.ep[0].desc = &ep0_in_desc; + controller.gadget.ep0 = &controller.ep[0].ep; INIT_LIST_HEAD(&controller.gadget.ep0->ep_list); - for (i = 0; i < 2 * NUM_ENDPOINTS; i++) { - if (i != 0) { - ep[i].ep.maxpacket = 512; - ep[i].ep.name = "ep-"; - list_add_tail(&ep[i].ep.ep_list, - &controller.gadget.ep_list); - ep[i].desc = NULL; - } - ep[i].ep.ops = &mv_ep_ops; + + /* Init EP 1..n */ + for (i = 1; i < NUM_ENDPOINTS; i++) { + memcpy(&controller.ep[i].ep, &mv_ep_init[1], + sizeof(*mv_ep_init)); + list_add_tail(&controller.ep[i].ep.ep_list, + &controller.gadget.ep_list); } + return 0; } int usb_gadget_register_driver(struct usb_gadget_driver *driver) { - struct mv_udc *udc = controller.udc; - int retval; - - if (!driver - || driver->speed < USB_SPEED_FULL - || !driver->bind - || !driver->setup) { - DBG("bad parameter.\n"); + struct mv_udc *udc; + int ret; + + if (!driver) return -EINVAL; - } + if (!driver->bind || !driver->setup || !driver->disconnect) + return -EINVAL; + if (driver->speed != USB_SPEED_FULL && driver->speed != USB_SPEED_HIGH) + return -EINVAL; + + ret = usb_lowlevel_init(0, (void **)&controller.ctrl); + if (ret) + return ret; + + ret = mvudc_probe(); + if (!ret) { + udc = (struct mv_udc *)controller.ctrl->hcor; - if (!mvudc_probe()) { - usb_lowlevel_init(); /* select ULPI phy */ writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc); } - retval = driver->bind(&controller.gadget); - if (retval) { - DBG("driver->bind() returned %d\n", retval); - return retval; + + ret = driver->bind(&controller.gadget); + if (ret) { + DBG("driver->bind() returned %d\n", ret); + return ret; } controller.driver = driver; diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 706cf0c..fdad739 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -36,16 +36,7 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #endif -static struct ehci_ctrl { - struct ehci_hccr *hccr; /* R/O registers, not need for volatile */ - struct ehci_hcor *hcor; - int rootdev; - uint16_t portreset; - struct QH qh_list __aligned(USB_DMA_MINALIGN); - struct QH periodic_queue __aligned(USB_DMA_MINALIGN); - uint32_t *periodic_list; - int ntds; -} ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT]; +static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT]; #define ALIGN_END_ADDR(type, ptr, size) \ ((uint32_t)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN)) @@ -954,7 +945,9 @@ int usb_lowlevel_init(int index, void **controller) * Split Transactions will be spread across microframes using * S-mask and C-mask. */ - ehcic[index].periodic_list = memalign(4096, 1024*4); + if (ehcic[index].periodic_list == NULL) + ehcic[index].periodic_list = memalign(4096, 1024 * 4); + if (!ehcic[index].periodic_list) return -ENOMEM; for (i = 0; i < 1024; i++) { diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c index a47e078..032d5e5 100644 --- a/drivers/usb/host/ehci-omap.c +++ b/drivers/usb/host/ehci-omap.c @@ -28,18 +28,21 @@ static struct omap_ehci *const ehci = (struct omap_ehci *)OMAP_EHCI_BASE; static int omap_uhh_reset(void) { - unsigned long init = get_timer(0); - - /* perform UHH soft reset, and wait until reset is complete */ - writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc); - - /* Wait for UHH reset to complete */ - while (!(readl(&uhh->syss) & OMAP_UHH_SYSSTATUS_EHCI_RESETDONE)) - if (get_timer(init) > CONFIG_SYS_HZ) { - debug("OMAP UHH error: timeout resetting ehci\n"); - return -EL3RST; - } - +/* + * Soft resetting the UHH module causes instability issues on + * all OMAPs so we just avoid it. + * + * See OMAP36xx Errata + * i571: USB host EHCI may stall when entering smart-standby mode + * i660: USBHOST Configured In Smart-Idle Can Lead To a Deadlock + * + * On OMAP4/5, soft-resetting the UHH module will put it into + * Smart-Idle mode and lead to a deadlock. + * + * On OMAP3, this doesn't seem to be the case but still instabilities + * are observed on beagle (3530 ES1.0) if soft-reset is used. + * e.g. NFS root failures with Linux kernel. + */ return 0; } diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index d090f0a..bd52afe 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -22,6 +22,8 @@ #ifndef USB_EHCI_H #define USB_EHCI_H +#include <usb.h> + #if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 #endif @@ -252,6 +254,17 @@ struct QH { }; }; +struct ehci_ctrl { + struct ehci_hccr *hccr; /* R/O registers, not need for volatile */ + struct ehci_hcor *hcor; + int rootdev; + uint16_t portreset; + struct QH qh_list __aligned(USB_DMA_MINALIGN); + struct QH periodic_queue __aligned(USB_DMA_MINALIGN); + uint32_t *periodic_list; + int ntds; +}; + /* Low level init functions */ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor); int ehci_hcd_stop(int index); diff --git a/drivers/video/Makefile b/drivers/video/Makefile index f1fb26c..6dee1e9 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -19,6 +19,7 @@ COBJS-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \ exynos_mipi_dsi_lowlevel.o COBJS-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o +COBJS-$(CONFIG_L5F31188) += l5f31188.o COBJS-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o COBJS-$(CONFIG_PXA_LCD) += pxa_lcd.o COBJS-$(CONFIG_S6E8AX0) += s6e8ax0.o diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 96ef8f9..fd28855 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -197,7 +197,6 @@ #include <linux/types.h> #include <stdio_dev.h> #include <video_font.h> -#include <video_font_data.h> #if defined(CONFIG_CMD_DATE) #include <rtc.h> @@ -431,6 +430,16 @@ static const int video_font_draw_table32[16][4] = { {0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff} }; +/* + * Implement a weak default function for boards that optionally + * need to skip the cfb initialization. + */ +__weak int board_cfb_skip(void) +{ + /* As default, don't skip cfb init */ + return 0; +} + static void video_drawchars(int xx, int yy, unsigned char *s, int count) { u8 *cdat, *dest, *dest0; @@ -452,6 +461,10 @@ static void video_drawchars(int xx, int yy, unsigned char *s, int count) ((u32 *) dest)[0] = (video_font_draw_table8[bits >> 4] & eorx) ^ bgx; + + if (VIDEO_FONT_WIDTH == 4) + continue; + ((u32 *) dest)[1] = (video_font_draw_table8[bits & 15] & eorx) ^ bgx; @@ -477,6 +490,10 @@ static void video_drawchars(int xx, int yy, unsigned char *s, int count) SHORTSWAP32((video_font_draw_table15 [bits >> 4 & 3] & eorx) ^ bgx); + + if (VIDEO_FONT_WIDTH == 4) + continue; + ((u32 *) dest)[2] = SHORTSWAP32((video_font_draw_table15 [bits >> 2 & 3] & eorx) ^ @@ -507,6 +524,10 @@ static void video_drawchars(int xx, int yy, unsigned char *s, int count) SHORTSWAP32((video_font_draw_table16 [bits >> 4 & 3] & eorx) ^ bgx); + + if (VIDEO_FONT_WIDTH == 4) + continue; + ((u32 *) dest)[2] = SHORTSWAP32((video_font_draw_table16 [bits >> 2 & 3] & eorx) ^ @@ -541,6 +562,11 @@ static void video_drawchars(int xx, int yy, unsigned char *s, int count) ((u32 *) dest)[3] = SWAP32((video_font_draw_table32 [bits >> 4][3] & eorx) ^ bgx); + + + if (VIDEO_FONT_WIDTH == 4) + continue; + ((u32 *) dest)[4] = SWAP32((video_font_draw_table32 [bits & 15][0] & eorx) ^ bgx); @@ -576,6 +602,10 @@ static void video_drawchars(int xx, int yy, unsigned char *s, int count) ((u32 *) dest)[2] = (video_font_draw_table24[bits >> 4][2] & eorx) ^ bgx; + + if (VIDEO_FONT_WIDTH == 4) + continue; + ((u32 *) dest)[3] = (video_font_draw_table24[bits & 15][0] & eorx) ^ bgx; @@ -1996,6 +2026,8 @@ static void *video_logo(void) return video_fb_address + video_logo_height * VIDEO_LINE_LEN; } #endif + if (board_cfb_skip()) + return 0; sprintf(info, " %s", version_string); @@ -2205,6 +2237,9 @@ int drv_video_init(void) /* Init video chip - returns with framebuffer cleared */ skip_dev_init = (video_init() == -1); + if (board_cfb_skip()) + return 0; + #if !defined(CONFIG_VGA_AS_SINGLE_DEVICE) debug("KBD: Keyboard init ...\n"); skip_dev_init |= (VIDEO_KBD_INIT_FCT == -1); diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c index 373991d..3a5f325 100644 --- a/drivers/video/da8xx-fb.c +++ b/drivers/video/da8xx-fb.c @@ -24,10 +24,17 @@ #include <asm/arch/hardware.h> #include "videomodes.h" -#include <asm/arch/da8xx-fb.h> +#include "da8xx-fb.h" + +#if !defined(DA8XX_LCD_CNTL_BASE) +#define DA8XX_LCD_CNTL_BASE DAVINCI_LCD_CNTL_BASE +#endif #define DRIVER_NAME "da8xx_lcdc" +#define LCD_VERSION_1 1 +#define LCD_VERSION_2 2 + /* LCD Status Register */ #define LCD_END_OF_FRAME1 (1 << 9) #define LCD_END_OF_FRAME0 (1 << 8) @@ -42,9 +49,14 @@ #define LCD_DMA_BURST_4 0x2 #define LCD_DMA_BURST_8 0x3 #define LCD_DMA_BURST_16 0x4 -#define LCD_END_OF_FRAME_INT_ENA (1 << 2) +#define LCD_V1_END_OF_FRAME_INT_ENA (1 << 2) +#define LCD_V2_END_OF_FRAME0_INT_ENA (1 << 8) +#define LCD_V2_END_OF_FRAME1_INT_ENA (1 << 9) #define LCD_DUAL_FRAME_BUFFER_ENABLE (1 << 0) +#define LCD_V2_TFT_24BPP_MODE (1 << 25) +#define LCD_V2_TFT_24BPP_UNPACK (1 << 26) + /* LCD Control Register */ #define LCD_CLK_DIVISOR(x) ((x) << 8) #define LCD_RASTER_MODE 0x01 @@ -58,12 +70,20 @@ #define LCD_MONO_8BIT_MODE (1 << 9) #define LCD_RASTER_ORDER (1 << 8) #define LCD_TFT_MODE (1 << 7) -#define LCD_UNDERFLOW_INT_ENA (1 << 6) -#define LCD_PL_ENABLE (1 << 4) +#define LCD_V1_UNDERFLOW_INT_ENA (1 << 6) +#define LCD_V2_UNDERFLOW_INT_ENA (1 << 5) +#define LCD_V1_PL_INT_ENA (1 << 4) +#define LCD_V2_PL_INT_ENA (1 << 6) #define LCD_MONOCHROME_MODE (1 << 1) #define LCD_RASTER_ENABLE (1 << 0) #define LCD_TFT_ALT_ENABLE (1 << 23) #define LCD_STN_565_ENABLE (1 << 24) +#define LCD_V2_DMA_CLK_EN (1 << 2) +#define LCD_V2_LIDD_CLK_EN (1 << 1) +#define LCD_V2_CORE_CLK_EN (1 << 0) +#define LCD_V2_LPP_B10 26 +#define LCD_V2_TFT_24BPP_MODE (1 << 25) +#define LCD_V2_TFT_24BPP_UNPACK (1 << 26) /* LCD Raster Timing 2 Register */ #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16) @@ -74,6 +94,8 @@ #define LCD_INVERT_LINE_CLOCK (1 << 21) #define LCD_INVERT_FRAME_CLOCK (1 << 20) +/* Clock registers available only on Version 2 */ +#define LCD_CLK_MAIN_RESET (1 << 3) /* LCD Block */ struct da8xx_lcd_regs { u32 revid; @@ -97,6 +119,15 @@ struct da8xx_lcd_regs { u32 dma_frm_buf_ceiling_addr_0; u32 dma_frm_buf_base_addr_1; u32 dma_frm_buf_ceiling_addr_1; + u32 resv1; + u32 raw_stat; + u32 masked_stat; + u32 int_ena_set; + u32 int_ena_clr; + u32 end_of_int_ind; + /* Clock registers available only on Version 2 */ + u32 clk_ena; + u32 clk_reset; }; #define LCD_NUM_BUFFERS 1 @@ -107,6 +138,8 @@ struct da8xx_lcd_regs { #define RIGHT_MARGIN 64 #define UPPER_MARGIN 32 #define LOWER_MARGIN 32 +#define WAIT_FOR_FRAME_DONE true +#define NO_WAIT_FOR_FRAME_DONE false #define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP) @@ -119,6 +152,8 @@ static GraphicDevice gpanel; static const struct da8xx_panel *lcd_panel; static struct fb_info *da8xx_fb_info; static int bits_x_pixel; +static unsigned int lcd_revision; +const struct lcd_ctrl_config *da8xx_lcd_cfg; static inline unsigned int lcdc_read(u32 *addr) { @@ -179,35 +214,24 @@ static struct fb_fix_screeninfo da8xx_fb_fix = { .accel = FB_ACCEL_NONE }; -static const struct display_panel disp_panel = { - QVGA, - 16, - 16, - COLOR_ACTIVE, -}; - -static const struct lcd_ctrl_config lcd_cfg = { - &disp_panel, - .ac_bias = 255, - .ac_bias_intrpt = 0, - .dma_burst_sz = 16, - .bpp = 16, - .fdd = 255, - .tft_alt_mode = 0, - .stn_565_mode = 0, - .mono_8bit_mode = 0, - .invert_line_clock = 1, - .invert_frm_clock = 1, - .sync_edge = 0, - .sync_ctrl = 1, - .raster_order = 0, -}; - /* Enable the Raster Engine of the LCD Controller */ static inline void lcd_enable_raster(void) { u32 reg; + /* Put LCDC in reset for several cycles */ + if (lcd_revision == LCD_VERSION_2) + lcdc_write(LCD_CLK_MAIN_RESET, + &da8xx_fb_reg_base->clk_reset); + + udelay(1000); + /* Bring LCDC out of reset */ + if (lcd_revision == LCD_VERSION_2) + lcdc_write(0, + &da8xx_fb_reg_base->clk_reset); + + udelay(1000); + reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); if (!(reg & LCD_RASTER_ENABLE)) lcdc_write(reg | LCD_RASTER_ENABLE, @@ -215,14 +239,40 @@ static inline void lcd_enable_raster(void) } /* Disable the Raster Engine of the LCD Controller */ -static inline void lcd_disable_raster(void) +static inline void lcd_disable_raster(bool wait_for_frame_done) { u32 reg; + u32 loop_cnt = 0; + u32 stat; + u32 i = 0; + + if (wait_for_frame_done) + loop_cnt = 5000; reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); if (reg & LCD_RASTER_ENABLE) lcdc_write(reg & ~LCD_RASTER_ENABLE, &da8xx_fb_reg_base->raster_ctrl); + + /* Wait for the current frame to complete */ + do { + if (lcd_revision == LCD_VERSION_1) + stat = lcdc_read(&da8xx_fb_reg_base->stat); + else + stat = lcdc_read(&da8xx_fb_reg_base->raw_stat); + + mdelay(1); + } while (!(stat & 0x01) && (i++ < loop_cnt)); + + if (lcd_revision == LCD_VERSION_1) + lcdc_write(stat, &da8xx_fb_reg_base->stat); + else + lcdc_write(stat, &da8xx_fb_reg_base->raw_stat); + + if ((loop_cnt != 0) && (i >= loop_cnt)) { + printf("LCD Controller timed out\n"); + return; + } } static void lcd_blit(int load_mode, struct da8xx_fb_par *par) @@ -231,6 +281,7 @@ static void lcd_blit(int load_mode, struct da8xx_fb_par *par) u32 end; u32 reg_ras; u32 reg_dma; + u32 reg_int; /* init reg to clear PLM (loading mode) fields */ reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); @@ -243,7 +294,15 @@ static void lcd_blit(int load_mode, struct da8xx_fb_par *par) end = par->dma_end; reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY); - reg_dma |= LCD_END_OF_FRAME_INT_ENA; + if (lcd_revision == LCD_VERSION_1) { + reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA; + } else { + reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) | + LCD_V2_END_OF_FRAME0_INT_ENA | + LCD_V2_END_OF_FRAME1_INT_ENA | + LCD_V2_UNDERFLOW_INT_ENA | LCD_SYNC_LOST; + lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set); + } #if (LCD_NUM_BUFFERS == 2) reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE; @@ -264,7 +323,13 @@ static void lcd_blit(int load_mode, struct da8xx_fb_par *par) end = start + par->palette_sz - 1; reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY); - reg_ras |= LCD_PL_ENABLE; + if (lcd_revision == LCD_VERSION_1) { + reg_ras |= LCD_V1_PL_INT_ENA; + } else { + reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) | + LCD_V2_PL_INT_ENA; + lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set); + } lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); @@ -348,6 +413,7 @@ static void lcd_cfg_vertical_sync(int back_porch, int pulse_width, static int lcd_cfg_display(const struct lcd_ctrl_config *cfg) { u32 reg; + u32 reg_int; reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE | LCD_MONO_8BIT_MODE | @@ -375,7 +441,13 @@ static int lcd_cfg_display(const struct lcd_ctrl_config *cfg) } /* enable additional interrupts here */ - reg |= LCD_UNDERFLOW_INT_ENA; + if (lcd_revision == LCD_VERSION_1) { + reg |= LCD_V1_UNDERFLOW_INT_ENA; + } else { + reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) | + LCD_V2_UNDERFLOW_INT_ENA; + lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set); + } lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl); @@ -413,22 +485,53 @@ static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height, /* Set the Panel Width */ /* Pixels per line = (PPL + 1)*16 */ - /*0x3F in bits 4..9 gives max horisontal resolution = 1024 pixels*/ - width &= 0x3f0; + if (lcd_revision == LCD_VERSION_1) { + /* + * 0x3F in bits 4..9 gives max horisontal resolution = 1024 + * pixels + */ + width &= 0x3f0; + } else { + /* + * 0x7F in bits 4..10 gives max horizontal resolution = 2048 + * pixels. + */ + width &= 0x7f0; + } reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0); reg &= 0xfffffc00; - reg |= ((width >> 4) - 1) << 4; + if (lcd_revision == LCD_VERSION_1) { + reg |= ((width >> 4) - 1) << 4; + } else { + width = (width >> 4) - 1; + reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3); + } lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0); /* Set the Panel Height */ + /* Set bits 9:0 of Lines Per Pixel */ reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1); reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00); lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1); + /* Set bit 10 of Lines Per Pixel */ + if (lcd_revision == LCD_VERSION_2) { + reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2); + reg |= ((height - 1) & 0x400) << 16; + lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2); + } + /* Set the Raster Order of the Frame Buffer */ reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8); if (raster_order) reg |= LCD_RASTER_ORDER; + + if (bpp == 24) + reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE); + else if (bpp == 32) + reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE + | LCD_V2_TFT_24BPP_UNPACK); + lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl); switch (bpp) { @@ -436,6 +539,8 @@ static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height, case 2: case 4: case 16: + case 24: + case 32: par->palette_sz = 16 * 2; break; @@ -494,6 +599,23 @@ static int fb_setcolreg(unsigned regno, unsigned red, unsigned green, update_hw = 1; palette[0] = 0x4000; } + } else if (((info->var.bits_per_pixel == 32) && regno < 32) || + ((info->var.bits_per_pixel == 24) && regno < 24)) { + red >>= (24 - info->var.red.length); + red <<= info->var.red.offset; + + green >>= (24 - info->var.green.length); + green <<= info->var.green.offset; + + blue >>= (24 - info->var.blue.length); + blue <<= info->var.blue.offset; + + par->pseudo_palette[regno] = red | green | blue; + + if (palette[0] != 0x4000) { + update_hw = 1; + palette[0] = 0x4000; + } } /* Update the palette in the h/w as needed. */ @@ -506,11 +628,18 @@ static int fb_setcolreg(unsigned regno, unsigned red, unsigned green, static void lcd_reset(struct da8xx_fb_par *par) { /* Disable the Raster if previously Enabled */ - lcd_disable_raster(); + lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE); /* DMA has to be disabled */ lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl); lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl); + + if (lcd_revision == LCD_VERSION_2) { + lcdc_write(0, &da8xx_fb_reg_base->int_ena_set); + /* Write 1 to reset */ + lcdc_write(LCD_CLK_MAIN_RESET, &da8xx_fb_reg_base->clk_reset); + lcdc_write(0, &da8xx_fb_reg_base->clk_reset); + } } static void lcd_calc_clk_divider(struct da8xx_fb_par *par) @@ -521,12 +650,17 @@ static void lcd_calc_clk_divider(struct da8xx_fb_par *par) lcd_clk = clk_get(2); div = lcd_clk / par->pxl_clk; - debug("LCD Clock: 0x%x Divider: 0x%x PixClk: 0x%x\n", - lcd_clk, div, par->pxl_clk); + debug("LCD Clock: %d Divider: %d PixClk: %d\n", + lcd_clk, div, par->pxl_clk); /* Configure the LCD clock divisor. */ lcdc_write(LCD_CLK_DIVISOR(div) | (LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl); + + if (lcd_revision == LCD_VERSION_2) + lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN | + LCD_V2_CORE_CLK_EN, + &da8xx_fb_reg_base->clk_ena); } static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg, @@ -566,7 +700,8 @@ static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg, if (ret < 0) return ret; - if (QVGA != cfg->p_disp_panel->panel_type) + if ((QVGA != cfg->p_disp_panel->panel_type) && + (WVGA != cfg->p_disp_panel->panel_type)) return -EINVAL; if (cfg->bpp <= cfg->p_disp_panel->max_bpp && @@ -602,7 +737,7 @@ static void lcdc_dma_start(void) &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); } -static u32 lcdc_irq_handler(void) +static u32 lcdc_irq_handler_rev01(void) { struct da8xx_fb_par *par = da8xx_fb_info->par; u32 stat = lcdc_read(&da8xx_fb_reg_base->stat); @@ -610,7 +745,7 @@ static u32 lcdc_irq_handler(void) if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { debug("LCD_SYNC_LOST\n"); - lcd_disable_raster(); + lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE); lcdc_write(stat, &da8xx_fb_reg_base->stat); lcd_enable_raster(); return LCD_SYNC_LOST; @@ -622,13 +757,13 @@ static u32 lcdc_irq_handler(void) * interrupt via the following write to the status register. If * this is done after then one gets multiple PL done interrupts. */ - lcd_disable_raster(); + lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE); lcdc_write(stat, &da8xx_fb_reg_base->stat); /* Disable PL completion inerrupt */ reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); - reg_ras &= ~LCD_PL_ENABLE; + reg_ras &= ~LCD_V1_PL_INT_ENA; lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl); /* Setup and start data loading mode */ @@ -650,6 +785,66 @@ static u32 lcdc_irq_handler(void) return stat; } +static u32 lcdc_irq_handler_rev02(void) +{ + struct da8xx_fb_par *par = da8xx_fb_info->par; + u32 stat = lcdc_read(&da8xx_fb_reg_base->masked_stat); + u32 reg_int; + + if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { + debug("LCD_SYNC_LOST\n"); + lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE); + lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); + lcd_enable_raster(); + lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); + return LCD_SYNC_LOST; + } else if (stat & LCD_PL_LOAD_DONE) { + debug("LCD_PL_LOAD_DONE\n"); + /* + * Must disable raster before changing state of any control bit. + * And also must be disabled before clearing the PL loading + * interrupt via the following write to the status register. If + * this is done after then one gets multiple PL done interrupts. + */ + lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE); + + lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); + + /* Disable PL completion inerrupt */ + reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_clr) | + (LCD_V2_PL_INT_ENA); + lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_clr); + + /* Setup and start data loading mode */ + lcd_blit(LOAD_DATA, par); + lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); + return LCD_PL_LOAD_DONE; + } else { + lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); + + if (stat & LCD_END_OF_FRAME0) + debug("LCD_END_OF_FRAME0\n"); + + lcdc_write(par->dma_start, + &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); + lcdc_write(par->dma_end, + &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); + par->vsync_flag = 1; + lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); + return LCD_END_OF_FRAME0; + } + lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); + return stat; +} + +static u32 lcdc_irq_handler(void) +{ + if (lcd_revision == LCD_VERSION_1) + return lcdc_irq_handler_rev01(); + else + return lcdc_irq_handler_rev02(); +} + static u32 wait_for_event(u32 event) { u32 timeout = 50000; @@ -673,6 +868,7 @@ void *video_hw_init(void) { struct da8xx_fb_par *par; u32 size; + u32 rev; char *p; if (!lcd_panel) { @@ -685,6 +881,10 @@ void *video_hw_init(void) gpanel.plnSizeY = lcd_panel->height; switch (bits_x_pixel) { + case 32: + gpanel.gdfBytesPP = 4; + gpanel.gdfIndex = GDF_32BIT_X888RGB; + break; case 24: gpanel.gdfBytesPP = 4; gpanel.gdfIndex = GDF_32BIT_X888RGB; @@ -699,12 +899,29 @@ void *video_hw_init(void) break; } - da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DAVINCI_LCD_CNTL_BASE; + da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DA8XX_LCD_CNTL_BASE; + + /* Determine LCD IP Version */ + rev = lcdc_read(&da8xx_fb_reg_base->revid); + switch (rev) { + case 0x4C100102: + lcd_revision = LCD_VERSION_1; + break; + case 0x4F200800: + case 0x4F201000: + lcd_revision = LCD_VERSION_2; + break; + default: + printf("Unknown PID Reg value 0x%x, defaulting to LCD revision 1\n", + rev); + lcd_revision = LCD_VERSION_1; + break; + } - debug("Resolution: %dx%d %x\n", - gpanel.winSizeX, - gpanel.winSizeY, - lcd_cfg.bpp); + debug("rev: 0x%x Resolution: %dx%d %d\n", rev, + gpanel.winSizeX, + gpanel.winSizeY, + da8xx_lcd_cfg->bpp); size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par); da8xx_fb_info = malloc(size); @@ -722,13 +939,14 @@ void *video_hw_init(void) par = da8xx_fb_info->par; par->pxl_clk = lcd_panel->pxl_clk; - if (lcd_init(par, &lcd_cfg, lcd_panel) < 0) { + if (lcd_init(par, da8xx_lcd_cfg, lcd_panel) < 0) { printf("lcd_init failed\n"); goto err_release_fb; } /* allocate frame buffer */ - par->vram_size = lcd_panel->width * lcd_panel->height * lcd_cfg.bpp; + par->vram_size = lcd_panel->width * lcd_panel->height * + da8xx_lcd_cfg->bpp; par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8; par->vram_virt = malloc(par->vram_size); @@ -741,12 +959,13 @@ void *video_hw_init(void) printf("GLCD: malloc for frame buffer failed\n"); goto err_release_fb; } + gd->fb_base = (int)par->vram_virt; gpanel.frameAdrs = (unsigned int)par->vram_virt; da8xx_fb_info->screen_base = (char *) par->vram_virt; da8xx_fb_fix.smem_start = gpanel.frameAdrs; da8xx_fb_fix.smem_len = par->vram_size; - da8xx_fb_fix.line_length = (lcd_panel->width * lcd_cfg.bpp) / 8; + da8xx_fb_fix.line_length = (lcd_panel->width * da8xx_lcd_cfg->bpp) / 8; par->dma_start = par->vram_phys; par->dma_end = par->dma_start + lcd_panel->height * @@ -762,7 +981,7 @@ void *video_hw_init(void) par->p_palette_base = (unsigned int)par->v_palette_base; /* Initialize par */ - da8xx_fb_info->var.bits_per_pixel = lcd_cfg.bpp; + da8xx_fb_info->var.bits_per_pixel = da8xx_lcd_cfg->bpp; da8xx_fb_var.xres = lcd_panel->width; da8xx_fb_var.xres_virtual = lcd_panel->width; @@ -771,8 +990,8 @@ void *video_hw_init(void) da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS; da8xx_fb_var.grayscale = - lcd_cfg.p_disp_panel->panel_shade == MONOCHROME ? 1 : 0; - da8xx_fb_var.bits_per_pixel = lcd_cfg.bpp; + da8xx_lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0; + da8xx_fb_var.bits_per_pixel = da8xx_lcd_cfg->bpp; da8xx_fb_var.hsync_len = lcd_panel->hsw; da8xx_fb_var.vsync_len = lcd_panel->vsw; @@ -787,8 +1006,11 @@ void *video_hw_init(void) /* Clear interrupt */ memset((void *)par->vram_virt, 0, par->vram_size); - lcd_disable_raster(); - lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat); + lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE); + if (lcd_revision == LCD_VERSION_1) + lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat); + else + lcdc_write(0xFFFF, &da8xx_fb_reg_base->masked_stat); debug("Palette at 0x%x size %d\n", par->p_palette_base, par->palette_sz); lcdc_dma_start(); @@ -823,8 +1045,10 @@ void video_set_lut(unsigned int index, /* color number */ return; } -void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel) +void da8xx_video_init(const struct da8xx_panel *panel, + const struct lcd_ctrl_config *lcd_cfg, int bits_pixel) { lcd_panel = panel; + da8xx_lcd_cfg = lcd_cfg; bits_x_pixel = bits_pixel; } diff --git a/drivers/video/da8xx-fb.h b/drivers/video/da8xx-fb.h new file mode 100644 index 0000000..6447a40 --- /dev/null +++ b/drivers/video/da8xx-fb.h @@ -0,0 +1,116 @@ +/* + * Porting to u-boot: + * + * (C) Copyright 2011 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * Copyright (C) 2008-2009 MontaVista Software Inc. + * Copyright (C) 2008-2009 Texas Instruments Inc + * + * Based on the LCD driver for TI Avalanche processors written by + * Ajay Singh and Shalom Hai. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef DA8XX_FB_H +#define DA8XX_FB_H + +enum panel_type { + QVGA = 0, + WVGA +}; + +enum panel_shade { + MONOCHROME = 0, + COLOR_ACTIVE, + COLOR_PASSIVE, +}; + +enum raster_load_mode { + LOAD_DATA = 1, + LOAD_PALETTE, +}; + +struct display_panel { + enum panel_type panel_type; /* QVGA */ + int max_bpp; + int min_bpp; + enum panel_shade panel_shade; +}; + +struct da8xx_panel { + const char name[25]; /* Full name <vendor>_<model> */ + unsigned short width; + unsigned short height; + int hfp; /* Horizontal front porch */ + int hbp; /* Horizontal back porch */ + int hsw; /* Horizontal Sync Pulse Width */ + int vfp; /* Vertical front porch */ + int vbp; /* Vertical back porch */ + int vsw; /* Vertical Sync Pulse Width */ + unsigned int pxl_clk; /* Pixel clock */ + unsigned char invert_pxl_clk; /* Invert Pixel clock */ +}; + +struct da8xx_lcdc_platform_data { + const char manu_name[10]; + void *controller_data; + const char type[25]; + void (*panel_power_ctrl)(int); +}; + +struct lcd_ctrl_config { + const struct display_panel *p_disp_panel; + + /* AC Bias Pin Frequency */ + int ac_bias; + + /* AC Bias Pin Transitions per Interrupt */ + int ac_bias_intrpt; + + /* DMA burst size */ + int dma_burst_sz; + + /* Bits per pixel */ + int bpp; + + /* FIFO DMA Request Delay */ + int fdd; + + /* TFT Alternative Signal Mapping (Only for active) */ + unsigned char tft_alt_mode; + + /* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */ + unsigned char stn_565_mode; + + /* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */ + unsigned char mono_8bit_mode; + + /* Invert line clock */ + unsigned char invert_line_clock; + + /* Invert frame clock */ + unsigned char invert_frm_clock; + + /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */ + unsigned char sync_edge; + + /* Horizontal and Vertical Sync: Control: 0=ignore */ + unsigned char sync_ctrl; + + /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */ + unsigned char raster_order; +}; + +struct lcd_sync_arg { + int back_porch; + int front_porch; + int pulse_width; +}; + +void da8xx_video_init(const struct da8xx_panel *panel, + const struct lcd_ctrl_config *lcd_cfg, + int bits_pixel); + +#endif /* ifndef DA8XX_FB_H */ diff --git a/drivers/video/exynos_mipi_dsi_common.c b/drivers/video/exynos_mipi_dsi_common.c index 2cc847f..97e1248 100644 --- a/drivers/video/exynos_mipi_dsi_common.c +++ b/drivers/video/exynos_mipi_dsi_common.c @@ -50,7 +50,7 @@ static unsigned int dpll_table[15] = { }; static void exynos_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim, - unsigned int data0, unsigned int data1) + const unsigned char *data0, unsigned int data1) { unsigned int data_cnt = 0, payload = 0; @@ -62,42 +62,40 @@ static void exynos_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim, */ if ((data1 - data_cnt) < 4) { if ((data1 - data_cnt) == 3) { - payload = *(u8 *)(data0 + data_cnt) | - (*(u8 *)(data0 + (data_cnt + 1))) << 8 | - (*(u8 *)(data0 + (data_cnt + 2))) << 16; + payload = data0[data_cnt] | + data0[data_cnt + 1] << 8 | + data0[data_cnt + 2] << 16; debug("count = 3 payload = %x, %x %x %x\n", - payload, *(u8 *)(data0 + data_cnt), - *(u8 *)(data0 + (data_cnt + 1)), - *(u8 *)(data0 + (data_cnt + 2))); + payload, data0[data_cnt], + data0[data_cnt + 1], + data0[data_cnt + 2]); } else if ((data1 - data_cnt) == 2) { - payload = *(u8 *)(data0 + data_cnt) | - (*(u8 *)(data0 + (data_cnt + 1))) << 8; + payload = data0[data_cnt] | + data0[data_cnt + 1] << 8; debug("count = 2 payload = %x, %x %x\n", payload, - *(u8 *)(data0 + data_cnt), - *(u8 *)(data0 + (data_cnt + 1))); + data0[data_cnt], data0[data_cnt + 1]); } else if ((data1 - data_cnt) == 1) { - payload = *(u8 *)(data0 + data_cnt); + payload = data0[data_cnt]; } } else { /* send 4bytes per one time. */ - payload = *(u8 *)(data0 + data_cnt) | - (*(u8 *)(data0 + (data_cnt + 1))) << 8 | - (*(u8 *)(data0 + (data_cnt + 2))) << 16 | - (*(u8 *)(data0 + (data_cnt + 3))) << 24; + payload = data0[data_cnt] | + data0[data_cnt + 1] << 8 | + data0[data_cnt + 2] << 16 | + data0[data_cnt + 3] << 24; debug("count = 4 payload = %x, %x %x %x %x\n", payload, *(u8 *)(data0 + data_cnt), - *(u8 *)(data0 + (data_cnt + 1)), - *(u8 *)(data0 + (data_cnt + 2)), - *(u8 *)(data0 + (data_cnt + 3))); - + data0[data_cnt + 1], + data0[data_cnt + 2], + data0[data_cnt + 3]); } exynos_mipi_dsi_wr_tx_data(dsim, payload); } } int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id, - unsigned int data0, unsigned int data1) + const unsigned char *data0, unsigned int data1) { unsigned int timeout = TRY_GET_FIFO_TIMEOUT; unsigned long delay_val, delay; @@ -136,8 +134,8 @@ int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id, case MIPI_DSI_DCS_SHORT_WRITE_PARAM: case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE: debug("data0 = %x data1 = %x\n", - data0, data1); - exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0, data1); + data0[0], data0[1]); + exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]); if (check_rx_ack) { /* process response func should be implemented */ return 0; @@ -150,7 +148,7 @@ int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id, case MIPI_DSI_COLOR_MODE_ON: case MIPI_DSI_SHUTDOWN_PERIPHERAL: case MIPI_DSI_TURN_ON_PERIPHERAL: - exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0, data1); + exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]); if (check_rx_ack) { /* process response func should be implemented. */ return 0; @@ -172,7 +170,7 @@ int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id, case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: case MIPI_DSI_DCS_READ: exynos_mipi_dsi_clear_all_interrupt(dsim); - exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0, data1); + exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]); /* process response func should be implemented. */ return 0; @@ -183,21 +181,19 @@ int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id, case MIPI_DSI_GENERIC_LONG_WRITE: case MIPI_DSI_DCS_LONG_WRITE: { - unsigned int data_cnt = 0, payload = 0; + unsigned int payload = 0; /* if data count is less then 4, then send 3bytes data. */ if (data1 < 4) { - payload = *(u8 *)(data0) | - *(u8 *)(data0 + 1) << 8 | - *(u8 *)(data0 + 2) << 16; + payload = data0[0] | + data0[1] << 8 | + data0[2] << 16; exynos_mipi_dsi_wr_tx_data(dsim, payload); debug("count = %d payload = %x,%x %x %x\n", - data1, payload, - *(u8 *)(data0 + data_cnt), - *(u8 *)(data0 + (data_cnt + 1)), - *(u8 *)(data0 + (data_cnt + 2))); + data1, payload, data0[0], + data0[1], data0[2]); } else { /* in case that data count is more then 4 */ exynos_mipi_dsi_long_data_wr(dsim, data0, data1); diff --git a/drivers/video/exynos_mipi_dsi_common.h b/drivers/video/exynos_mipi_dsi_common.h index 318c7ec..ef6510a 100644 --- a/drivers/video/exynos_mipi_dsi_common.h +++ b/drivers/video/exynos_mipi_dsi_common.h @@ -13,7 +13,7 @@ #define _EXYNOS_MIPI_DSI_COMMON_H int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id, - unsigned int data0, unsigned int data1); + const unsigned char *data0, unsigned int data1); int exynos_mipi_dsi_pll_on(struct mipi_dsim_device *dsim, unsigned int enable); unsigned long exynos_mipi_dsi_change_pll(struct mipi_dsim_device *dsim, unsigned int pre_divider, unsigned int main_divider, diff --git a/drivers/video/exynos_mipi_dsi_lowlevel.c b/drivers/video/exynos_mipi_dsi_lowlevel.c index b47eee4..1313bce 100644 --- a/drivers/video/exynos_mipi_dsi_lowlevel.c +++ b/drivers/video/exynos_mipi_dsi_lowlevel.c @@ -600,7 +600,7 @@ unsigned int exynos_mipi_dsi_get_fifo_state(struct mipi_dsim_device *dsim) } void exynos_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim, - unsigned int di, unsigned int data0, unsigned int data1) + unsigned int di, const unsigned char data0, const unsigned char data1) { struct exynos_mipi_dsim *mipi_dsim = (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); diff --git a/drivers/video/exynos_mipi_dsi_lowlevel.h b/drivers/video/exynos_mipi_dsi_lowlevel.h index 8a45954..59f6ce0 100644 --- a/drivers/video/exynos_mipi_dsi_lowlevel.h +++ b/drivers/video/exynos_mipi_dsi_lowlevel.h @@ -91,7 +91,7 @@ unsigned int _exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim); void _exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim); void exynos_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim, - unsigned int di, unsigned int data0, unsigned int data1); + unsigned int di, const unsigned char data0, const unsigned char data1); void exynos_mipi_dsi_wr_tx_data(struct mipi_dsim_device *dsim, unsigned int tx_data); diff --git a/drivers/video/l5f31188.c b/drivers/video/l5f31188.c new file mode 100644 index 0000000..3312dcf --- /dev/null +++ b/drivers/video/l5f31188.c @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2013 Samsung Electronics Co., Ltd. All rights reserved. + * Hyungwon Hwang <human.hwang@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/mipi_dsim.h> + +#define SCAN_FROM_LEFT_TO_RIGHT 0 +#define SCAN_FROM_RIGHT_TO_LEFT 1 +#define SCAN_FROM_TOP_TO_BOTTOM 0 +#define SCAN_FROM_BOTTOM_TO_TOP 1 + +static void l5f31188_sleep_in(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x10, 0x00); +} + +static void l5f31188_sleep_out(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x11, 0x00); +} + +static void l5f31188_set_gamma(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x26, 0x00); +} + +static void l5f31188_display_off(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x28, 0x00); +} + +static void l5f31188_display_on(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x29, 0x00); +} + +static void l5f31188_ctl_memory_access(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops, + int h_direction, int v_direction) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x36, + (((h_direction & 0x1) << 1) | (v_direction & 0x1))); +} + +static void l5f31188_set_pixel_format(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x3A, 0x70); +} + +static void l5f31188_write_disbv(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops, unsigned int brightness) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x51, brightness); +} + +static void l5f31188_write_ctrld(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x53, 0x2C); +} + +static void l5f31188_write_cabc(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops, + unsigned int wm_mode) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x55, wm_mode); +} + +static void l5f31188_write_cabcmb(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops, unsigned int min_brightness) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x5E, + min_brightness); +} + +static void l5f31188_set_extension(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + const unsigned char data_to_send[] = { + 0xB9, 0xFF, 0x83, 0x94 + }; + + ops->cmd_write(dev, MIPI_DSI_DCS_LONG_WRITE, + (unsigned int)data_to_send, ARRAY_SIZE(data_to_send)); +} + +static void l5f31188_set_dgc_lut(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + const unsigned char data_to_send[] = { + 0xC1, 0x01, 0x00, 0x04, 0x0E, 0x18, 0x1E, 0x26, + 0x2F, 0x36, 0x3E, 0x47, 0x4E, 0x56, 0x5D, 0x65, + 0x6D, 0x75, 0x7D, 0x84, 0x8C, 0x94, 0x9C, 0xA4, + 0xAD, 0xB5, 0xBD, 0xC5, 0xCC, 0xD4, 0xDE, 0xE5, + 0xEE, 0xF7, 0xFF, 0x3F, 0x9A, 0xCE, 0xD4, 0x21, + 0xA1, 0x26, 0x54, 0x00, 0x00, 0x04, 0x0E, 0x19, + 0x1F, 0x27, 0x30, 0x37, 0x40, 0x48, 0x50, 0x58, + 0x60, 0x67, 0x6F, 0x77, 0x7F, 0x87, 0x8F, 0x97, + 0x9F, 0xA7, 0xB0, 0xB8, 0xC0, 0xC8, 0xCE, 0xD8, + 0xE0, 0xE7, 0xF0, 0xF7, 0xFF, 0x3C, 0xEB, 0xFD, + 0x2F, 0x66, 0xA8, 0x2C, 0x46, 0x00, 0x00, 0x04, + 0x0E, 0x18, 0x1E, 0x26, 0x30, 0x38, 0x41, 0x4A, + 0x52, 0x5A, 0x62, 0x6B, 0x73, 0x7B, 0x83, 0x8C, + 0x94, 0x9C, 0xA5, 0xAD, 0xB6, 0xBD, 0xC5, 0xCC, + 0xD4, 0xDD, 0xE3, 0xEB, 0xF2, 0xF9, 0xFF, 0x3F, + 0xA4, 0x8A, 0x8F, 0xC7, 0x33, 0xF5, 0xE9, 0x00 + }; + ops->cmd_write(dev, MIPI_DSI_DCS_LONG_WRITE, + (unsigned int)data_to_send, ARRAY_SIZE(data_to_send)); +} + +static void l5f31188_set_tcon(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + const unsigned char data_to_send[] = { + 0xC7, 0x00, 0x20 + }; + ops->cmd_write(dev, MIPI_DSI_DCS_LONG_WRITE, + (unsigned int)data_to_send, ARRAY_SIZE(data_to_send)); +} + +static void l5f31188_set_ptba(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + const unsigned char data_to_send[] = { + 0xBF, 0x06, 0x10 + }; + ops->cmd_write(dev, MIPI_DSI_DCS_LONG_WRITE, + (unsigned int)data_to_send, ARRAY_SIZE(data_to_send)); +} + +static void l5f31188_set_eco(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0xC6, 0x0C); +} + +static int l5f31188_panel_init(struct mipi_dsim_device *dev) +{ + struct mipi_dsim_master_ops *ops = dev->master_ops; + + l5f31188_set_extension(dev, ops); + l5f31188_set_dgc_lut(dev, ops); + + l5f31188_set_eco(dev, ops); + l5f31188_set_tcon(dev, ops); + l5f31188_set_ptba(dev, ops); + l5f31188_set_gamma(dev, ops); + l5f31188_ctl_memory_access(dev, ops, + SCAN_FROM_LEFT_TO_RIGHT, SCAN_FROM_TOP_TO_BOTTOM); + l5f31188_set_pixel_format(dev, ops); + l5f31188_write_disbv(dev, ops, 0xFF); + l5f31188_write_ctrld(dev, ops); + l5f31188_write_cabc(dev, ops, 0x0); + l5f31188_write_cabcmb(dev, ops, 0x0); + + l5f31188_sleep_out(dev, ops); + + /* 120 msec */ + udelay(120 * 1000); + + return 0; +} + +static void l5f31188_display_enable(struct mipi_dsim_device *dev) +{ + struct mipi_dsim_master_ops *ops = dev->master_ops; + l5f31188_display_on(dev, ops); +} + +static struct mipi_dsim_lcd_driver l5f31188_dsim_ddi_driver = { + .name = "l5f31188", + .id = -1, + + .mipi_panel_init = l5f31188_panel_init, + .mipi_display_on = l5f31188_display_enable, +}; + +void l5f31188_init(void) +{ + exynos_mipi_dsi_register_lcd_driver(&l5f31188_dsim_ddi_driver); +} diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index 6bf9fc5..03b0f88 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -15,11 +15,25 @@ #include <asm/errno.h> #include <asm/io.h> +#include <asm/imx-common/dma.h> + #include "videomodes.h" #define PS2KHZ(ps) (1000000000UL / (ps)) static GraphicDevice panel; +struct mxs_dma_desc desc; + +/** + * mxsfb_system_setup() - Fine-tune LCDIF configuration + * + * This function is used to adjust the LCDIF configuration. This is usually + * needed when driving the controller in System-Mode to operate an 8080 or + * 6800 connected SmartLCD. + */ +__weak void mxsfb_system_setup(void) +{ +} /* * DENX M28EVK: @@ -75,6 +89,9 @@ static void mxs_lcd_init(GraphicDevice *panel, writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET, ®s->hw_lcdif_ctrl1); + + mxsfb_system_setup(); + writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres, ®s->hw_lcdif_transfer_count); @@ -102,8 +119,10 @@ static void mxs_lcd_init(GraphicDevice *panel, /* Flush FIFO first */ writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_set); +#ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM /* Sync signals ON */ setbits_le32(®s->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON); +#endif /* FIFO cleared */ writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_clr); @@ -161,7 +180,8 @@ void *video_hw_init(void) panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP; /* Allocate framebuffer */ - fb = malloc(panel.memSize); + fb = memalign(ARCH_DMA_MINALIGN, + roundup(panel.memSize, ARCH_DMA_MINALIGN)); if (!fb) { printf("MXSFB: Error allocating framebuffer!\n"); return NULL; @@ -177,5 +197,28 @@ void *video_hw_init(void) /* Start framebuffer */ mxs_lcd_init(&panel, &mode, bpp); +#ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM + /* + * If the LCD runs in system mode, the LCD refresh has to be triggered + * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid + * having to set this bit manually after every single change in the + * framebuffer memory, we set up specially crafted circular DMA, which + * sets the RUN bit, then waits until it gets cleared and repeats this + * infinitelly. This way, we get smooth continuous updates of the LCD. + */ + struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; + + memset(&desc, 0, sizeof(struct mxs_dma_desc)); + desc.address = (dma_addr_t)&desc; + desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN | + MXS_DMA_DESC_WAIT4END | + (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET); + desc.cmd.pio_words[0] = readl(®s->hw_lcdif_ctrl) | LCDIF_CTRL_RUN; + desc.cmd.next = (uint32_t)&desc.cmd; + + /* Execute the DMA chain. */ + mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc); +#endif + return (void *)&panel; } diff --git a/drivers/video/s6e8ax0.c b/drivers/video/s6e8ax0.c index fc09252..0e97f51 100644 --- a/drivers/video/s6e8ax0.c +++ b/drivers/video/s6e8ax0.c @@ -34,11 +34,11 @@ static void s6e8ax0_panel_cond(struct mipi_dsim_device *dsim_dev) if (reverse) { ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - (unsigned int)data_to_send_reverse, + data_to_send_reverse, ARRAY_SIZE(data_to_send_reverse)); } else { ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - (unsigned int)data_to_send, ARRAY_SIZE(data_to_send)); + data_to_send, ARRAY_SIZE(data_to_send)); } } @@ -50,8 +50,7 @@ static void s6e8ax0_display_cond(struct mipi_dsim_device *dsim_dev) }; ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - (unsigned int)data_to_send, - ARRAY_SIZE(data_to_send)); + data_to_send, ARRAY_SIZE(data_to_send)); } static void s6e8ax0_gamma_cond(struct mipi_dsim_device *dsim_dev) @@ -65,15 +64,18 @@ static void s6e8ax0_gamma_cond(struct mipi_dsim_device *dsim_dev) }; ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - (unsigned int)data_to_send, - ARRAY_SIZE(data_to_send)); + data_to_send, ARRAY_SIZE(data_to_send)); } static void s6e8ax0_gamma_update(struct mipi_dsim_device *dsim_dev) { struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; + static const unsigned char data_to_send[] = { + 0xf7, 0x03 + }; - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0xf7, 0x3); + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, data_to_send, + ARRAY_SIZE(data_to_send)); } static void s6e8ax0_etc_source_control(struct mipi_dsim_device *dsim_dev) @@ -84,8 +86,7 @@ static void s6e8ax0_etc_source_control(struct mipi_dsim_device *dsim_dev) }; ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - (unsigned int)data_to_send, - ARRAY_SIZE(data_to_send)); + data_to_send, ARRAY_SIZE(data_to_send)); } static void s6e8ax0_etc_pentile_control(struct mipi_dsim_device *dsim_dev) @@ -97,8 +98,7 @@ static void s6e8ax0_etc_pentile_control(struct mipi_dsim_device *dsim_dev) }; ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - (unsigned int)data_to_send, - ARRAY_SIZE(data_to_send)); + data_to_send, ARRAY_SIZE(data_to_send)); } static void s6e8ax0_etc_mipi_control1(struct mipi_dsim_device *dsim_dev) @@ -109,8 +109,7 @@ static void s6e8ax0_etc_mipi_control1(struct mipi_dsim_device *dsim_dev) }; ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - (unsigned int)data_to_send, - ARRAY_SIZE(data_to_send)); + data_to_send, ARRAY_SIZE(data_to_send)); } static void s6e8ax0_etc_mipi_control2(struct mipi_dsim_device *dsim_dev) @@ -121,8 +120,7 @@ static void s6e8ax0_etc_mipi_control2(struct mipi_dsim_device *dsim_dev) }; ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - (unsigned int)data_to_send, - ARRAY_SIZE(data_to_send)); + data_to_send, ARRAY_SIZE(data_to_send)); } static void s6e8ax0_etc_power_control(struct mipi_dsim_device *dsim_dev) @@ -133,14 +131,18 @@ static void s6e8ax0_etc_power_control(struct mipi_dsim_device *dsim_dev) }; ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - (unsigned int)data_to_send, ARRAY_SIZE(data_to_send)); + data_to_send, ARRAY_SIZE(data_to_send)); } static void s6e8ax0_etc_mipi_control3(struct mipi_dsim_device *dsim_dev) { struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; + static const unsigned char data_to_send[] = { + 0xe3, 0x40 + }; - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0xe3, 0x40); + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, data_to_send, + ARRAY_SIZE(data_to_send)); } static void s6e8ax0_etc_mipi_control4(struct mipi_dsim_device *dsim_dev) @@ -151,7 +153,7 @@ static void s6e8ax0_etc_mipi_control4(struct mipi_dsim_device *dsim_dev) }; ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - (unsigned int)data_to_send, ARRAY_SIZE(data_to_send)); + data_to_send, ARRAY_SIZE(data_to_send)); } static void s6e8ax0_elvss_set(struct mipi_dsim_device *dsim_dev) @@ -162,24 +164,29 @@ static void s6e8ax0_elvss_set(struct mipi_dsim_device *dsim_dev) }; ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - (unsigned int)data_to_send, - ARRAY_SIZE(data_to_send)); + data_to_send, ARRAY_SIZE(data_to_send)); } static void s6e8ax0_display_on(struct mipi_dsim_device *dsim_dev) { struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; + static const unsigned char data_to_send[] = { + 0x29, 0x00 + }; - ops->cmd_write(dsim_dev, - MIPI_DSI_DCS_SHORT_WRITE, 0x29, 0x00); + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE, data_to_send, + ARRAY_SIZE(data_to_send)); } static void s6e8ax0_sleep_out(struct mipi_dsim_device *dsim_dev) { struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; + static const unsigned char data_to_send[] = { + 0x11, 0x00 + }; - ops->cmd_write(dsim_dev, - MIPI_DSI_DCS_SHORT_WRITE, 0x11, 0x00); + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE, data_to_send, + ARRAY_SIZE(data_to_send)); } static void s6e8ax0_apply_level1_key(struct mipi_dsim_device *dsim_dev) @@ -190,7 +197,7 @@ static void s6e8ax0_apply_level1_key(struct mipi_dsim_device *dsim_dev) }; ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - (unsigned int)data_to_send, ARRAY_SIZE(data_to_send)); + data_to_send, ARRAY_SIZE(data_to_send)); } static void s6e8ax0_apply_mtp_key(struct mipi_dsim_device *dsim_dev) @@ -201,7 +208,7 @@ static void s6e8ax0_apply_mtp_key(struct mipi_dsim_device *dsim_dev) }; ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, - (unsigned int)data_to_send, ARRAY_SIZE(data_to_send)); + data_to_send, ARRAY_SIZE(data_to_send)); } static void s6e8ax0_panel_init(struct mipi_dsim_device *dsim_dev) diff --git a/drivers/video/sed156x.c b/drivers/video/sed156x.c index d8b0d7f..f324354 100644 --- a/drivers/video/sed156x.c +++ b/drivers/video/sed156x.c @@ -25,7 +25,6 @@ /* include the font data */ #include <video_font.h> -#include <video_font_data.h> #if VIDEO_FONT_WIDTH != 8 || VIDEO_FONT_HEIGHT != 16 #error Expecting VIDEO_FONT_WIDTH == 8 && VIDEO_FONT_HEIGHT == 16 |