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-rw-r--r--include/asm-mips/addrspace.h2
-rw-r--r--include/asm-mips/io.h16
2 files changed, 16 insertions, 2 deletions
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index b8214b1..0e6abd7 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -49,7 +49,7 @@
cannot access physical memory directly from core */
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
#else /* !CONFIG_AU1X00 */
-#define UNCACHED_SDRAM(a) PHYSADDR(a)
+#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
#endif /* CONFIG_AU1X00 */
#endif /* __ASSEMBLY__ */
/*
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index cd4d5dc..1e060f7 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -71,7 +71,21 @@
* instruction, so the lower 16 bits must be zero. Should be true on
* on any sane architecture; generic code does not use this assumption.
*/
-extern unsigned long mips_io_port_base;
+extern const unsigned long mips_io_port_base;
+
+/*
+ * Gcc will generate code to load the value of mips_io_port_base after each
+ * function call which may be fairly wasteful in some cases. So we don't
+ * play quite by the book. We tell gcc mips_io_port_base is a long variable
+ * which solves the code generation issue. Now we need to violate the
+ * aliasing rules a little to make initialization possible and finally we
+ * will need the barrier() to fight side effects of the aliasing chat.
+ * This trickery will eventually collapse under gcc's optimizer. Oh well.
+ */
+static inline void set_io_port_base(unsigned long base)
+{
+ * (unsigned long *) &mips_io_port_base = base;
+}
/*
* Thanks to James van Artsdalen for a better timing-fix than