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Diffstat (limited to 'include/configs/MPC8540EVAL.h')
-rw-r--r--include/configs/MPC8540EVAL.h176
1 files changed, 88 insertions, 88 deletions
diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h
index ee4f41f..46a141a 100644
--- a/include/configs/MPC8540EVAL.h
+++ b/include/configs/MPC8540EVAL.h
@@ -66,9 +66,9 @@
#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
-#undef CFG_DRAM_TEST /* memory test, takes time */
-#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
-#define CFG_MEMTEST_END 0x00400000
+#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00400000
#if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET)
#error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both."
@@ -78,42 +78,42 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
-#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
-#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
-#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
-#define CFG_SDRAM_SIZE 256 /* DDR is now 256MB */
+#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is now 256MB */
#if defined(CONFIG_RAM_AS_FLASH)
-#define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
#else
-#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
#endif
-#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 0MB */
+#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 0MB */
#if defined(CONFIG_RAM_AS_FLASH)
-#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */
-#define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */
+#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH 16M */
+#define CONFIG_SYS_BR0_PRELIM 0xf8001801 /* port size 32bit */
#else /* Boot from real Flash */
-#define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */
-#define CFG_BR0_PRELIM 0xff801001 /* port size 16bit */
+#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
+#define CONFIG_SYS_BR0_PRELIM 0xff801001 /* port size 16bit */
#endif
-#define CFG_OR0_PRELIM 0xff806f67 /* 8MB Flash */
-#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
-#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
-#undef CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms)*/
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms)*/
-#define CFG_FLASH_CFI 1
+#define CONFIG_SYS_OR0_PRELIM 0xff806f67 /* 8MB Flash */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms)*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms)*/
+#define CONFIG_SYS_FLASH_CFI 1
-#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
#else
-#undef CFG_RAMBOOT
+#undef CONFIG_SYS_RAMBOOT
#endif
/* DDR Setup */
@@ -127,8 +127,8 @@
#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-#define CFG_DDR_SDRAM_BASE 0x00000000
-#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM
#define CONFIG_NUM_DDR_CONTROLLERS 1
@@ -141,57 +141,57 @@
#undef CONFIG_CLOCKS_IN_MHZ
/* local bus definitions */
-#define CFG_BR2_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
-#define CFG_OR2_PRELIM 0xfc006901
-#define CFG_LBC_LCRR 0x00030004 /* local bus freq divider*/
-#define CFG_LBC_LBCR 0x00000000
-#define CFG_LBC_LSRT 0x20000000
-#define CFG_LBC_MRTPR 0x20000000
-#define CFG_LBC_LSDMR_1 0x2861b723
-#define CFG_LBC_LSDMR_2 0x0861b723
-#define CFG_LBC_LSDMR_3 0x0861b723
-#define CFG_LBC_LSDMR_4 0x1861b723
-#define CFG_LBC_LSDMR_5 0x4061b723
+#define CONFIG_SYS_BR2_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
+#define CONFIG_SYS_OR2_PRELIM 0xfc006901
+#define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq divider*/
+#define CONFIG_SYS_LBC_LBCR 0x00000000
+#define CONFIG_SYS_LBC_LSRT 0x20000000
+#define CONFIG_SYS_LBC_MRTPR 0x20000000
+#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
+#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
+#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
+#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
+#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
#if defined(CONFIG_RAM_AS_FLASH)
-#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
+#define CONFIG_SYS_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
#else
-#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
+#define CONFIG_SYS_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
#endif
-#define CFG_OR4_PRELIM 0xffffe1f1
-#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000)
+#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
+#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 1
-#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
-#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE 1
-#define CFG_NS16550_CLK get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_BAUDRATE 115200
-#define CFG_BAUDRATE_TABLE \
+#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
/* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif
/*
@@ -200,16 +200,16 @@
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_SLAVE 0x7F
-#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-#define CFG_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET 0x3000
/* General PCI */
-#define CFG_PCI_MEM_BASE 0x80000000
-#define CFG_PCI_MEM_PHYS 0x80000000
-#define CFG_PCI_MEM_SIZE 0x20000000
-#define CFG_PCI_IO_BASE 0xe2000000
+#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS 0x80000000
+#define CONFIG_SYS_PCI_MEM_SIZE 0x20000000
+#define CONFIG_SYS_PCI_IO_BASE 0xe2000000
#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
@@ -222,8 +222,8 @@
#define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
#endif
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0008
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0008
#elif defined(CONFIG_TSEC_ENET)
#define CONFIG_NET_MULTI 1
#define CONFIG_MII 1 /* MII PHY management */
@@ -254,21 +254,21 @@
#endif
/* Environment */
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
#if defined(CONFIG_RAM_AS_FLASH)
#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000)
#define CONFIG_ENV_SIZE 0x2000
#else
#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
#endif
#define CONFIG_ENV_SIZE 0x2000
#else
-/* #define CFG_NO_FLASH 1 */ /* Flash is not usable now */
+/* #define CONFIG_SYS_NO_FLASH 1 */ /* Flash is not usable now */
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
-#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
@@ -277,7 +277,7 @@
#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*
@@ -301,7 +301,7 @@
#define CONFIG_CMD_PCI
#endif
-#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_LOADS
#endif
@@ -312,25 +312,25 @@
/*
* Miscellaneous configurable options
*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_LOAD_ADDR 0x2000000 /* default load address */
-#define CFG_PROMPT "MPC8540EVAL=> "/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "MPC8540EVAL=> "/* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Internal Definitions