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-rw-r--r--include/configs/AP1000.h2
-rw-r--r--include/configs/BAB7xx.h1
-rw-r--r--include/configs/EB+MCF-EV123.h2
-rw-r--r--include/configs/ELPPC.h1
-rw-r--r--include/configs/IPHASE4539.h2
-rw-r--r--include/configs/M52277EVB.h2
-rw-r--r--include/configs/M5235EVB.h2
-rw-r--r--include/configs/M5271EVB.h2
-rw-r--r--include/configs/M5329EVB.h2
-rw-r--r--include/configs/M5373EVB.h2
-rw-r--r--include/configs/M54455EVB.h2
-rw-r--r--include/configs/M5475EVB.h2
-rw-r--r--include/configs/M5485EVB.h2
-rw-r--r--include/configs/MPC8315ERDB.h2
-rw-r--r--include/configs/MPC8323ERDB.h2
-rw-r--r--include/configs/MPC832XEMDS.h2
-rw-r--r--include/configs/MPC8349EMDS.h3
-rw-r--r--include/configs/MPC8360EMDS.h2
-rw-r--r--include/configs/MPC8360ERDK.h2
-rw-r--r--include/configs/MPC837XEMDS.h2
-rw-r--r--include/configs/MPC8540EVAL.h2
-rw-r--r--include/configs/MPC8610HPCD.h2
-rw-r--r--include/configs/MPC8641HPCN.h2
-rw-r--r--include/configs/MVBLUE.h2
-rw-r--r--include/configs/QS823.h1
-rw-r--r--include/configs/QS850.h1
-rw-r--r--include/configs/QS860T.h1
-rw-r--r--include/configs/Rattler.h2
-rw-r--r--include/configs/TQM834x.h34
-rw-r--r--include/configs/ads5121.h3
-rw-r--r--include/configs/assabet.h2
-rw-r--r--include/configs/at91cap9adk.h212
-rw-r--r--include/configs/atngw100.h10
-rw-r--r--include/configs/atstk1002.h4
-rw-r--r--include/configs/atstk1004.h2
-rw-r--r--include/configs/ep8248.h2
-rw-r--r--include/configs/ep82xxm.h2
-rw-r--r--include/configs/gcplus.h2
-rw-r--r--include/configs/gw8260.h1
-rw-r--r--include/configs/hcu4.h26
-rw-r--r--include/configs/hcu5.h47
-rw-r--r--include/configs/korat.h234
-rw-r--r--include/configs/m501sk.h197
-rw-r--r--include/configs/mgcoge.h2
-rw-r--r--include/configs/mpc7448hpc2.h2
-rw-r--r--include/configs/ms7720se.h1
-rw-r--r--include/configs/ms7722se.h1
-rw-r--r--include/configs/ms7750se.h1
-rw-r--r--include/configs/munices.h2
-rw-r--r--include/configs/netstar.h86
-rw-r--r--include/configs/pcs440ep.h2
-rw-r--r--include/configs/ppmc7xx.h1
-rw-r--r--include/configs/qemu-mips.h2
-rw-r--r--include/configs/sacsng.h1
-rw-r--r--include/configs/sbc8260.h1
-rw-r--r--include/configs/sbc8349.h2
-rw-r--r--include/configs/sbc8641d.h2
-rw-r--r--include/configs/sequoia.h238
-rw-r--r--include/configs/trizepsiv.h2
-rw-r--r--include/configs/xsengine.h18
-rw-r--r--include/configs/yosemite.h2
61 files changed, 747 insertions, 449 deletions
diff --git a/include/configs/AP1000.h b/include/configs/AP1000.h
index d490b33..baa9741 100644
--- a/include/configs/AP1000.h
+++ b/include/configs/AP1000.h
@@ -22,8 +22,6 @@
* (easy to change)
*/
-#undef DEBUG
-
#define CONFIG_405 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
diff --git a/include/configs/BAB7xx.h b/include/configs/BAB7xx.h
index c11e9c9..8ec70aa 100644
--- a/include/configs/BAB7xx.h
+++ b/include/configs/BAB7xx.h
@@ -28,7 +28,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
#define GTREGREAD(x) 0xffffffff /* needed for debug */
/*
diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h
index dae5295..ea49a5d 100644
--- a/include/configs/EB+MCF-EV123.h
+++ b/include/configs/EB+MCF-EV123.h
@@ -27,9 +27,7 @@
#define CONFIG_EB_MCF_EV123
-#undef DEBUG
#undef CFG_HALT_BEFOR_RAM_JUMP
-#undef ET_DEBUG
/*
* High Level Configuration Options (easy to change)
diff --git a/include/configs/ELPPC.h b/include/configs/ELPPC.h
index bb77188..c64537f 100644
--- a/include/configs/ELPPC.h
+++ b/include/configs/ELPPC.h
@@ -28,7 +28,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
#define GTREGREAD(x) 0xffffffff /* needed for debug */
/*
diff --git a/include/configs/IPHASE4539.h b/include/configs/IPHASE4539.h
index 6fee455..bb2c96a 100644
--- a/include/configs/IPHASE4539.h
+++ b/include/configs/IPHASE4539.h
@@ -30,8 +30,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG /* General debug */
-
/*-----------------------------------------------------------------------
* High Level Configuration Options
* (easy to change)
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
index ab574d5..a3d7bc4 100644
--- a/include/configs/M52277EVB.h
+++ b/include/configs/M52277EVB.h
@@ -38,8 +38,6 @@
#define CONFIG_M52277 /* define processor type */
#define CONFIG_M52277EVB /* M52277EVB board */
-#undef DEBUG
-
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index 7f544c8..3b4bff3 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -37,8 +37,6 @@
#define CONFIG_MCF523x /* define processor family */
#define CONFIG_M5235 /* define processor type */
-#undef DEBUG
-
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h
index 798ec0c..47e1e03 100644
--- a/include/configs/M5271EVB.h
+++ b/include/configs/M5271EVB.h
@@ -31,8 +31,6 @@
#ifndef _M5271EVB_H
#define _M5271EVB_H
-#undef DEBUG
-
/*
* High Level Configuration Options (easy to change)
*/
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index e956739..1a15c77 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -37,8 +37,6 @@
#define CONFIG_MCF532x /* define processor family */
#define CONFIG_M5329 /* define processor type */
-#undef DEBUG
-
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index 6bfffa1..da4156c 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -37,8 +37,6 @@
#define CONFIG_MCF532x /* define processor family */
#define CONFIG_M5373 /* define processor type */
-#undef DEBUG
-
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 581c794..5f55761 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -38,8 +38,6 @@
#define CONFIG_M54455 /* define processor type */
#define CONFIG_M54455EVB /* M54455EVB board */
-#undef DEBUG
-
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h
index 84c2105..f0d42be 100644
--- a/include/configs/M5475EVB.h
+++ b/include/configs/M5475EVB.h
@@ -38,8 +38,6 @@
#define CONFIG_M547x /* define processor type */
#define CONFIG_M5475 /* define processor type */
-#undef DEBUG
-
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
index e9e5ee9..88dd219 100644
--- a/include/configs/M5485EVB.h
+++ b/include/configs/M5485EVB.h
@@ -38,8 +38,6 @@
#define CONFIG_M548x /* define processor type */
#define CONFIG_M5485 /* define processor type */
-#undef DEBUG
-
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index ad2305c..ff7101f 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -25,8 +25,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
-
/*
* High Level Configuration Options
*/
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 295e785..bf5ef4b 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -9,8 +9,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
-
/*
* High Level Configuration Options
*/
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 6c0e68a..702b073 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -20,8 +20,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
-
/*
* High Level Configuration Options
*/
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 07f2f30..331f4c9 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -29,8 +29,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
-
/*
* High Level Configuration Options
*/
@@ -356,6 +354,7 @@
#define CFG_I2C2_OFFSET 0x3100
/* SPI */
+#define CONFIG_MPC8XXX_SPI
#define CONFIG_HARD_SPI /* SPI with hardware support */
#undef CONFIG_SOFT_SPI /* SPI bit-banged */
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index 168ca2a..eff9fba 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -22,8 +22,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
-
/*
* High Level Configuration Options
*/
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index 83a4b1e..27b037a 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -17,8 +17,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
-
/*
* High Level Configuration Options
*/
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 2b84e9c..61de084 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -21,8 +21,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
-
/*
* High Level Configuration Options
*/
diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h
index bf64f27..174215c 100644
--- a/include/configs/MPC8540EVAL.h
+++ b/include/configs/MPC8540EVAL.h
@@ -240,8 +240,6 @@
#define INTEL_LXT971_PHY 1
#endif
-#undef DEBUG
-
/* Environment */
#ifndef CFG_RAMBOOT
#if defined(CONFIG_RAM_AS_FLASH)
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index a53953c..3920147 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -42,6 +42,7 @@
#define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */
#define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
@@ -314,6 +315,7 @@
#define CONFIG_NET_MULTI
#define CONFIG_CMD_NET
#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_CMD_REGINFO
#define CONFIG_ULI526X
#ifdef CONFIG_ULI526X
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 985182f..a8d0077 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -49,6 +49,7 @@
#define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */
#define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_FSL_LAW 1 /* Use common FSL law init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
@@ -536,6 +537,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
+#define CONFIG_CMD_REGINFO
#if defined(CFG_RAMBOOT)
#undef CONFIG_CMD_ENV
diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h
index 0defafe..d799f54 100644
--- a/include/configs/MVBLUE.h
+++ b/include/configs/MVBLUE.h
@@ -53,8 +53,6 @@
#define ERR_LED(code)
#endif
-#undef DEBUG
-
#define CONFIG_MPC824X 1
#define CONFIG_MPC8245 1
#define CONFIG_MVBLUE 1
diff --git a/include/configs/QS823.h b/include/configs/QS823.h
index 3657fea..3dd84e8 100644
--- a/include/configs/QS823.h
+++ b/include/configs/QS823.h
@@ -38,7 +38,6 @@
#undef CFG_DEVICE_NULLDEV /* null device */
#undef CONFIG_SILENT_CONSOLE /* silent console */
#undef CFG_CONSOLE_INFO_QUIET /* silent console ? */
-#undef DEBUG /* debug output code */
#undef DEBUG_FLASH /* debug flash code */
#undef FLASH_DEBUG /* debug fash code */
#undef DEBUG_ENV /* debug environment code */
diff --git a/include/configs/QS850.h b/include/configs/QS850.h
index 3db539f..7dd6eca 100644
--- a/include/configs/QS850.h
+++ b/include/configs/QS850.h
@@ -38,7 +38,6 @@
#undef CFG_DEVICE_NULLDEV /* null device */
#undef CONFIG_SILENT_CONSOLE /* silent console */
#undef CFG_CONSOLE_INFO_QUIET /* silent console ? */
-#undef DEBUG /* debug output code */
#undef DEBUG_FLASH /* debug flash code */
#undef FLASH_DEBUG /* debug fash code */
#undef DEBUG_ENV /* debug environment code */
diff --git a/include/configs/QS860T.h b/include/configs/QS860T.h
index b3442de..62cf2a4 100644
--- a/include/configs/QS860T.h
+++ b/include/configs/QS860T.h
@@ -38,7 +38,6 @@
#undef CFG_DEVICE_NULLDEV /* null device */
#undef CONFIG_SILENT_CONSOLE /* silent console */
#undef CFG_CONSOLE_INFO_QUIET /* silent console ? */
-#undef DEBUG /* debug output code */
#undef DEBUG_FLASH /* debug flash code */
#undef FLASH_DEBUG /* debug fash code */
#undef DEBUG_ENV /* debug environment code */
diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h
index d7652fa..428c0c2 100644
--- a/include/configs/Rattler.h
+++ b/include/configs/Rattler.h
@@ -37,8 +37,6 @@
#define CONFIG_RATTLER /* Analogue&Micro Rattler board */
-#undef DEBUG
-
/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 8ef3f09..024ecfa 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -181,7 +181,7 @@ extern int tqm834x_num_flash_banks;
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc */
/*
* Serial Port
@@ -302,7 +302,7 @@ extern int tqm834x_num_flash_banks;
#ifndef CFG_RAMBOOT
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
- #define CFG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */
+ #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_NO_FLASH 1 /* Flash is not usable now */
@@ -335,6 +335,7 @@ extern int tqm834x_num_flash_banks;
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
@@ -491,24 +492,7 @@ extern int tqm834x_num_flash_banks;
* Environment Configuration
*/
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_ETHADDR D2:DA:5E:44:BC:29
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 1E:F3:40:21:92:53
-#endif
-
-#define CONFIG_IPADDR 192.168.205.1
-
-#define CONFIG_HOSTNAME tqm8349
-#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx
-#define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage
-
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-
-#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
+#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
@@ -523,7 +507,7 @@ extern int tqm834x_num_flash_banks;
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "hostname=tqm83xx\0" \
+ "hostname=tqm834x\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
@@ -535,13 +519,13 @@ extern int tqm834x_num_flash_banks;
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "net_nfs=tftp 400000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
- "bootfile=/tftpboot/tqm83xx/uImage\0" \
+ "bootfile=/tftpboot/tqm834x/uImage\0" \
"kernel_addr=80060000\0" \
"ramdisk_addr=80160000\0" \
- "load=tftp 100000 /tftpboot/tqm83xx/u-boot.bin\0" \
+ "load=tftp 100000 /tftpboot/tqm834x/u-boot.bin\0" \
"update=protect off 80000000 8003ffff; " \
"era 80000000 8003ffff; cp.b 100000 80000000 40000\0" \
"upd=run load;run update\0" \
@@ -557,7 +541,7 @@ extern int tqm834x_num_flash_banks;
#define MTDIDS_DEFAULT "nor0=TQM834x-0"
/* default mtd partition table */
-#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),128k(env),"\
+#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env),"\
"1m(kernel),2m(initrd),"\
"-(user);"\
diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h
index 8d90ea1..09c3140 100644
--- a/include/configs/ads5121.h
+++ b/include/configs/ads5121.h
@@ -27,9 +27,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define DEBUG
-#undef DEBUG
-
/*
* Memory map for the ADS5121 board:
*
diff --git a/include/configs/assabet.h b/include/configs/assabet.h
index 226ad54..d10f092 100644
--- a/include/configs/assabet.h
+++ b/include/configs/assabet.h
@@ -29,8 +29,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
-
/*
* High Level Configuration Options
* (easy to change)
diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h
new file mode 100644
index 0000000..f0dfd71
--- /dev/null
+++ b/include/configs/at91cap9adk.h
@@ -0,0 +1,212 @@
+/*
+ * (C) Copyright 2007
+ * Stelian Pop <stelian.pop <at> leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the AT91CAP9ADK board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define AT91C_MAIN_CLOCK 200000000 /* from 12 MHz crystal */
+#define AT91C_MASTER_CLOCK 100000000 /* peripheral = main / 2 */
+#define CFG_HZ 1000000 /* 1us resolution */
+
+#define AT91_SLOW_CLOCK 32768 /* slow clock */
+
+#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
+#define CONFIG_AT91CAP9 1 /* It's an Atmel AT91CAP9 SoC */
+#define CONFIG_AT91CAP9ADK 1 /* on an AT91CAP9ADK Board */
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN ROUND(CFG_ENV_SIZE + 128*1024, 0x1000)
+#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
+
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_ATMEL_USART 1
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+#undef CONFIG_USART2
+#define CONFIG_USART3 1 /* USART 3 is DBGU */
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mtdblock1 rw rootfstype=jffs2"
+
+/* #define CONFIG_ENV_OVERWRITE 1 */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE 1
+#define CONFIG_BOOTP_BOOTPATH 1
+#define CONFIG_BOOTP_GATEWAY 1
+#define CONFIG_BOOTP_HOSTNAME 1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADS
+
+#define CONFIG_CMD_PING 1
+#define CONFIG_CMD_DHCP 1
+#define CONFIG_CMD_NAND 1
+#define CONFIG_CMD_USB 1
+
+/* SDRAM: Careful: this supposes an AT91CAP-MEM33 expansion card */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x70000000
+#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
+
+/* DataFlash */
+#define CONFIG_HAS_DATAFLASH 1
+#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
+#define CFG_MAX_DATAFLASH_BANKS 1
+#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
+#define CONFIG_NEW_PARTITION 1
+
+/* NOR flash */
+#define CFG_FLASH_CFI 1
+#define CFG_FLASH_CFI_DRIVER 1
+#define PHYS_FLASH_1 0x10000000
+#define CFG_FLASH_BASE PHYS_FLASH_1
+#define CFG_MAX_FLASH_SECT 256
+#define CFG_MAX_FLASH_BANKS 1
+
+#define AT91C_FLASH_NWE_SETUP (4 << 0)
+#define AT91C_FLASH_NCS_WR_SETUP (2 << 8)
+#define AT91C_FLASH_NRD_SETUP (4 << 16)
+#define AT91C_FLASH_NCS_RD_SETUP (2 << 24)
+
+#define AT91C_FLASH_NWE_PULSE (8 << 0)
+#define AT91C_FLASH_NCS_WR_PULSE (10 << 8)
+#define AT91C_FLASH_NRD_PULSE (8 << 16)
+#define AT91C_FLASH_NCS_RD_PULSE (10 << 24)
+
+#define AT91C_FLASH_NWE_CYCLE (16 << 0)
+#define AT91C_FLASH_NRD_CYCLE (16 << 16)
+
+/* NAND flash */
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1
+#define CFG_NAND_BASE 0x40000000
+
+#define AT91C_SM_NWE_SETUP (2 << 0)
+#define AT91C_SM_NCS_WR_SETUP (1 << 8)
+#define AT91C_SM_NRD_SETUP (2 << 16)
+#define AT91C_SM_NCS_RD_SETUP (1 << 24)
+
+#define AT91C_SM_NWE_PULSE (4 << 0)
+#define AT91C_SM_NCS_WR_PULSE (6 << 8)
+#define AT91C_SM_NRD_PULSE (4 << 16)
+#define AT91C_SM_NCS_RD_PULSE (6 << 24)
+
+#define AT91C_SM_NWE_CYCLE (8 << 0)
+#define AT91C_SM_NRD_CYCLE (8 << 16)
+
+#define AT91C_SM_TDF (1 << 16)
+
+/* Ethernet */
+#define CONFIG_MACB 1
+#define CONFIG_RMII 1
+#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_RESET_PHY_R 1
+
+/* USB */
+#define CONFIG_USB_OHCI_NEW 1
+#define LITTLEENDIAN 1
+#define CONFIG_DOS_PARTITION 1
+#define CFG_USB_OHCI_CPU_INIT 1
+#define CFG_USB_OHCI_REGS_BASE 0x00700000 /* AT91C_BASE_UHP */
+#define CFG_USB_OHCI_SLOT_NAME "at91cap9"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 2
+
+
+#define CFG_LOAD_ADDR 0x72000000 /* load address */
+
+#define CFG_MEMTEST_START PHYS_SDRAM
+#define CFG_MEMTEST_END 0x73000000
+
+#define CFG_USE_DATAFLASH 1
+#undef CFG_USE_NORFLASH
+
+#ifdef CFG_USE_DATAFLASH
+
+/* bootstrap + u-boot + env + linux in dataflash */
+#define CFG_ENV_IS_IN_DATAFLASH 1
+#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
+#define CFG_ENV_OFFSET 0x4200
+#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
+#define CFG_ENV_SIZE 0x4200
+#define CONFIG_BOOTCOMMAND "cp.b 0xC003DE00 0x72000000 0x200040; bootm"
+
+#else
+
+/* bootstrap + u-boot + env + linux in norflash */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_MONITOR_BASE (PHYS_FLASH_1 + 0x8000)
+#define CFG_ENV_OFFSET 0x4000
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_ENV_OFFSET)
+#define CFG_ENV_SIZE 0x4000
+#define CONFIG_BOOTCOMMAND "cp.b 0x10040000 0x72000000 0x200000; bootm"
+
+#endif
+
+#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
+
+#define CFG_PROMPT "U-Boot> "
+#define CFG_CBSIZE 256
+#define CFG_MAXARGS 16
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+
+#define CONFIG_STACKSIZE (32*1024) /* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
index 414e130..5aad043 100644
--- a/include/configs/atngw100.h
+++ b/include/configs/atngw100.h
@@ -170,13 +170,9 @@
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
#define CFG_LONGHELP 1
-#define CFG_MEMTEST_START \
- ({ DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start; })
-#define CFG_MEMTEST_END \
- ({ \
- DECLARE_GLOBAL_DATA_PTR; \
- gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; \
- })
+#define CFG_MEMTEST_START CFG_SDRAM_BASE
+#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x1f00000)
+
#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
#endif /* __CONFIG_H */
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
index b33e26f..95aeab6 100644
--- a/include/configs/atstk1002.h
+++ b/include/configs/atstk1002.h
@@ -184,8 +184,8 @@
#define CFG_MALLOC_LEN (256*1024)
#define CFG_DMA_ALLOC_LEN (16384)
-/* Allow 2MB for the kernel run-time image */
-#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000)
+/* Allow 4MB for the kernel run-time image */
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000)
#define CFG_BOOTPARAMS_LEN (16 * 1024)
/* Other configuration settings that shouldn't have to change all that often */
diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h
index 1bad171..b81fc21 100644
--- a/include/configs/atstk1004.h
+++ b/include/configs/atstk1004.h
@@ -167,7 +167,7 @@
#define CFG_MALLOC_LEN (256*1024)
-/* Allow 4MB for the kernel run-time image */
+/* Allow 2MB for the kernel run-time image */
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000)
#define CFG_BOOTPARAMS_LEN (16 * 1024)
diff --git a/include/configs/ep8248.h b/include/configs/ep8248.h
index 85ad70a..cebe849 100644
--- a/include/configs/ep8248.h
+++ b/include/configs/ep8248.h
@@ -31,8 +31,6 @@
#define CONFIG_EP8248 /* Embedded Planet EP8248 board */
-#undef DEBUG
-
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h
index 4febd32..8e5d6e5 100644
--- a/include/configs/ep82xxm.h
+++ b/include/configs/ep82xxm.h
@@ -31,8 +31,6 @@
#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board */
/* 256MB SDRAM / 64MB FLASH */
-#undef DEBUG
-
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
diff --git a/include/configs/gcplus.h b/include/configs/gcplus.h
index e11ce4c..3b1b4ab 100644
--- a/include/configs/gcplus.h
+++ b/include/configs/gcplus.h
@@ -29,8 +29,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
-
/*
* The ADS GCPlus Linux boot ROM loads U-Boot into RAM at 0xc0200000.
* We don't actually init RAM in this case since we're using U-Boot as
diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h
index ff57240..7c2c224 100644
--- a/include/configs/gw8260.h
+++ b/include/configs/gw8260.h
@@ -51,7 +51,6 @@
#define __CONFIG_H
/* Enable debug prints */
-#undef DEBUG /* General debug */
#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
/* What is the oscillator's (UX2) frequency in Hz? */
diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h
index cb51406..9242d2c 100644
--- a/include/configs/hcu4.h
+++ b/include/configs/hcu4.h
@@ -33,7 +33,6 @@
*----------------------------------------------------------------------*/
#define CONFIG_HCU4 1 /* Board is HCU4 */
#define CONFIG_4xx 1 /* ... PPC4xx family */
-#define CONFIG_405GPr 1 /* HCU4 has a 405GPr */
#define CONFIG_405GP 1
#define CONFIG_4xx 1
@@ -176,7 +175,7 @@
#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=0x01000000\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
@@ -190,14 +189,14 @@
"bootm\0" \
"rootpath=/home/diagnose/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/hcu4/uImage\0" \
- "load=tftp 100000 hcu4/u-boot.bin\0" \
- "update=protect off FFFB0000 FFFFFFFF;era FFFC0000 FFFFFFFF;" \
+ "load=tftp 100000 hcu4/u-boot.bin\0" \
+ "update=protect off FFFB0000 FFFFFFFF;era FFFB0000 FFFFFFFF;" \
"cp.b 100000 FFFB0000 50000\0" \
"upd=run load;run update\0" \
- "vx=tftp ${loadaddr} hcu4_vx_rom;" \
- "vx=tftp ${loadaddr} hcu4/hcu4_vx_rom;" \
- "setenv bootargs emac(0,0)c:hcu4/hcu4_vx_rom e=${ipaddr} " \
- "bootvx ${loadaddr}\0" \
+ "vx_rom=hcu4/hcu4_vx_rom\0" \
+ "vx=tftp ${loadaddr} ${vx_rom};run vxargs; bootvx\0" \
+ "vxargs=setenv bootargs emac(0,0)c:${vx_rom} e=${ipaddr}" \
+ " h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008\0" \
""
#define CONFIG_BOOTCOMMAND "run vx"
@@ -207,7 +206,7 @@
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 1 /* PHY address */
+#define CONFIG_PHY_ADDR 1 /* PHY address */
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
@@ -334,15 +333,6 @@
/* Configuration Port location */
#define CONFIG_PORT_ADDR 0xF0000500
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CFG_HUSH_PARSER /* use "hush" command parser */
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h
index d66c47a..8c26613 100644
--- a/include/configs/hcu5.h
+++ b/include/configs/hcu5.h
@@ -123,7 +123,7 @@
/* Put the environment in Flash */
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */
+#define CFG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
@@ -148,9 +148,9 @@
* I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
* the second internal I2C controller of the PPC440EPx
*----------------------------------------------------------------------*/
-#define CFG_SPD_BUS_NUM 1
+#define CFG_SPD_BUS_NUM 1
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
@@ -182,7 +182,7 @@
#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=0x01000000\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
@@ -197,14 +197,13 @@
"bootfile=hcu5/uImage\0" \
"rootpath=/home/hcu/eldk/ppc_4xxFP\0" \
"load=tftp 100000 hcu5/u-boot.bin\0" \
- "update=protect off FFFb0000 FFFFFFFF;era FFFb0000 FFFFFFFF;" \
- "cp.b 100000 FFFb0000 50000\0" \
+ "update=protect off FFFB0000 FFFFFFFF;era FFFB0000 FFFFFFFF;" \
+ "cp.b 100000 FFFB0000 50000\0" \
"upd=run load;run update\0" \
- "vx=tftp ${loadaddr} hcu5/hcu5_vx_rom; run vxboot\0" \
- "vxusb=usb start; fatload usb 0 ${loadaddr} vxWorks.st; run vxboot\0" \
- "vxargs=emac(0,0)c:hcu5/hcu5_vx_rom e=${ipaddr} h=${serverip}" \
- " u=dpu pw=netstal8752 tn=hcu5 f=0x3008\0" \
- "vxboot=setenv bootargs $(vxargs); bootvx ${loadaddr}\0" \
+ "vx_rom=hcu5/hcu5_vx_rom\0" \
+ "vx=tftp ${loadaddr} ${vx_rom};run vxargs; bootvx\0" \
+ "vxargs=setenv bootargs emac(0,0)c:${vx_rom} e=${ipaddr}" \
+ " h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008\0" \
"usbargs=setenv bootargs root=/dev/sda1 ro\0" \
"linux=usb start; ext2load usb 0 ${loadaddr} /boot/uImage;" \
"run usbargs addip addtty; bootm\0" \
@@ -225,16 +224,16 @@
#define CONFIG_M88E1111_PHY 1
#define CONFIG_IBM_EMAC4_V4 1
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
+#define CONFIG_PHY_ADDR 1 /* PHY address, like on HCU4 */
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_HAS_ETH0
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & desc. */
#define CONFIG_NET_MULTI 1
-#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
-#define CONFIG_PHY1_ADDR 1
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_PHY1_ADDR 2
/* USB */
#define CONFIG_USB_OHCI
@@ -311,7 +310,7 @@
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
@@ -350,11 +349,11 @@
* Flash
*----------------------------------------------------------------------*/
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
@@ -393,14 +392,6 @@
#define HCU_CPLD_VERSION_REGISTER ( CFG_CPLD + 0x0F00000 )
#define HCU_HW_VERSION_REGISTER ( CFG_CPLD + 0x1400000 )
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CFG_HUSH_PARSER /* use "hush" command parser */
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
diff --git a/include/configs/korat.h b/include/configs/korat.h
index 5182972..7f2b09a 100644
--- a/include/configs/korat.h
+++ b/include/configs/korat.h
@@ -25,73 +25,73 @@
* MA 02111-1307 USA
*/
-/************************************************************************
+/*
* korat.h - configuration for Korat board
- ***********************************************************************/
+ */
#ifndef __CONFIG_H
#define __CONFIG_H
-/*-----------------------------------------------------------------------
+/*
* High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_440EPX 1 /* Specific PPC440EPx */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
+ */
+#define CONFIG_440EPX 1 /* Specific PPC440EPx */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-/*-----------------------------------------------------------------------
+/*
* Manufacturer's information serial EEPROM parameters
- *----------------------------------------------------------------------*/
-#define MAN_DATA_EEPROM_ADDR 0x53 /* EEPROM I2C address */
+ */
+#define MAN_DATA_EEPROM_ADDR 0x53 /* EEPROM I2C address */
#define MAN_SERIAL_NO_FIELD 2
#define MAN_SERIAL_NO_LENGTH 13
#define MAN_MAC_ADDR_FIELD 3
#define MAN_MAC_ADDR_LENGTH 17
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
-#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
+/*
+ * Base addresses -- Note these are effective addresses where the actual
+ * resources get mapped (not physical addresses).
+ */
+#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kiB for Monitor */
+#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kiB for malloc() */
#define CFG_BOOT_BASE_ADDR 0xf0000000
-#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
#define CFG_MONITOR_BASE TEXT_BASE
-#define CFG_OCM_BASE 0xe0010000 /* ocm */
+#define CFG_OCM_BASE 0xe0010000 /* ocm */
#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
-#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
-#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
/* Don't change either of these */
-#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
+#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
#define CFG_USB2D0_BASE 0xe0000100
#define CFG_USB_DEVICE 0xe0000000
#define CFG_USB_HOST 0xe0000400
#define CFG_CPLD_BASE 0xc0000000
-/*-----------------------------------------------------------------------
+/*
* Initial RAM & stack pointer
- *----------------------------------------------------------------------*/
+ */
/* 440EPx has 16KB of internal SRAM, so no need for D-Cache */
#undef CFG_INIT_RAM_DCACHE
-#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
+#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
#define CFG_INIT_RAM_END (4 << 10)
-#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
-/*-----------------------------------------------------------------------
+/*
* Serial Port
- *----------------------------------------------------------------------*/
-#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
+ */
+#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SERIAL_MULTI 1
/* define this if you want console on UART1 */
@@ -100,57 +100,57 @@
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-/*-----------------------------------------------------------------------
+/*
* Environment
- *----------------------------------------------------------------------*/
-#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */
+ */
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */
-/*-----------------------------------------------------------------------
+/*
* FLASH related
- *----------------------------------------------------------------------*/
-#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+ */
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
-#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
-#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
-/*-----------------------------------------------------------------------
+/*
* DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CFG_MBYTES_SDRAM (512) /* 512 MiB TODO: remove */
-#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
-#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
-#define CONFIG_DDR_ECC /* Use ECC when available */
+ */
+#define CFG_MBYTES_SDRAM (512) /* 512 MiB TODO: remove */
+#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
+#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
+#define CONFIG_DDR_ECC /* Use ECC when available */
#define SPD_EEPROM_ADDRESS {0x50}
#define CONFIG_PROG_SDRAM_TLB
#define CFG_DRAM_TEST
-/*-----------------------------------------------------------------------
+/*
* I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_MULTI_EEPROMS
@@ -164,8 +164,8 @@
#define CFG_I2C_RTC_ADDR 0x68
/* I2C SYSMON (LM73) */
-#define CONFIG_DTT_LM73 1 /* National Semi's LM73 */
-#define CONFIG_DTT_SENSORS {2} /* Sensor addresses */
+#define CONFIG_DTT_LM73 1 /* National Semi's LM73 */
+#define CONFIG_DTT_SENSORS {2} /* Sensor addresses */
#define CFG_DTT_MAX_TEMP 70
#define CFG_DTT_MIN_TEMP -30
@@ -206,24 +206,24 @@
""
#define CONFIG_BOOTCOMMAND "run flash_self"
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_IBM_EMAC4_V4 1
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */
#define CONFIG_PHY_DYNAMIC_ANEG 1
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CONFIG_HAS_ETH0
-#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx */
+ /* buffers & descriptors */
#define CONFIG_NET_MULTI 1
-#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY1_ADDR 3
/* USB */
@@ -273,80 +273,81 @@
#define CONFIG_CMD_USB
/* POST support */
-#define CONFIG_POST (CFG_POST_CACHE | \
+#define CONFIG_POST (CFG_POST_CACHE | \
CFG_POST_CPU | \
- CFG_POST_ECC | \
+ CFG_POST_ECC | \
CFG_POST_ETHER | \
CFG_POST_FPU | \
CFG_POST_I2C | \
CFG_POST_MEMORY | \
- CFG_POST_RTC | \
- CFG_POST_SPR | \
+ CFG_POST_RTC | \
+ CFG_POST_SPR | \
CFG_POST_UART)
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
#define CONFIG_LOGBUFFER
-#define CFG_POST_CACHE_ADDR 0xC8000000 /* free virtual address */
+#define CFG_POST_CACHE_ADDR 0xC8000000 /* free virtual address */
#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
#define CONFIG_SUPPORT_VFAT
-/*-----------------------------------------------------------------------
+/*
* Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+ /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-/*-----------------------------------------------------------------------
+/*
* PCI stuff
- *----------------------------------------------------------------------*/
+ */
/* General PCI */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
-
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
+ /* CFG_PCI_MEMBASE */
/* Board-specific PCI */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
-#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
-#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
+#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
+ * For booting Linux, the board info and command line data have to be in the
+ * first 8 MB of memory, since this is the maximum mapped by the Linux kernel
+ * during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
+/*
* External Bus Controller (EBC) Setup
- *----------------------------------------------------------------------*/
+ */
/* Memory Bank 0 (NOR-FLASH) initialization */
#define CFG_EBC_PB0AP 0x04017300
@@ -360,7 +361,7 @@
#define CFG_EBC_PB2AP 0x04017300
#define CFG_EBC_PB2CR (CFG_CPLD_BASE | 0x00038000)
-/*-----------------------------------------------------------------------
+/*
* GPIO Setup
*
* Korat GPIO usage:
@@ -423,7 +424,7 @@
* . . . . .
* . . . . .
* GPIO63 xxxx x x (reserved for trace port)
-*----------------------------------------------------------------------*/
+ */
#define CFG_GPIO_ATMEGA_SS_ 13
#define CFG_GPIO_PHY0_FIBER_SEL 27
@@ -435,7 +436,7 @@
#define CFG_GPIO_PHY0_EN 45
#define CFG_GPIO_PHY1_EN 46
-/*-----------------------------------------------------------------------
+/*
* PPC440 GPIO Configuration
*/
#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
@@ -516,11 +517,12 @@
*
* Boot Flags
*/
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
+
#endif /* __CONFIG_H */
diff --git a/include/configs/m501sk.h b/include/configs/m501sk.h
new file mode 100644
index 0000000..095fdaf
--- /dev/null
+++ b/include/configs/m501sk.h
@@ -0,0 +1,197 @@
+/*
+ * Based on Modifications by Alan Lu / Artila and
+ * Rick Bronson <rick@efn.org>
+ *
+ * Configuration settings for the Artila M-501 starter kit,
+ * with V02 processor card.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+/* from 18.432 MHz crystal (18432000 / 4 * 39) */
+#define AT91C_MAIN_CLOCK 179712000
+/* Perip clock (AT91C_MASTER_CLOCK / 3) */
+#define AT91C_MASTER_CLOCK 59904000
+#define AT91_SLOW_CLOCK 32768 /* slow clock */
+
+#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#undef CONFIG_AUTOBOOT_PROMPT
+#define CONFIG_MENUPROMPT "."
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE 128 /* Bytes reserved for initial data */
+
+#define CONFIG_BAUDRATE 115200
+
+/* Hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
+#define CFG_AT91C_BRGR_DIVISOR 33
+
+/*
+ * Hardware drivers
+ */
+#define CFG_FLASH_CFI 1
+#define CFG_FLASH_CFI_DRIVER 1
+#define CFG_ENV_SECT_SIZE 0x20000
+#define CFG_FLASH_USE_BUFFER_WRITE
+#define CFG_FLASH_PROTECTION /*for Intel P30 Flash*/
+#define CONFIG_HARD_I2C
+#define CFG_I2C_SPEED 100
+#define CFG_I2C_SLAVE 0
+#define CFG_CONSOLE_INFO_QUIET
+#undef CFG_ENV_IS_IN_EEPROM
+#define CFG_I2C_EEPROM_ADDR 0x50
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_AT24C16
+#define CFG_I2C_RTC_ADDR 0x32
+#undef CONFIG_RTC_DS1338
+#define CONFIG_RTC_RS5C372A
+#undef CONFIG_POST
+#define CONFIG_M501SK
+#define CONFIG_CMC_PU2
+
+/* define one of these to choose the DBGU, USART0 or USART1 as console */
+#define CONFIG_DBGU
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+
+#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
+#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
+
+#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200 " \
+ "initrd=0x20800000,8192000 ramdisk_size=15360 " \
+ "root=/dev/ram0 rw mtdparts=phys_mapped_flash:" \
+ "128k(loader)ro,128k(reserved)ro,1408k(linux)" \
+ "ro,2560k(ramdisk)ro,-(userdisk)"
+#define CONFIG_BOOTCOMMAND "bootm 10040000 101a0000"
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_IPADDR 192.168.1.100
+#define CONFIG_SERVERIP 192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.254
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_BOOTFILE uImage
+#define CONFIG_ETHADDR 00:13:48:aa:bb:cc
+#define CONFIG_ENV_OVERWRITE 1
+#define BOARD_LATE_INIT
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "unlock=yes\0"
+
+#define CFG_CMD_JFFS2
+#undef CONFIG_CMD_EEPROM
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_POST
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_ENV
+
+#define CFG_HUSH_PARSER
+#define CONFIG_AUTO_COMPLETE
+#define CFG_PROMPT_HUSH_PS2 ">>"
+
+#define CFG_MAX_NAND_DEVICE 0 /* Max number of NAND devices */
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x20000000
+#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */
+
+#define CFG_MEMTEST_START 0x21000000 /* PHYS_SDRAM */
+/* CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 */
+#define CFG_MEMTEST_END 0x00100000
+
+#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_AT91C_USE_RMII
+
+#define PHYS_FLASH_1 0x10000000
+#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
+#define CFG_FLASH_BASE PHYS_FLASH_1
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_MAX_FLASH_SECT 256
+#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
+
+#ifdef CFG_ENV_IS_IN_DATAFLASH
+#define CFG_ENV_OFFSET 0x20000
+#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
+#define CFG_ENV_SIZE 0x2000
+#else
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x00020000)
+#define CFG_ENV_SIZE 2048
+#endif
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_OFFSET 1024
+#define CFG_ENV_SIZE 1024
+#endif
+
+#define CFG_LOAD_ADDR 0x21000000 /* default load address */
+
+/* use for protect flash sectors */
+#define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */
+#define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000)
+#define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */
+
+#define CFG_BAUDRATE_TABLE { 115200 , 19200, 38400, 57600, 9600 }
+
+#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 512 /* Console I/O Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+/* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+
+#define CFG_HZ 1000
+#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2
+
+#define CONFIG_STACKSIZE (32*1024) /* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h
index 3de2466..f4a1cc0 100644
--- a/include/configs/mgcoge.h
+++ b/include/configs/mgcoge.h
@@ -35,8 +35,6 @@
#define CONFIG_CPM2 1 /* Has a CPM2 */
-#undef DEBUG
-
/*
* Select serial console configuration
*
diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h
index bd3107a..c7216c9 100644
--- a/include/configs/mpc7448hpc2.h
+++ b/include/configs/mpc7448hpc2.h
@@ -33,8 +33,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
-
/* Board Configuration Definitions */
/* MPC7448HPC2 (High-Performance Computing II) (Taiga) board */
diff --git a/include/configs/ms7720se.h b/include/configs/ms7720se.h
index 7035002..9c94c4e 100644
--- a/include/configs/ms7720se.h
+++ b/include/configs/ms7720se.h
@@ -25,7 +25,6 @@
#ifndef __MS7720SE_H
#define __MS7720SE_H
-#undef DEBUG
#define CONFIG_SH 1
#define CONFIG_SH3 1
#define CONFIG_CPU_SH7720 1
diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h
index ae0d018..8538037 100644
--- a/include/configs/ms7722se.h
+++ b/include/configs/ms7722se.h
@@ -25,7 +25,6 @@
#ifndef __MS7722SE_H
#define __MS7722SE_H
-#undef DEBUG
#define CONFIG_SH 1
#define CONFIG_SH4 1
#define CONFIG_CPU_SH7722 1
diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h
index 3668156..a25364d 100644
--- a/include/configs/ms7750se.h
+++ b/include/configs/ms7750se.h
@@ -25,7 +25,6 @@
#ifndef __MS7750SE_H
#define __MS7750SE_H
-#undef DEBUG
#define CONFIG_SH 1
#define CONFIG_SH4 1
#define CONFIG_CPU_SH7750 1
diff --git a/include/configs/munices.h b/include/configs/munices.h
index 2372b57..38b27bb 100644
--- a/include/configs/munices.h
+++ b/include/configs/munices.h
@@ -48,7 +48,7 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
diff --git a/include/configs/netstar.h b/include/configs/netstar.h
index 33159d3..a48893d 100644
--- a/include/configs/netstar.h
+++ b/include/configs/netstar.h
@@ -48,14 +48,15 @@
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
-#define CFG_DEVICE_NULLDEV 1 /* enable null device */
#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
+#define CFG_CONSOLE_INFO_QUIET
/*
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024)
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
/*
@@ -63,30 +64,21 @@
*/
#define CFG_FLASH_BASE PHYS_FLASH_1
#define CFG_MAX_FLASH_BANKS 1
-#if (PHYS_SDRAM_1_SIZE == SZ_32M)
-/*#if 1*/
-#define CFG_FLASH_CFI /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER /* Use the common driver */
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_MAX_FLASH_SECT 128
-#else
-#define PHYS_FLASH_1_SIZE SZ_1M
+#define PHYS_FLASH_1_SIZE (1 * 1024 * 1024)
#define CFG_MAX_FLASH_SECT 19
#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* in ticks */
#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ)
-#endif
#define CFG_MONITOR_BASE PHYS_FLASH_1
-#define CFG_MONITOR_LEN SZ_256K
+#define CFG_MONITOR_LEN (256 * 1024)
/*
* Environment settings
*/
#define CFG_ENV_IS_IN_FLASH
-#define ENV_IS_SOLITARY
#define CFG_ENV_ADDR 0x4000
-#define CFG_ENV_SIZE SZ_8K
-#define CFG_ENV_SECT_SIZE SZ_8K
+#define CFG_ENV_SIZE (8 * 1024)
+#define CFG_ENV_SECT_SIZE (8 * 1024)
#define CFG_ENV_ADDR_REDUND 0x6000
#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
#define CONFIG_ENV_OVERWRITE
@@ -95,14 +87,12 @@
* Size of malloc() pool
*/
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-/* XXX #define CFG_MALLOC_LEN (SZ_64K - CFG_GBL_DATA_SIZE)*/
-#define CFG_MALLOC_LEN SZ_4M
+#define CFG_MALLOC_LEN (4 * 1024 * 1024)
/*
* The stack size is set up in start.S using the settings below
*/
-/* XXX #define CONFIG_STACKSIZE SZ_8K /XXX* regular stack */
-#define CONFIG_STACKSIZE SZ_1M /* regular stack */
+#define CONFIG_STACKSIZE (1 * 1024 * 1024) /* regular stack */
/*
* Hardware drivers
@@ -132,13 +122,16 @@
#define CFG_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_BASE 0x04000000 + (2 << 23)
+#define NAND_ALLOW_ERASE_ALL 1
/*
- * JFFS2 partitions (mtdparts command line support)
+ * partitions (mtdparts command line support)
*/
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=omapflash.0,nand0=omapnand.0"
-#define MTDPARTS_DEFAULT "mtdparts=omapflash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);omapnand.0:48M(rootfs0),48M(rootfs1),-(data)"
+#define MTDPARTS_DEFAULT "mtdparts=" \
+ "omapflash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);" \
+ "omapnand.0:4M(kernel0),40M(rootfs0),4M(kernel1),40M(rootfs1),-(data)"
/*
@@ -176,36 +169,34 @@
#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
#define CFG_AUTOLOAD "n" /* No autoload */
-#define CONFIG_BOOTCOMMAND "run nboot"
+#define CONFIG_BOOTCOMMAND "run fboot"
#define CONFIG_PREBOOT "run setup"
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "setup=setenv bootargs console=ttyS0,$baudrate " \
- "$mtdparts\0" \
- "ospart=0\0" \
- "setpart=" \
- "if test -n $swapos; then " \
- "if test $ospart -eq 0; then chpart nand0,1; else chpart nand0,0; fi; "\
- "setenv swapos; saveenv; " \
- "else " \
- "chpart nand0,$ospart; " \
- "fi\0" \
- "nfsargs=setenv bootargs $bootargs " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
- "nfsroot=$rootpath root=/dev/nfs\0" \
- "flashargs=run setpart;setenv bootargs $bootargs " \
- "root=/dev/mtdblock$partition ro " \
- "rootfstype=jffs2\0" \
- "initrdargs=setenv bootargs $bootargs " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
- "iboot=bootp;run initrdargs;tftp;bootm\0" \
- "fboot=run flashargs;fsload /boot/uImage;bootm\0" \
- "nboot=bootp;run nfsargs;tftp;bootm\0"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "autostart=yes\0" \
+ "ospart=0\0" \
+ "setup=setenv bootargs console=ttyS0,$baudrate " \
+ "$mtdparts\0" \
+ "setpart=" \
+ "if test -n $swapos; then " \
+ "setenv swapos; saveenv; " \
+ "else " \
+ "if test $ospart -eq 0; then setenv ospart 1;" \
+ "else setenv ospart 0; fi; " \
+ "fi\0" \
+ "nfsargs=setenv bootargs $bootargs " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
+ "nfsroot=$rootpath root=/dev/nfs\0" \
+ "flashargs=run setpart;setenv bootargs $bootargs " \
+ "root=mtd:rootfs$ospart ro " \
+ "rootfstype=jffs2\0" \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
+ "fboot=run flashargs;nboot kernel$ospart\0" \
+ "nboot=bootp;run nfsargs;tftp\0"
#if 0 /* feel free to disable for development */
#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
-#define CONFIG_AUTOBOOT_PROMPT "\nNetStar PBX - boot in %d sec...\n"
-#define CONFIG_AUTOBOOT_DELAY_STR "R" /* 1st "password" */
-#define CONFIG_BOOT_RETRY_TIME 30
+#define CONFIG_AUTOBOOT_PROMPT "\nNetStar PBX - boot in %d secs...\n"
+#define CONFIG_AUTOBOOT_DELAY_STR "." /* 1st "password" */
#endif
/*
@@ -223,7 +214,8 @@
#define CONFIG_AUTO_COMPLETE
#define CFG_MEMTEST_START PHYS_SDRAM_1
-#define CFG_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE
+#define CFG_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - \
+ (CFG_MONITOR_LEN + CFG_MALLOC_LEN + CONFIG_STACKSIZE)
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h
index d66f4bd..07fc23e 100644
--- a/include/configs/pcs440ep.h
+++ b/include/configs/pcs440ep.h
@@ -66,7 +66,7 @@
*----------------------------------------------------------------------*/
#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
-#define CFG_INIT_RAM_END (8 << 10)
+#define CFG_INIT_RAM_END (4 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h
index fe7de7b..1d2d38b 100644
--- a/include/configs/ppmc7xx.h
+++ b/include/configs/ppmc7xx.h
@@ -30,7 +30,6 @@
* do_bdinfo - Required to build with debug
*/
-#undef DEBUG
#ifdef DEBUG
#define GTREGREAD(x) 0xFFFFFFFF
#define do_bdinfo(a,b,c,d)
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index 33c8283..e164019 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -32,8 +32,6 @@
#define CONFIG_QEMU_MIPS 1
#define CONFIG_MISC_INIT_R
-#undef DEBUG
-
/*IP address is default used by Qemu*/
#define CONFIG_IPADDR 10.0.2.15 /* Our IP address */
#define CONFIG_SERVERIP 10.0.2.2 /* Server IP address*/
diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h
index c474acd..ec7d34a 100644
--- a/include/configs/sacsng.h
+++ b/include/configs/sacsng.h
@@ -35,7 +35,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG /* General debug */
#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
#undef CONFIG_LOGBUFFER /* External logbuffer support */
diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h
index b1d41a6..6063398 100644
--- a/include/configs/sbc8260.h
+++ b/include/configs/sbc8260.h
@@ -36,7 +36,6 @@
#define __CONFIG_H
/* Enable debug prints */
-#undef DEBUG /* General debug */
#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
/*****************************************************************************
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 4cc4ff1..2498b3e 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -31,8 +31,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
-
/*
* High Level Configuration Options
*/
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 54eac38..1991a8c 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -53,6 +53,7 @@
#define CONFIG_PCI1 1 /* PCIE controler 1 (slot 1) */
#define CONFIG_PCI2 1 /* PCIE controler 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
@@ -479,6 +480,7 @@
#include <config_cmd_default.h>
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
+ #define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 056c288..cd0ae6d 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -22,23 +22,23 @@
* MA 02111-1307 USA
*/
-/************************************************************************
+/*
* sequoia.h - configuration for Sequoia & Rainier boards
- ***********************************************************************/
+ */
#ifndef __CONFIG_H
#define __CONFIG_H
-/*-----------------------------------------------------------------------
+/*
* High Level Configuration Options
- *----------------------------------------------------------------------*/
+ */
/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */
#ifndef CONFIG_RAINIER
-#define CONFIG_440EPX 1 /* Specific PPC440EPx */
+#define CONFIG_440EPX 1 /* Specific PPC440EPx */
#else
-#define CONFIG_440GRX 1 /* Specific PPC440GRx */
+#define CONFIG_440GRX 1 /* Specific PPC440GRx */
#endif
-#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_440 1 /* ... PPC440 family */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
/* Detect Sequoia PLL input clock automatically via CPLD bit */
#define CONFIG_SYS_CLK_FREQ ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
33333333 : 33000000)
@@ -48,28 +48,28 @@
* 44x dcache supported is working now on sequoia, but we don't enable
* it yet since it needs further testing
*/
-#define CONFIG_4xx_DCACHE /* enable dcache */
+#define CONFIG_4xx_DCACHE /* enable dcache */
#endif
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-/*-----------------------------------------------------------------------
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
-#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
+/*
+ * Base addresses -- Note these are effective addresses where the actual
+ * resources get mapped (not physical addresses).
+ */
+#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kiB for Monitor */
+#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kiB for malloc() */
#define CFG_TLB_FOR_BOOT_FLASH 0x0003
#define CFG_BOOT_BASE_ADDR 0xf0000000
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
#define CFG_MONITOR_BASE TEXT_BASE
-#define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */
-#define CFG_OCM_BASE 0xe0010000 /* ocm */
+#define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */
+#define CFG_OCM_BASE 0xe0010000 /* ocm */
#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
-#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
+#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
@@ -83,62 +83,62 @@
#define CFG_USB_HOST 0xe0000400
#define CFG_BCSR_BASE 0xc0000000
-/*-----------------------------------------------------------------------
+/*
* Initial RAM & stack pointer
- *----------------------------------------------------------------------*/
+ */
/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
#define CFG_INIT_RAM_END (4 << 10)
-#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
-/*-----------------------------------------------------------------------
+/*
* Serial Port
- *----------------------------------------------------------------------*/
+ */
#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SERIAL_MULTI 1
+#define CONFIG_SERIAL_MULTI 1
/* define this if you want console on UART1 */
#undef CONFIG_UART1_CONSOLE
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-/*-----------------------------------------------------------------------
+/*
* Environment
- *----------------------------------------------------------------------*/
+ */
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */
#else
-#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
-#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
+#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environ vars */
+#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
#endif
-/*-----------------------------------------------------------------------
+/*
* FLASH related
- *----------------------------------------------------------------------*/
-#define CFG_FLASH_CFI /* The flash is CFI compatible */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+ */
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
-#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
@@ -163,27 +163,28 @@
* set up. While still running from cache, I experienced problems accessing
* the NAND controller. sr - 2006-08-25
*/
-#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
-#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
-#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */
-#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
-#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
+#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
+#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
+#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */
+#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
+#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from */
+ /* this addr */
#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
/*
* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
*/
-#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
-#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
+#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
+#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
/*
* Now the NAND chip has to be defined (no autodetection used!)
*/
-#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
-#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
-#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
-#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
-#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
+#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
+#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
+#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
+#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
+#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
#define CFG_NAND_ECCSIZE 256
#define CFG_NAND_ECCBYTES 3
@@ -202,20 +203,20 @@
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
#endif
-/*-----------------------------------------------------------------------
+/*
* DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CFG_MBYTES_SDRAM (256) /* 256MB */
+ */
+#define CFG_MBYTES_SDRAM (256) /* 256MB */
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
+#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
#endif
-/*-----------------------------------------------------------------------
+/*
* I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_MULTI_EEPROMS
@@ -226,9 +227,9 @@
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
-#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
-#define CONFIG_DTT_AD7414 1 /* use AD7414 */
-#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
+#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
+#define CONFIG_DTT_AD7414 1 /* use AD7414 */
+#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
#define CFG_DTT_MAX_TEMP 70
#define CFG_DTT_LOW_TEMP -30
#define CFG_DTT_HYSTERESIS 3
@@ -290,12 +291,12 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CONFIG_HAS_ETH0
-#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx */
+ /* buffers & descriptors */
#define CONFIG_NET_MULTI 1
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY1_ADDR 1
@@ -322,7 +323,6 @@
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
-
/*
* BOOTP options
*/
@@ -332,7 +332,6 @@
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_SUBNETMASK
-
/*
* Command line configuration.
*/
@@ -367,26 +366,26 @@
#endif
/* POST support */
-#define CONFIG_POST (CFG_POST_MEMORY | \
+#define CONFIG_POST (CFG_POST_CACHE | \
CFG_POST_CPU | \
- CFG_POST_UART | \
- CFG_POST_I2C | \
- CFG_POST_CACHE | \
- CFG_POST_FPU_ON | \
CFG_POST_ETHER | \
- CFG_POST_SPR)
+ CFG_POST_FPU_ON | \
+ CFG_POST_I2C | \
+ CFG_POST_MEMORY | \
+ CFG_POST_SPR | \
+ CFG_POST_UART)
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
#define CONFIG_LOGBUFFER
-#define CFG_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
+#define CFG_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
-#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
#define CONFIG_SUPPORT_VFAT
-/*-----------------------------------------------------------------------
+/*
* Miscellaneous configurable options
- *----------------------------------------------------------------------*/
+ */
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
@@ -394,7 +393,8 @@
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+ /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
@@ -402,26 +402,26 @@
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-/*-----------------------------------------------------------------------
+/*
* PCI stuff
- *----------------------------------------------------------------------*/
+ */
/* General PCI */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
-
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
+ /* CFG_PCI_MEMBASE */
/* Board-specific PCI */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
@@ -430,54 +430,54 @@
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
+ * For booting Linux, the board info and command line data have to be in the
+ * first 8 MB of memory, since this is the maximum mapped by the Linux kernel
+ * during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
+/*
* External Bus Controller (EBC) Setup
- *----------------------------------------------------------------------*/
+ */
/*
* On Sequoia CS0 and CS3 are switched when configuring for NAND booting
*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-#define CFG_NAND_CS 3 /* NAND chip connected to CSx */
-/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CFG_NAND_CS 3 /* NAND chip connected to CSx */
+/* Memory Bank 0 (NOR-FLASH) initialization */
#define CFG_EBC_PB0AP 0x03017200
#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000)
-/* Memory Bank 3 (NAND-FLASH) initialization */
+/* Memory Bank 3 (NAND-FLASH) initialization */
#define CFG_EBC_PB3AP 0x018003c0
#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000)
#else
-#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
-/* Memory Bank 3 (NOR-FLASH) initialization */
+#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
+/* Memory Bank 3 (NOR-FLASH) initialization */
#define CFG_EBC_PB3AP 0x03017200
#define CFG_EBC_PB3CR (CFG_FLASH_BASE | 0xda000)
-/* Memory Bank 0 (NAND-FLASH) initialization */
+/* Memory Bank 0 (NAND-FLASH) initialization */
#define CFG_EBC_PB0AP 0x018003c0
#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000)
#endif
-/* Memory Bank 2 (CPLD) initialization */
+/* Memory Bank 2 (CPLD) initialization */
#define CFG_EBC_PB2AP 0x24814580
#define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x38000)
#define CFG_BCSR5_PCI66EN 0x80
-/*-----------------------------------------------------------------------
+/*
* NAND FLASH
- *----------------------------------------------------------------------*/
+ */
#define CFG_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
-#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
+#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
-/*-----------------------------------------------------------------------
+/*
* PPC440 GPIO Configuration
*/
/* test-only: take GPIO init from pcs440ep ???? in config file */
@@ -559,16 +559,16 @@
*
* Boot Flags
*/
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
-#endif /* __CONFIG_H */
+#endif /* __CONFIG_H */
diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h
index 84998d4..7a15d97 100644
--- a/include/configs/trizepsiv.h
+++ b/include/configs/trizepsiv.h
@@ -140,7 +140,7 @@
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
/* #define CONFIG_INITRD_TAG 1 */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h
index d167e01..4d1bdd7 100644
--- a/include/configs/xsengine.h
+++ b/include/configs/xsengine.h
@@ -33,7 +33,7 @@
#define CONFIG_XSENGINE 1
#define CONFIG_MMC 1
#define CONFIG_DOS_PARTITION 1
-#define OARD_LATE_INIT 1
+#define BOARD_LATE_INIT 1
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
@@ -86,8 +86,8 @@
#define CFG_ENV_SIZE 0x4000 /* 16kB Total Size of Environment Sector */
/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT (75*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT (50*CFG_HZ) /* Timeout for Flash Write */
+#define CFG_FLASH_ERASE_TOUT (75*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (50*CFG_HZ) /* Timeout for Flash Write */
/* Size of malloc() pool */
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024)
@@ -96,7 +96,7 @@
/* Hardware drivers */
#define CONFIG_DRIVER_SMC91111
#define CONFIG_SMC91111_BASE 0x04000300
-#define CONFIG_SMC_USE_32_BIT 1
+#define CONFIG_SMC_USE_32_BIT 1
/* select serial console configuration */
#define CONFIG_FFUART 1
@@ -138,15 +138,15 @@
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "XS-Engine u-boot> " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0xA0400000 /* memtest works on */
#define CFG_MEMTEST_END 0xA0800000 /* 4 ... 8 MB in DRAM */
-#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */
#define CFG_MMC_BASE 0xF0000000
-#define CFG_LOAD_ADDR 0xA0000000 /* load kernel to this address */
+#define CFG_LOAD_ADDR 0xA0000000 /* load kernel to this address */
/* Stack sizes - The stack sizes are set up in start.S using the settings below */
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
@@ -168,7 +168,7 @@
/* GP direction register */
#define CFG_GPDR0_VAL 0x0000A000 /* CS1, PROG(FPGA) */
#define CFG_GPDR1_VAL 0x00022A80 /* nPWE, FFUART + BTUART pins */
-#define CFG_GPDR2_VAL 0x0000C000 /* CS2, CS3 */
+#define CFG_GPDR2_VAL 0x0000C000 /* CS2, CS3 */
/* GP rising edge detect register */
#define CFG_GRER0_VAL 0x00000000
@@ -185,7 +185,7 @@
#define CFG_GAFR0_U_VAL 0x00000010 /* RDY */
#define CFG_GAFR1_L_VAL 0x09988050 /* FFUART + BTUART pins */
#define CFG_GAFR1_U_VAL 0x00000008 /* nPWE */
-#define CFG_GAFR2_L_VAL 0xA0000000 /* CS2, CS3 */
+#define CFG_GAFR2_L_VAL 0xA0000000 /* CS2, CS3 */
#define CFG_GAFR2_U_VAL 0x00000000
#define CFG_PSSR_VAL 0x00000020 /* Power manager sleep status */
diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
index a8eeff9..4c86bc5 100644
--- a/include/configs/yosemite.h
+++ b/include/configs/yosemite.h
@@ -75,7 +75,7 @@
*----------------------------------------------------------------------*/
#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
-#define CFG_INIT_RAM_END (8 << 10)
+#define CFG_INIT_RAM_END (4 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET