diff options
Diffstat (limited to 'include')
58 files changed, 321 insertions, 136 deletions
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 6b56fe7..2a205cd 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -61,7 +61,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 3edf52e..282366c 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -46,7 +46,6 @@ #endif /* High Level Configuration Options */ -#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_TSEC_ENET #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 557f6ef..969f448 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -68,7 +68,6 @@ #endif /* High Level Configuration Options */ -#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ #if defined(CONFIG_PCI) diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index b5d3737..3af2425 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -68,7 +68,6 @@ #endif /* High Level Configuration Options */ -#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ #ifdef CONFIG_PCI diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index a444a78..05a2360 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -130,7 +130,6 @@ #endif /* High Level Configuration Options */ -#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ #if defined(CONFIG_PCI) diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 480261b..325baa2 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -40,7 +40,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 275d898..e850f54 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -28,8 +28,6 @@ #define CONFIG_DEEP_SLEEP -#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ - #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg #define CONFIG_SPL_FLUSH_IMAGE diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index e464683..9a4af80 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -26,8 +26,6 @@ #define CONFIG_ENV_OVERWRITE -#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ - /* support deep sleep */ #ifdef CONFIG_ARCH_T1024 #define CONFIG_DEEP_SLEEP diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 6fd8827..8343f37 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index b3e9c28..bd1cfd4 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -161,7 +161,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index ff6fc2d..17daf1d 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -33,7 +33,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_ENV_OVERWRITE #ifdef CONFIG_RAMBOOT_PBL diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index f9534b7..e3d57e6 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -27,7 +27,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_ENV_OVERWRITE #ifdef CONFIG_RAMBOOT_PBL diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 3ef647e..9d4baaa 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -12,7 +12,6 @@ #define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE4 -#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index c35506c..e8ac43c 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -72,7 +72,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 18938bf..9408759 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -18,10 +18,6 @@ */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */ -/* Common ARM Erratas */ -#define CONFIG_ARM_ERRATA_454179 -#define CONFIG_ARM_ERRATA_430973 -#define CONFIG_ARM_ERRATA_621766 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index c98c663..f1584e4 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -19,11 +19,6 @@ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -/* Common ARM Erratas */ -#define CONFIG_ARM_ERRATA_454179 -#define CONFIG_ARM_ERRATA_430973 -#define CONFIG_ARM_ERRATA_621766 - #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ /* diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 74fd9c4..e6f2422 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -47,10 +47,6 @@ /* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */ #define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000 -/* CPU Errata */ -#define CONFIG_ARM_ERRATA_773022 -#define CONFIG_ARM_ERRATA_774769 - /* Power */ #define CONFIG_POWER #define CONFIG_POWER_I2C diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h index 6dd6f09..fc9dc9c 100644 --- a/include/configs/bav335x.h +++ b/include/configs/bav335x.h @@ -23,8 +23,6 @@ #ifndef CONFIG_SPL_BUILD # define CONFIG_TIMESTAMP # define CONFIG_LZO -# ifdef CONFIG_ENABLE_VBOOT -# endif #endif #define CONFIG_SYS_BOOTM_LEN (16 << 20) diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index d244824..e8b79a2 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -25,10 +25,6 @@ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP_GPIO #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ -/* Common ARM Erratas */ -#define CONFIG_ARM_ERRATA_454179 -#define CONFIG_ARM_ERRATA_430973 -#define CONFIG_ARM_ERRATA_621766 #define CONFIG_SDRC /* The chip has SDRC controller */ diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h index bfd3b50..c179a2b 100644 --- a/include/configs/cm_t3517.h +++ b/include/configs/cm_t3517.h @@ -15,10 +15,6 @@ */ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_CM_T3517 /* working with CM-T3517 */ -/* Common ARM Erratas */ -#define CONFIG_ARM_ERRATA_454179 -#define CONFIG_ARM_ERRATA_430973 -#define CONFIG_ARM_ERRATA_621766 #define CONFIG_SYS_TEXT_BASE 0x80008000 diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 8bed3e3..f810d34 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -58,7 +58,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index 700fb5e..676dfc9 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -122,7 +122,6 @@ #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD /* SPL related MMC defines */ -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 #define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS #ifdef CONFIG_SPL_BUILD diff --git a/include/configs/kc1.h b/include/configs/kc1.h index 76642d9..cc78a09 100644 --- a/include/configs/kc1.h +++ b/include/configs/kc1.h @@ -107,8 +107,6 @@ #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" #define CONFIG_SPL_BOARD_INIT -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 2 - /* * Console */ diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index c4ee23e..2fc3fe9 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -118,8 +118,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_FSL_CAAM /* Enable CAAM */ - /* * Serial Port */ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 774a1de..6b640c4 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -129,8 +129,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#define CONFIG_FSL_CAAM /* Enable CAAM */ - #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ !defined(CONFIG_QSPI_BOOT) #define CONFIG_U_QE diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index c49ad36..fe87ab3 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -133,9 +133,9 @@ * size increases then increase this size in case of secure boot as * it uses raw u-boot image instead of fit image. */ -#define CONFIG_SYS_MONITOR_LEN (0x80000 + CONFIG_U_BOOT_HDR_SIZE) +#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) #else -#define CONFIG_SYS_MONITOR_LEN 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0x100000 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ #endif @@ -154,8 +154,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_FSL_CAAM /* Enable CAAM */ - #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ !defined(CONFIG_QSPI_BOOT) #define CONFIG_U_QE diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index c4b05e0..9a01e48 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -145,8 +145,6 @@ #endif #endif -#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ - /* FMan ucode */ #define CONFIG_SYS_DPAA_FMAN #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index f3b521d..6a345c0 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -38,7 +38,9 @@ unsigned long get_board_ddr_clk(void); #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SPD_BUS_NUM 0 +#ifndef CONFIG_SPL #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#endif #define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 8fa3bb3..f185380 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -29,7 +29,9 @@ #define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_FSL_DDR_BIST +#ifndef CONFIG_SPL #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#endif #define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index be65e4f..8ec1247 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -118,8 +118,6 @@ #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 #endif -#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ - #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ /* FMan ucode */ diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index cba22ca..4b3b21e 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -38,7 +38,9 @@ unsigned long get_board_ddr_clk(void); #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SPD_BUS_NUM 0 +#ifndef CONFIG_SPL #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#endif #define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index a96aa65..2141b82 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -34,7 +34,9 @@ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ +#ifndef CONFIG_SPL #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#endif #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 4bfd0ac..816d7f5 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -21,8 +21,6 @@ /* We need architecture specific misc initializations */ -#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ - /* Link Definitions */ #ifndef CONFIG_QSPI_BOOT #ifdef CONFIG_SPL @@ -143,7 +141,6 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 /* MC firmware */ -#define CONFIG_FSL_MC_ENET /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 @@ -161,7 +158,6 @@ unsigned long long get_qixis_addr(void); */ #ifdef CONFIG_FSL_MC_ENET #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) -#define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024) #endif /* Command line configuration */ diff --git a/include/configs/mcx.h b/include/configs/mcx.h index ef44110..06c1a95 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -15,10 +15,6 @@ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP3_MCX /* working with mcx */ #define CONFIG_OMAP_GPIO -/* Common ARM Erratas */ -#define CONFIG_ARM_ERRATA_454179 -#define CONFIG_ARM_ERRATA_430973 -#define CONFIG_ARM_ERRATA_621766 #define CONFIG_MACH_TYPE MACH_TYPE_MCX diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 39d6418..afe9b93 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -8,11 +8,6 @@ #define __MX6_COMMON_H #ifndef CONFIG_MX6UL -#define CONFIG_ARM_ERRATA_743622 -#define CONFIG_ARM_ERRATA_751472 -#define CONFIG_ARM_ERRATA_794072 -#define CONFIG_ARM_ERRATA_761320 - #ifndef CONFIG_SYS_L2CACHE_OFF #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE L2_PL310_BASE @@ -90,7 +85,6 @@ /* Secure boot (HAB) support */ #ifdef CONFIG_SECURE_BOOT #define CONFIG_CSF_SIZE 0x2000 -#define CONFIG_FSL_CAAM #define CONFIG_CMD_DEKBLOB #ifdef CONFIG_SPL_BUILD #define CONFIG_SPL_DRIVERS_MISC_SUPPORT diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index 837d5f7..b10b7f1 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -68,7 +68,6 @@ /* Secure boot (HAB) support */ #ifdef CONFIG_SECURE_BOOT #define CONFIG_CSF_SIZE 0x2000 -#define CONFIG_FSL_CAAM #define CONFIG_CMD_DEKBLOB #endif diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index e17c3c0..5b0cb2e 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -27,10 +27,6 @@ #define CONFIG_OMAP3430 /* which is in a 3430 */ #define CONFIG_OMAP3_RX51 /* working with RX51 */ #define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */ -/* Common ARM Erratas */ -#define CONFIG_ARM_ERRATA_454179 -#define CONFIG_ARM_ERRATA_430973 -#define CONFIG_ARM_ERRATA_621766 #define CONFIG_MACH_TYPE MACH_TYPE_NOKIA_RX51 diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 6a57ebd..a28f9ba 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -85,10 +85,6 @@ */ #define CONFIG_OMAP /* This is TI OMAP core */ #define CONFIG_OMAP_GPIO -/* Common ARM Erratas */ -#define CONFIG_ARM_ERRATA_454179 -#define CONFIG_ARM_ERRATA_430973 -#define CONFIG_ARM_ERRATA_621766 #define CONFIG_SDRC /* The chip has SDRC controller */ diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index ac0df3e..70d337e 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -140,7 +140,7 @@ #define CONFIG_SPL_UBI_INFO_ADDR 0x88080000 /* environment organization */ -#define CONFIG_ENV_IS_IN_UBI 1 +#define CONFIG_ENV_IS_NOWHERE 1 #define CONFIG_ENV_UBI_PART "UBI" #define CONFIG_ENV_UBI_VOLUME "config" #define CONFIG_ENV_UBI_VOLUME_REDUND "config_r" diff --git a/include/configs/sniper.h b/include/configs/sniper.h index a1431ca..83fa6e0 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -17,9 +17,6 @@ */ #define CONFIG_ARM_ARCH_CP15_ERRATA -#define CONFIG_ARM_ERRATA_454179 -#define CONFIG_ARM_ERRATA_430973 -#define CONFIG_ARM_ERRATA_621766 /* * Platform @@ -115,8 +112,6 @@ #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" #define CONFIG_SPL_BOARD_INIT -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 2 - #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index b187860..582b04a 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -310,8 +310,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" -#else -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 #endif #endif diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h new file mode 100644 index 0000000..28e2f7f --- /dev/null +++ b/include/configs/stih410-b2260.h @@ -0,0 +1,60 @@ +/* + * (C) Copyright 2017 + * Patrice Chotard, <patrice.chotard@st.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <config.h> + +/* ram memory-related information */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x40000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define PHYS_SDRAM_1_SIZE 0x3FE00000 +#define CONFIG_SYS_TEXT_BASE 0x7D600000 +#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 /* default load addr */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_HZ_CLOCK 1000000000 /* 1 GHz */ + +/* Libraries */ +#define CONFIG_MD5 + +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" + +/* Environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "board= B2260" \ + "load_addr= #CONFIG_SYS_LOAD_ADDR \0" + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x4000 + +/* Extra Commands */ +#define CONFIG_CMD_ASKENV +#define CONFIG_SYS_LONGHELP + +#define CONFIG_SETUP_MEMORY_TAGS + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN 0x1800000 +#define CONFIG_SYS_GBL_DATA_SIZE 1024 /* Global data structures */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \ + CONFIG_SYS_MALLOC_LEN - \ + CONFIG_SYS_GBL_DATA_SIZE) + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#endif /* __CONFIG_H */ diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 87b5315..2704319 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -15,10 +15,6 @@ */ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP_GPIO -/* Common ARM Erratas */ -#define CONFIG_ARM_ERRATA_454179 -#define CONFIG_ARM_ERRATA_430973 -#define CONFIG_ARM_ERRATA_621766 #define CONFIG_SYS_TEXT_BASE 0x80008000 diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 89d2e6b..ead8ea7 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -19,10 +19,6 @@ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP_GPIO -/* Common ARM Erratas */ -#define CONFIG_ARM_ERRATA_454179 -#define CONFIG_ARM_ERRATA_430973 -#define CONFIG_ARM_ERRATA_621766 #define CONFIG_SDRC /* Has an SDRC controller */ diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 793310f..db1cc24 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -10,13 +10,6 @@ #include "tegra-common.h" /* - * Errata configuration - */ -#define CONFIG_ARM_ERRATA_716044 -#define CONFIG_ARM_ERRATA_742230 -#define CONFIG_ARM_ERRATA_751472 - -/* * NS16550 Configuration */ #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index baf3d00..6083847 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -10,12 +10,6 @@ #include "tegra-common.h" /* - * Errata configuration - */ -#define CONFIG_ARM_ERRATA_743622 -#define CONFIG_ARM_ERRATA_751472 - -/* * NS16550 Configuration */ #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 0ad3235..0147662 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -21,11 +21,6 @@ #include <asm/arch/cpu.h> #include <asm/arch/omap.h> -/* Common ARM Erratas */ -#define CONFIG_ARM_ERRATA_454179 -#define CONFIG_ARM_ERRATA_430973 -#define CONFIG_ARM_ERRATA_621766 - /* The chip has SDRC controller */ #define CONFIG_SDRC diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 37d6565..7fb1bb6 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -17,9 +17,6 @@ #ifndef __CONFIG_TI_OMAP5_COMMON_H #define __CONFIG_TI_OMAP5_COMMON_H -/* Common ARM Erratas */ -#define CONFIG_ARM_ERRATA_798870 - /* Use General purpose timer 1 */ #define CONFIG_SYS_TIMERBASE GPT2_BASE diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 09783a2..1c0a762 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -93,10 +93,6 @@ #define CONFIG_MII #define CONFIG_ARP_TIMEOUT 200UL -/* Network config - Allow larger/faster download for TFTP/NFS */ -#define CONFIG_IP_DEFRAG -#define CONFIG_TFTP_BLOCKSIZE 4096 -#define CONFIG_NFS_READ_SIZE 4096 /* Command definition */ #define CONFIG_CMD_BMODE @@ -137,8 +133,8 @@ "update_uboot=if tftp ${uboot}; then " \ "if itest ${filesize} > 0; then " \ "mmc dev ${mmcdev}; mmc rescan; " \ - "setexpr blkc ${filesize} / 0x200; " \ - "setexpr blkc ${blkc} + 1; " \ + "setexpr blkc ${filesize} + 0x1ff; " \ + "setexpr blkc ${blkc} / 0x200; " \ "if itest ${blkc} <= ${uboot_size}; then " \ "mmc write ${loadaddr} ${uboot_start} " \ "${blkc}; " \ @@ -149,8 +145,8 @@ "if tftp ${kernel}; then " \ "if itest ${filesize} > 0; then " \ "mmc dev ${mmcdev}; mmc rescan; " \ - "setexpr blkc ${filesize} / 0x200; " \ - "setexpr blkc ${blkc} + 1; " \ + "setexpr blkc ${filesize} + 0x1ff; " \ + "setexpr blkc ${blkc} / 0x200; " \ "if itest ${blkc} <= ${kernel_size}; then " \ "mmc write ${loadaddr} " \ "${kernel_start} ${blkc}; " \ @@ -161,8 +157,8 @@ "update_fdt=if tftp ${fdt_file}; then " \ "if itest ${filesize} > 0; then " \ "mmc dev ${mmcdev}; mmc rescan; " \ - "setexpr blkc ${filesize} / 0x200; " \ - "setexpr blkc ${blkc} + 1; " \ + "setexpr blkc ${filesize} + 0x1ff; " \ + "setexpr blkc ${blkc} / 0x200; " \ "if itest ${blkc} <= ${fdt_size}; then " \ "mmc write ${loadaddr} ${fdt_start} ${blkc}; " \ "fi; " \ @@ -266,7 +262,7 @@ __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ "setexpr offset ${fdt_start} * " \ __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "sf read ${${fdt_addr}} ${offset} ${size}; " \ + "sf read ${fdt_addr} ${offset} ${size}; " \ "setenv size ; setenv offset\0" \ #define CONFIG_BOOTCOMMAND \ @@ -281,6 +277,9 @@ /* 128 MiB offset as in ARM related docu for linux suggested */ #define TQMA6_FDT_ADDRESS 0x18000000 +/* set to a resonable value, changeable by user */ +#define TQMA6_CMA_SIZE 160M + #define CONFIG_EXTRA_ENV_SETTINGS \ "board=tqma6\0" \ "uimage=uImage\0" \ @@ -292,17 +291,21 @@ "uboot=u-boot.imx\0" \ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "fdt_addr="__stringify(TQMA6_FDT_ADDRESS)"\0" \ - "console=" CONSOLE_DEV "\0" \ + "console=" CONSOLE_DEV "\0" \ + "cma_size="__stringify(TQMA6_CMA_SIZE)"\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ + "rootfsmode=ro\0" \ + "addcma=setenv bootargs ${bootargs} cma=${cma_size}\0" \ "addtty=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \ "addfb=setenv bootargs ${bootargs} " \ "imx-fbdev.legacyfb_depth=32 consoleblank=0\0" \ "mmcpart=2\0" \ "mmcblkdev=0\0" \ - "mmcargs=run addmmc addtty addfb\0" \ + "mmcargs=run addmmc addtty addfb addcma\0" \ "addmmc=setenv bootargs ${bootargs} " \ - "root=/dev/mmcblk${mmcblkdev}p${mmcpart} rw rootwait\0" \ + "root=/dev/mmcblk${mmcblkdev}p${mmcpart} ${rootfsmode} " \ + "rootwait\0" \ "mmcboot=echo Booting from mmc ...; " \ "setenv bootargs; " \ "run mmcargs; " \ @@ -317,7 +320,7 @@ "netdev=eth0\0" \ "rootpath=/srv/nfs/tqma6\0" \ "ipmode=static\0" \ - "netargs=run addnfs addip addtty addfb\0" \ + "netargs=run addnfs addip addtty addfb addcma\0" \ "addnfs=setenv bootargs ${bootargs} " \ "root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath},v3,tcp;\0" \ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index e4b3290..2b80352 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -19,10 +19,6 @@ /* High Level Configuration Options */ #define CONFIG_SYS_THUMB_BUILD #define CONFIG_OMAP /* in a TI OMAP core */ -/* Common ARM Erratas */ -#define CONFIG_ARM_ERRATA_454179 -#define CONFIG_ARM_ERRATA_430973 -#define CONFIG_ARM_ERRATA_621766 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER /* diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 23a3685..1d737cc 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -30,6 +30,7 @@ /* Linux only */ #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0,115200\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "fdtfile=undefined\0" \ @@ -51,7 +52,7 @@ "echo WARNING: Could not determine dtb to use; fi\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "ramdisk_addr_r=0x83000000\0" \ + "ramdisk_addr_r=0x84000000\0" \ "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ BOOTENV diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index ab35191..2976d63 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -142,7 +142,7 @@ #if defined(CONFIG_ARM64) && !defined(CONFIG_ARMV8_MULTIENTRY) /* ARM Trusted Firmware */ #define BOOT_IMAGES \ - "second_image=bl1.bin\0" \ + "second_image=unph_bl.bin\0" \ "third_image=fip.bin\0" #else #define BOOT_IMAGES \ diff --git a/include/dt-bindings/clock/stih407-clks.h b/include/dt-bindings/clock/stih407-clks.h new file mode 100644 index 0000000..082edd9 --- /dev/null +++ b/include/dt-bindings/clock/stih407-clks.h @@ -0,0 +1,90 @@ +/* + * This header provides constants clk index STMicroelectronics + * STiH407 SoC. + */ +#ifndef _DT_BINDINGS_CLK_STIH407 +#define _DT_BINDINGS_CLK_STIH407 + +/* CLOCKGEN A0 */ +#define CLK_IC_LMI0 0 +#define CLK_IC_LMI1 1 + +/* CLOCKGEN C0 */ +#define CLK_ICN_GPU 0 +#define CLK_FDMA 1 +#define CLK_NAND 2 +#define CLK_HVA 3 +#define CLK_PROC_STFE 4 +#define CLK_PROC_TP 5 +#define CLK_RX_ICN_DMU 6 +#define CLK_RX_ICN_DISP_0 6 +#define CLK_RX_ICN_DISP_1 6 +#define CLK_RX_ICN_HVA 7 +#define CLK_RX_ICN_TS 7 +#define CLK_ICN_CPU 8 +#define CLK_TX_ICN_DMU 9 +#define CLK_TX_ICN_HVA 9 +#define CLK_TX_ICN_TS 9 +#define CLK_ICN_COMPO 9 +#define CLK_MMC_0 10 +#define CLK_MMC_1 11 +#define CLK_JPEGDEC 12 +#define CLK_ICN_REG 13 +#define CLK_TRACE_A9 13 +#define CLK_PTI_STM 13 +#define CLK_EXT2F_A9 13 +#define CLK_IC_BDISP_0 14 +#define CLK_IC_BDISP_1 15 +#define CLK_PP_DMU 16 +#define CLK_VID_DMU 17 +#define CLK_DSS_LPC 18 +#define CLK_ST231_AUD_0 19 +#define CLK_ST231_GP_0 19 +#define CLK_ST231_GP_1 20 +#define CLK_ST231_DMU 21 +#define CLK_ICN_LMI 22 +#define CLK_TX_ICN_DISP_0 23 +#define CLK_TX_ICN_DISP_1 23 +#define CLK_ICN_SBC 24 +#define CLK_STFE_FRC2 25 +#define CLK_ETH_PHY 26 +#define CLK_ETH_REF_PHYCLK 27 +#define CLK_FLASH_PROMIP 28 +#define CLK_MAIN_DISP 29 +#define CLK_AUX_DISP 30 +#define CLK_COMPO_DVP 31 + +/* CLOCKGEN D0 */ +#define CLK_PCM_0 0 +#define CLK_PCM_1 1 +#define CLK_PCM_2 2 +#define CLK_SPDIFF 3 + +/* CLOCKGEN D2 */ +#define CLK_PIX_MAIN_DISP 0 +#define CLK_PIX_PIP 1 +#define CLK_PIX_GDP1 2 +#define CLK_PIX_GDP2 3 +#define CLK_PIX_GDP3 4 +#define CLK_PIX_GDP4 5 +#define CLK_PIX_AUX_DISP 6 +#define CLK_DENC 7 +#define CLK_PIX_HDDAC 8 +#define CLK_HDDAC 9 +#define CLK_SDDAC 10 +#define CLK_PIX_DVO 11 +#define CLK_DVO 12 +#define CLK_PIX_HDMI 13 +#define CLK_TMDS_HDMI 14 +#define CLK_REF_HDMIPHY 15 + +/* CLOCKGEN D3 */ +#define CLK_STFE_FRC1 0 +#define CLK_TSOUT_0 1 +#define CLK_TSOUT_1 2 +#define CLK_MCHI 3 +#define CLK_VSENS_COMPO 4 +#define CLK_FRC1_REMOTE 5 +#define CLK_LPC_0 6 +#define CLK_LPC_1 7 +#endif diff --git a/include/dt-bindings/clock/stih410-clks.h b/include/dt-bindings/clock/stih410-clks.h new file mode 100644 index 0000000..2097a4b --- /dev/null +++ b/include/dt-bindings/clock/stih410-clks.h @@ -0,0 +1,25 @@ +/* + * This header provides constants clk index STMicroelectronics + * STiH410 SoC. + */ +#ifndef _DT_BINDINGS_CLK_STIH410 +#define _DT_BINDINGS_CLK_STIH410 + +#include "stih407-clks.h" + +/* STiH410 introduces new clock outputs compared to STiH407 */ + +/* CLOCKGEN C0 */ +#define CLK_TX_ICN_HADES 32 +#define CLK_RX_ICN_HADES 33 +#define CLK_ICN_REG_16 34 +#define CLK_PP_HADES 35 +#define CLK_CLUST_HADES 36 +#define CLK_HWPE_HADES 37 +#define CLK_FC_HADES 38 + +/* CLOCKGEN D0 */ +#define CLK_PCMR10_MASTER 4 +#define CLK_USB2_PHY 5 + +#endif diff --git a/include/dt-bindings/interrupt-controller/irq-st.h b/include/dt-bindings/interrupt-controller/irq-st.h new file mode 100644 index 0000000..6baa9ad --- /dev/null +++ b/include/dt-bindings/interrupt-controller/irq-st.h @@ -0,0 +1,30 @@ +/* + * include/linux/irqchip/irq-st.h + * + * Copyright (C) 2014 STMicroelectronics All Rights Reserved + * + * Author: Lee Jones <lee.jones@linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ST_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ST_H + +#define ST_IRQ_SYSCFG_EXT_0 0 +#define ST_IRQ_SYSCFG_EXT_1 1 +#define ST_IRQ_SYSCFG_EXT_2 2 +#define ST_IRQ_SYSCFG_CTI_0 3 +#define ST_IRQ_SYSCFG_CTI_1 4 +#define ST_IRQ_SYSCFG_PMU_0 5 +#define ST_IRQ_SYSCFG_PMU_1 6 +#define ST_IRQ_SYSCFG_pl310_L2 7 +#define ST_IRQ_SYSCFG_DISABLED 0xFFFFFFFF + +#define ST_IRQ_SYSCFG_EXT_1_INV 0x1 +#define ST_IRQ_SYSCFG_EXT_2_INV 0x2 +#define ST_IRQ_SYSCFG_EXT_3_INV 0x4 + +#endif diff --git a/include/dt-bindings/mfd/st-lpc.h b/include/dt-bindings/mfd/st-lpc.h new file mode 100644 index 0000000..d05894a --- /dev/null +++ b/include/dt-bindings/mfd/st-lpc.h @@ -0,0 +1,16 @@ +/* + * This header provides shared DT/Driver defines for ST's LPC device + * + * Copyright (C) 2014 STMicroelectronics -- All Rights Reserved + * + * Author: Lee Jones <lee.jones@linaro.org> for STMicroelectronics + */ + +#ifndef __DT_BINDINGS_ST_LPC_H__ +#define __DT_BINDINGS_ST_LPC_H__ + +#define ST_LPC_MODE_RTC 0 +#define ST_LPC_MODE_WDT 1 +#define ST_LPC_MODE_CLKSRC 2 + +#endif /* __DT_BINDINGS_ST_LPC_H__ */ diff --git a/include/dt-bindings/reset/stih407-resets.h b/include/dt-bindings/reset/stih407-resets.h new file mode 100644 index 0000000..4ab3a1c --- /dev/null +++ b/include/dt-bindings/reset/stih407-resets.h @@ -0,0 +1,65 @@ +/* + * This header provides constants for the reset controller + * based peripheral powerdown requests on the STMicroelectronics + * STiH407 SoC. + */ +#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH407 +#define _DT_BINDINGS_RESET_CONTROLLER_STIH407 + +/* Powerdown requests control 0 */ +#define STIH407_EMISS_POWERDOWN 0 +#define STIH407_NAND_POWERDOWN 1 + +/* Synp GMAC PowerDown */ +#define STIH407_ETH1_POWERDOWN 2 + +/* Powerdown requests control 1 */ +#define STIH407_USB3_POWERDOWN 3 +#define STIH407_USB2_PORT1_POWERDOWN 4 +#define STIH407_USB2_PORT0_POWERDOWN 5 +#define STIH407_PCIE1_POWERDOWN 6 +#define STIH407_PCIE0_POWERDOWN 7 +#define STIH407_SATA1_POWERDOWN 8 +#define STIH407_SATA0_POWERDOWN 9 + +/* Reset defines */ +#define STIH407_ETH1_SOFTRESET 0 +#define STIH407_MMC1_SOFTRESET 1 +#define STIH407_PICOPHY_SOFTRESET 2 +#define STIH407_IRB_SOFTRESET 3 +#define STIH407_PCIE0_SOFTRESET 4 +#define STIH407_PCIE1_SOFTRESET 5 +#define STIH407_SATA0_SOFTRESET 6 +#define STIH407_SATA1_SOFTRESET 7 +#define STIH407_MIPHY0_SOFTRESET 8 +#define STIH407_MIPHY1_SOFTRESET 9 +#define STIH407_MIPHY2_SOFTRESET 10 +#define STIH407_SATA0_PWR_SOFTRESET 11 +#define STIH407_SATA1_PWR_SOFTRESET 12 +#define STIH407_DELTA_SOFTRESET 13 +#define STIH407_BLITTER_SOFTRESET 14 +#define STIH407_HDTVOUT_SOFTRESET 15 +#define STIH407_HDQVDP_SOFTRESET 16 +#define STIH407_VDP_AUX_SOFTRESET 17 +#define STIH407_COMPO_SOFTRESET 18 +#define STIH407_HDMI_TX_PHY_SOFTRESET 19 +#define STIH407_JPEG_DEC_SOFTRESET 20 +#define STIH407_VP8_DEC_SOFTRESET 21 +#define STIH407_GPU_SOFTRESET 22 +#define STIH407_HVA_SOFTRESET 23 +#define STIH407_ERAM_HVA_SOFTRESET 24 +#define STIH407_LPM_SOFTRESET 25 +#define STIH407_KEYSCAN_SOFTRESET 26 +#define STIH407_USB2_PORT0_SOFTRESET 27 +#define STIH407_USB2_PORT1_SOFTRESET 28 +#define STIH407_ST231_AUD_SOFTRESET 29 +#define STIH407_ST231_DMU_SOFTRESET 30 +#define STIH407_ST231_GP0_SOFTRESET 31 +#define STIH407_ST231_GP1_SOFTRESET 32 + +/* Picophy reset defines */ +#define STIH407_PICOPHY0_RESET 0 +#define STIH407_PICOPHY1_RESET 1 +#define STIH407_PICOPHY2_RESET 2 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH407 */ diff --git a/include/part.h b/include/part.h index 9d0e20d..b6d1b33 100644 --- a/include/part.h +++ b/include/part.h @@ -59,6 +59,9 @@ typedef struct disk_partition { #ifdef CONFIG_PARTITION_TYPE_GUID char type_guid[37]; /* type GUID as string, if exists */ #endif +#ifdef CONFIG_DOS_PARTITION + uchar sys_ind; /* partition type */ +#endif } disk_partition_t; /* Misc _get_dev functions */ |