diff options
Diffstat (limited to 'include')
272 files changed, 2191 insertions, 548 deletions
diff --git a/include/common.h b/include/common.h index e910730..75c78d5 100644 --- a/include/common.h +++ b/include/common.h @@ -432,7 +432,6 @@ int get_env_id (void); void pci_init (void); void pci_init_board(void); -void pciinfo (int, int); #if defined(CONFIG_PCI) && defined(CONFIG_4xx) int pci_pre_init (struct pci_controller *); @@ -474,10 +473,7 @@ void reset_phy (void); void fdc_hw_init (void); /* $(BOARD)/eeprom.c */ -void eeprom_init (void); -#ifndef CONFIG_SPI -int eeprom_probe (unsigned dev_addr, unsigned offset); -#endif +void eeprom_init (int bus); int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt); int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt); diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h index 48d5063..8a91cdb 100644 --- a/include/configs/10m50_devboard.h +++ b/include/configs/10m50_devboard.h @@ -20,6 +20,7 @@ */ #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress console info */ +#define CONFIG_SYS_NS16550_MEM32 /* * Flash diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index c83e5ce..9fb5cee 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -483,7 +483,6 @@ unsigned long get_board_ddr_clk(void); * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -587,8 +586,6 @@ unsigned long get_board_ddr_clk(void); /* * eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_SST #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 2754016..4b5ad0e 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -227,7 +227,6 @@ extern unsigned long get_sdram_size(void); /* Serial Port */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -267,7 +266,6 @@ extern unsigned long get_sdram_size(void); /* I2C EEPROM */ #define CONFIG_CMD_EEPROM -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 @@ -275,10 +273,8 @@ extern unsigned long get_sdram_size(void); #define CONFIG_CMD_I2C -#define CONFIG_FSL_ESPI /* eSPI - Enhanced SPI */ #ifdef CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 54dcf3b..d0e5a25 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -408,7 +408,6 @@ combinations. this should be removed later /* Serial Port */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -463,7 +462,6 @@ combinations. this should be removed later /* enable read and write access to EEPROM */ #define CONFIG_CMD_EEPROM -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 @@ -480,9 +478,7 @@ combinations. this should be removed later * used for SLIC */ /* eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI /* SPI */ #ifdef CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 94f991b..16920c6 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -377,7 +377,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -420,7 +419,6 @@ /* I2C EEPROM */ /* enable read and write access to EEPROM */ #define CONFIG_CMD_EEPROM -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 @@ -428,9 +426,6 @@ #define CONFIG_CMD_I2C /* eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_SPANSION -#define CONFIG_SPI_FLASH_EON #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index e00ab04..c3a7714 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -89,7 +89,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #define CONFIG_CONS_INDEX 2 /* Use UART1 */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index 332a1df..1e5285c 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -113,7 +113,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h index ffee225..f2ea9a8 100644 --- a/include/configs/M52277EVB.h +++ b/include/configs/M52277EVB.h @@ -131,7 +131,6 @@ #define CONFIG_SYS_SBFHDR_SIZE 0x7 #ifdef CONFIG_CMD_SPI # define CONFIG_SYS_DSPI_CS2 -# define CONFIG_SPI_FLASH_STMICRO # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ DSPI_CTAR_PCSSCK_1CLK | \ diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h index 927b7da..05ba13b 100644 --- a/include/configs/M54418TWR.h +++ b/include/configs/M54418TWR.h @@ -193,7 +193,6 @@ #define CONFIG_HARD_SPI #define CONFIG_SYS_SBFHDR_SIZE 0x7 #ifdef CONFIG_CMD_SPI -# define CONFIG_SPI_FLASH_ATMEL # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ DSPI_CTAR_PCSSCK_1CLK | \ diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h index 61ebb24..c778823 100644 --- a/include/configs/M54451EVB.h +++ b/include/configs/M54451EVB.h @@ -141,7 +141,6 @@ #define CONFIG_HARD_SPI #define CONFIG_SYS_SBFHDR_SIZE 0x7 #ifdef CONFIG_CMD_SPI -# define CONFIG_SPI_FLASH_STMICRO # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ DSPI_CTAR_PCSSCK_1CLK | \ diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index f813dab..7941040 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -173,7 +173,6 @@ #define CONFIG_HARD_SPI #define CONFIG_SYS_SBFHDR_SIZE 0x13 #ifdef CONFIG_CMD_SPI -# define CONFIG_SPI_FLASH_STMICRO # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ DSPI_CTAR_PCSSCK_1CLK | \ diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index ba93c18..1a793d7 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -160,7 +160,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */ #define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 551b72d..955ce62 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -315,7 +315,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -354,7 +353,6 @@ #ifdef CONFIG_MPC8XXX_SPI #define CONFIG_CMD_SPI #define CONFIG_USE_SPIFLASH -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #endif diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 44c3175..fa6dd6f 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -370,7 +370,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index eb50be6..ba952e3 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -292,7 +292,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 59d5e56..a1d45d8 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -212,7 +212,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 5ab7d5f..b3322ae 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -292,7 +292,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 988a900..71dcc6c 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -318,7 +318,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 091ca17..ded73b4 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -353,7 +353,6 @@ boards, we say we have two, but don't display a message if we find only one. */ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 7d1262d..df47888 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -308,7 +308,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index ab68e63..e77848e 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -329,7 +329,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index f582f55..294be3b 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -368,7 +368,6 @@ * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -420,10 +419,8 @@ * eSPI - Enhanced SPI */ #define CONFIG_HARD_SPI -#define CONFIG_FSL_ESPI #if defined(CONFIG_SPI_FLASH) -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 157ca69..921180f 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -221,7 +221,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 68ea5d8..d5805c1 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -244,7 +244,6 @@ extern unsigned long get_clock_freq(void); /* Serial Port */ #define CONFIG_CONS_INDEX 2 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 6ec072c..0fa5fd3 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -196,7 +196,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 517b449..a84ebfd 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -321,7 +321,6 @@ extern unsigned long get_clock_freq(void); /* Serial Port */ #define CONFIG_CONS_INDEX 2 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 184f514..84b8174 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -242,7 +242,6 @@ extern unsigned long get_clock_freq(void); /* Serial Port */ #define CONFIG_CONS_INDEX 2 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index f6e43ce..03ba806 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -227,7 +227,6 @@ extern unsigned long get_clock_freq(void); /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 6f614b0..f86d10f 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -235,7 +235,6 @@ extern unsigned long get_clock_freq(void); /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 9b131a2..b34a033 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -364,7 +364,6 @@ * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 4ce04a8..8160b28 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -225,7 +225,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index a5dad2d..a84db51 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -259,7 +259,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 81b0855..f9776c0 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -604,7 +604,6 @@ extern unsigned long get_sdram_size(void); /* Serial Port */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -660,7 +659,6 @@ extern unsigned long get_sdram_size(void); #endif /* enable read and write access to EEPROM */ #define CONFIG_CMD_EEPROM -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 @@ -677,8 +675,6 @@ extern unsigned long get_sdram_size(void); */ #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) /* eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index a9d825b..6235bbb 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -393,7 +393,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -478,10 +477,8 @@ /* * eSPI - Enhanced SPI */ -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_HARD_SPI -#define CONFIG_FSL_ESPI #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index 4d87198..bc479f6 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -162,7 +162,6 @@ extern unsigned long get_clock_freq(void); /* Serial Port */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 2c4c8b5..b2e51b5 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -324,7 +324,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -410,8 +409,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); /* * eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index aac5a4d..b5959c8 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -153,7 +153,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */ #define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index d668a15..4eb5fe1 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -114,7 +114,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h index 0fdd7e2..ce0c49f 100644 --- a/include/configs/PMC405DE.h +++ b/include/configs/PMC405DE.h @@ -88,7 +88,6 @@ #define CONFIG_SYS_MEMTEST_END 0x3000000 /* 1 ... 48 MB in DRAM */ #define CONFIG_CONS_INDEX 2 /* Use UART1 */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index 0227649..05ad315 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -84,7 +84,6 @@ * Serial Port *----------------------------------------------------------------------*/ #define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() @@ -159,7 +158,6 @@ #define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 52942ed..951cbc4 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -495,7 +495,6 @@ unsigned long get_board_ddr_clk(void); /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -579,11 +578,7 @@ unsigned long get_board_ddr_clk(void); /* * eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_STMICRO #ifndef CONFIG_SPL_BUILD -#define CONFIG_SPI_FLASH_SST -#define CONFIG_SPI_FLASH_EON #endif #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH_BAR diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 39fa5e2..4a0f5b2 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -496,7 +496,6 @@ unsigned long get_board_ddr_clk(void); /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -568,11 +567,8 @@ unsigned long get_board_ddr_clk(void); /* * eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI #if defined(CONFIG_T1024RDB) -#define CONFIG_SPI_FLASH_STMICRO #elif defined(CONFIG_T1023RDB) -#define CONFIG_SPI_FLASH_SPANSION #endif #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH_BAR diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index fc263df..9e151da 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -398,7 +398,6 @@ unsigned long get_board_ddr_clk(void); * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -483,10 +482,6 @@ unsigned long get_board_ddr_clk(void); /* * eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_SST -#define CONFIG_SPI_FLASH_EON #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 840be04..da65f56 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -450,7 +450,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -538,8 +537,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg /* * eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SPI_FLASH_BAR #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index a81f1e6..a0cecc6 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -445,7 +445,6 @@ unsigned long get_board_ddr_clk(void); * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -551,11 +550,7 @@ unsigned long get_board_ddr_clk(void); * eSPI - Enhanced SPI */ #ifdef CONFIG_SPI_FLASH -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_STMICRO #ifndef CONFIG_SPL_BUILD -#define CONFIG_SPI_FLASH_SST -#define CONFIG_SPI_FLASH_EON #endif #define CONFIG_CMD_SF diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 8b76234..312b0eb 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -405,7 +405,6 @@ unsigned long get_board_ddr_clk(void); * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -505,8 +504,6 @@ unsigned long get_board_ddr_clk(void); * eSPI - Enhanced SPI */ #ifdef CONFIG_SPI_FLASH -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SPI_FLASH_BAR #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 4edb3cb..1b94f64 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -401,8 +401,6 @@ unsigned long get_board_ddr_clk(void); /* * eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_SST #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 2e875d2..73279c8 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -197,7 +197,6 @@ * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -610,8 +609,6 @@ unsigned long get_board_ddr_clk(void); /* * eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_SST #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 0b046d1..58a17f5 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -158,7 +158,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -183,7 +182,6 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS /* more than one eeprom */ /* I2C RTC */ #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index ad2f115..2354009 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -329,7 +329,6 @@ */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -380,11 +379,7 @@ * eSPI - Enhanced SPI */ #define CONFIG_HARD_SPI -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_SST 1 -#define CONFIG_SPI_FLASH_STMICRO 1 -#define CONFIG_SPI_FLASH_WINBOND 1 #define CONFIG_CMD_SF 1 #define CONFIG_CMD_SPI 1 #define CONFIG_SF_DEFAULT_SPEED 10000000 diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index 60f266c..6cbf1b7 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -99,7 +99,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() diff --git a/include/configs/acadia.h b/include/configs/acadia.h index 4dd5720..2f53d73 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -120,7 +120,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h index 849b08e..2499b39 100644 --- a/include/configs/adp-ag101p.h +++ b/include/configs/adp-ag101p.h @@ -87,7 +87,6 @@ /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ #define CONFIG_BAUDRATE 38400 #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE #define CONFIG_SYS_NS16550_REG_SIZE -4 diff --git a/include/configs/alt.h b/include/configs/alt.h index 6d2c242..6bd2983 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -42,7 +42,6 @@ /* FLASH */ #define CONFIG_SPI #define CONFIG_SH_QSPI -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_SPI_FLASH_QUAD #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index ed3fd34..c51db8c 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -218,7 +218,6 @@ #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_MULTI_EEPROMS /* PMIC support */ #define CONFIG_POWER_TPS65217 @@ -469,7 +468,6 @@ /* SPI flash. */ #define CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_SPEED 24000000 /* Network. */ diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 0bf0af7..4ed8e00 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -66,7 +66,6 @@ */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 9aa14f4..23457d6 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -72,7 +72,6 @@ */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 76d4032..aac550a 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -22,13 +22,10 @@ #include <asm/arch/omap.h> /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_CLK 48000000 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) #define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_CLK 48000000 #define CONFIG_SYS_NS16550_REG_SIZE (-4) -#else -#define CONFIG_OMAP_SERIAL #endif /* I2C Configuration */ @@ -36,7 +33,6 @@ #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_MULTI_EEPROMS /* Power */ #define CONFIG_POWER @@ -223,8 +219,6 @@ /* SPI */ #undef CONFIG_OMAP3_SPI -#define CONFIG_TI_QSPI -#define CONFIG_SPI_FLASH_MACRONIX #define CONFIG_CMD_SF #define CONFIG_CMD_SPI #define CONFIG_TI_SPI_MMAP diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index e87c0cb..78d8044 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -19,7 +19,6 @@ /* * UART */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #ifndef CONFIG_DM_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index fe1ef9d..e1eb700 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -49,10 +49,8 @@ /* PCI host support */ #define CONFIG_PCI -#define CONFIG_PCI_TEGRA #define CONFIG_PCI_PNP #define CONFIG_CMD_PCI -#define CONFIG_CMD_PCI_ENUM /* PCI networking support */ #define CONFIG_E1000_NO_NVM diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h index f03297e..0b97ccc 100644 --- a/include/configs/aristainetos-common.h +++ b/include/configs/aristainetos-common.h @@ -43,7 +43,6 @@ #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH_MTD -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_SPEED 20000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index 8fa5ff5..ba91d1f 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -93,7 +93,6 @@ /* DataFlash */ #ifdef CONFIG_CMD_SF #define CONFIG_ATMEL_SPI -#define CONFIG_SPI_FLASH_ATMEL #define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_ENV_SPI_MODE SPI_MODE_3 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 20a5581..45bb861 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -92,7 +92,6 @@ /* DataFlash */ #ifdef CONFIG_CMD_SF #define CONFIG_ATMEL_SPI -#define CONFIG_SPI_FLASH_ATMEL #define CONFIG_SF_DEFAULT_SPEED 30000000 #endif diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index c436fef..11d7d0c 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -100,7 +100,6 @@ #define CONFIG_GENERIC_MMC #define CONFIG_ATMEL_SPI -#define CONFIG_SPI_FLASH_ATMEL #define CONFIG_SYS_DCACHE_LINESZ 32 #define CONFIG_SYS_ICACHE_LINESZ 32 diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h index 3935811..0dcc192 100644 --- a/include/configs/atngw100mkii.h +++ b/include/configs/atngw100mkii.h @@ -120,7 +120,6 @@ #define CONFIG_GENERIC_MMC #define CONFIG_ATMEL_SPI -#define CONFIG_SPI_FLASH_ATMEL #define CONFIG_SYS_DCACHE_LINESZ 32 #define CONFIG_SYS_ICACHE_LINESZ 32 diff --git a/include/configs/axs101.h b/include/configs/axs101.h index 9a7e0dc..650d97d 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -52,7 +52,6 @@ * UART configuration */ #define CONFIG_DW_SERIAL -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 33333333 #define CONFIG_SYS_NS16550_MEM32 @@ -79,7 +78,6 @@ /* * EEPROM configuration */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR (0xA8 >> 1) #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1 diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index 6ba4aaf..5b8b22f 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -139,7 +139,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h index 9917627..943ba17 100644 --- a/include/configs/bav335x.h +++ b/include/configs/bav335x.h @@ -580,7 +580,6 @@ DEFAULT_LINUX_BOOT_ENV \ /* SPI flash. */ #define CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_SPEED 24000000 /* Network. */ diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h index 7247907..131f613 100644 --- a/include/configs/bcm28155_ap.h +++ b/include/configs/bcm28155_ap.h @@ -79,7 +79,6 @@ #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE /* Serial Info */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL /* Post pad 3 bytes after each reg addr */ #define CONFIG_SYS_NS16550_REG_SIZE (-4) diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h index c3ebb4d..305864f 100644 --- a/include/configs/bcm_ep_board.h +++ b/include/configs/bcm_ep_board.h @@ -45,7 +45,6 @@ #define CONFIG_ENV_OVERWRITE /* Serial Info */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/beaver.h b/include/configs/beaver.h index 1790f60..3bed9a4 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -51,9 +51,7 @@ #define CONFIG_SYS_MMC_ENV_PART 2 /* SPI */ -#define CONFIG_TEGRA20_SLINK #define CONFIG_TEGRA_SLINK_CTRLS 6 -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 #define CONFIG_CMD_SPI @@ -73,10 +71,8 @@ /* PCI host support */ #define CONFIG_PCI -#define CONFIG_PCI_TEGRA #define CONFIG_PCI_PNP #define CONFIG_CMD_PCI -#define CONFIG_CMD_PCI_ENUM /* PCI networking support */ #define CONFIG_RTL8169 diff --git a/include/configs/bf506f-ezkit.h b/include/configs/bf506f-ezkit.h index 64db3ac..597f1cd 100644 --- a/include/configs/bf506f-ezkit.h +++ b/include/configs/bf506f-ezkit.h @@ -73,7 +73,6 @@ #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 /* -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_CMD_SF #define CONFIG_CMD_SPI */ diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h index b7ceba4..84bb044 100644 --- a/include/configs/bf518f-ezbrd.h +++ b/include/configs/bf518f-ezbrd.h @@ -105,8 +105,6 @@ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_SST -#define CONFIG_SPI_FLASH_STMICRO /* diff --git a/include/configs/bf525-ucr2.h b/include/configs/bf525-ucr2.h index fce6fc2..d12963a 100644 --- a/include/configs/bf525-ucr2.h +++ b/include/configs/bf525-ucr2.h @@ -69,7 +69,6 @@ #define CONFIG_BFIN_SPI #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_HZ 30000000 -#define CONFIG_SPI_FLASH_EON #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SPI_MAX_HZ 30000000 diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h index a8f0979..35a2228 100644 --- a/include/configs/bf526-ezbrd.h +++ b/include/configs/bf526-ezbrd.h @@ -103,7 +103,6 @@ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_SST /* diff --git a/include/configs/bf527-ad7160-eval.h b/include/configs/bf527-ad7160-eval.h index 1c5fc9e..2f3dec5 100644 --- a/include/configs/bf527-ad7160-eval.h +++ b/include/configs/bf527-ad7160-eval.h @@ -89,7 +89,6 @@ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_STMICRO /* diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h index d23602b..aee7761 100644 --- a/include/configs/bf527-ezkit.h +++ b/include/configs/bf527-ezkit.h @@ -101,7 +101,6 @@ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_STMICRO /* diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h index c57c862..4fbdca7 100644 --- a/include/configs/bf537-minotaur.h +++ b/include/configs/bf537-minotaur.h @@ -101,7 +101,6 @@ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_STMICRO /* diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h index e922bd5..2474adb 100644 --- a/include/configs/bf537-pnav.h +++ b/include/configs/bf537-pnav.h @@ -82,7 +82,6 @@ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_STMICRO /* diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h index 90aeeec..89d2604 100644 --- a/include/configs/bf537-srv1.h +++ b/include/configs/bf537-srv1.h @@ -100,7 +100,6 @@ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_STMICRO /* diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h index f0f768a..65009c6 100644 --- a/include/configs/bf548-ezkit.h +++ b/include/configs/bf548-ezkit.h @@ -92,7 +92,6 @@ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_STMICRO /* diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h index b3c6d29..92251fc 100644 --- a/include/configs/bf561-acvilon.h +++ b/include/configs/bf561-acvilon.h @@ -114,7 +114,6 @@ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 10000000 #define CONFIG_SF_DEFAULT_SPEED 10000000 -#define CONFIG_SPI_FLASH_ATMEL /* diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index 91a84fe..9c537e0 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -278,13 +278,6 @@ * SPI Settings */ #ifdef CONFIG_SPI_FLASH_ALL -# define CONFIG_SPI_FLASH_ATMEL -# define CONFIG_SPI_FLASH_EON -# define CONFIG_SPI_FLASH_MACRONIX -# define CONFIG_SPI_FLASH_SPANSION -# define CONFIG_SPI_FLASH_SST -# define CONFIG_SPI_FLASH_STMICRO -# define CONFIG_SPI_FLASH_WINBOND #endif /* diff --git a/include/configs/bg0900.h b/include/configs/bg0900.h index 9abbc39..05c932f 100644 --- a/include/configs/bg0900.h +++ b/include/configs/bg0900.h @@ -48,7 +48,6 @@ /* SPI FLASH */ #ifdef CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SF_DEFAULT_BUS 2 #define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 40000000 diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h index 3b7a47f..60650aa 100644 --- a/include/configs/blackstamp.h +++ b/include/configs/blackstamp.h @@ -216,7 +216,6 @@ /* For the M25P64 SCK Should be Kept < 15Mhz */ #define CONFIG_ENV_SPI_MAX_HZ 15000000 #define CONFIG_SF_DEFAULT_SPEED 15000000 -#define CONFIG_SPI_FLASH_STMICRO /* * FLASH organization and environment definitions diff --git a/include/configs/blackvme.h b/include/configs/blackvme.h index 5b15e0e..16949aa 100644 --- a/include/configs/blackvme.h +++ b/include/configs/blackvme.h @@ -142,7 +142,6 @@ #define CONFIG_ENV_SPI_MAX_HZ 15000000 #define CONFIG_SF_DEFAULT_SPEED 15000000 -#define CONFIG_SPI_FLASH_STMICRO /* * Interactive command settings diff --git a/include/configs/br4.h b/include/configs/br4.h index 959f9a9..7dda472 100644 --- a/include/configs/br4.h +++ b/include/configs/br4.h @@ -82,7 +82,6 @@ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_STMICRO /* diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index c9eb63e..ffc6811 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -46,7 +46,6 @@ #include <asm/arch/omap.h> /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK 48000000 diff --git a/include/configs/calimain.h b/include/configs/calimain.h index 7f942dc..e6b2d4d 100644 --- a/include/configs/calimain.h +++ b/include/configs/calimain.h @@ -151,7 +151,6 @@ /* * Serial Driver info */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index ed790cc..e136824 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -248,7 +248,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index ce6b158..c26a25c 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -54,9 +54,7 @@ #define CONFIG_SYS_MMC_ENV_PART 2 /* SPI */ -#define CONFIG_TEGRA20_SLINK #define CONFIG_TEGRA_SLINK_CTRLS 6 -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 #define CONFIG_CMD_SPI @@ -75,10 +73,8 @@ /* PCI host support */ #define CONFIG_PCI -#define CONFIG_PCI_TEGRA #define CONFIG_PCI_PNP #define CONFIG_CMD_PCI -#define CONFIG_CMD_PCI_ENUM /* PCI networking support */ #define CONFIG_RTL8169 diff --git a/include/configs/chromebook_jerry.h b/include/configs/chromebook_jerry.h index a22b123..058325c 100644 --- a/include/configs/chromebook_jerry.h +++ b/include/configs/chromebook_jerry.h @@ -9,6 +9,7 @@ #include <configs/rk3288_common.h> +#define CONFIG_ENV_IS_NOWHERE #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 5f2f020..2dc745e 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -70,7 +70,6 @@ */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h index 1c086fc..0aefec8 100644 --- a/include/configs/cm_t3517.h +++ b/include/configs/cm_t3517.h @@ -77,7 +77,6 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index c4d3b94..d3cd38d 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -18,9 +18,7 @@ #include <asm/arch/omap.h> /* Serial support */ -#define CONFIG_OMAP_SERIAL #define CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 48000000 #define CONFIG_SYS_NS16550_COM1 0x44e09000 @@ -71,14 +69,6 @@ /* SPI Flash support */ #define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_MACRONIX -#define CONFIG_SPI_FLASH_ATMEL -#define CONFIG_SPI_FLASH_EON -#define CONFIG_SPI_FLASH_GIGADEVICE -#define CONFIG_SPI_FLASH_SPANSION -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_SST -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_TI_SPI_MMAP #define CONFIG_SPI_FLASH_BAR #define CONFIG_SF_DEFAULT_SPEED 48000000 diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 9135d6c..708c79a 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -270,7 +270,6 @@ #ifdef CONFIG_OF_CONTROL #define CONFIG_DM_SPI #define CONFIG_CMD_SPI -#define CONFIG_FSL_DSPI #endif #endif /* __CONFIG_H */ diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index 600bb83..641aa7c 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -178,7 +178,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 2 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -216,9 +215,7 @@ * eSPI - Enhanced SPI */ #define CONFIG_HARD_SPI -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 9210216..aef37dd 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -329,7 +329,6 @@ * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -415,8 +414,6 @@ /* * eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index c052e8a..ffd65d5 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -29,7 +29,6 @@ #define CONFIG_SCSI_DEV_LIST \ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA} -#define CONFIG_SPI_FLASH_SST #define CONFIG_MMC #define CONFIG_SDHCI diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h index 5d25fb1..bc7cac4 100644 --- a/include/configs/cyrus.h +++ b/include/configs/cyrus.h @@ -215,7 +215,6 @@ * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -280,7 +279,6 @@ /* * eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI /* * General PCI diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 5aa643a..63abb80 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -133,7 +133,6 @@ /* * Serial Driver info */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ @@ -142,8 +141,6 @@ #define CONFIG_BAUDRATE 115200 /* Default baud rate */ #define CONFIG_SPI -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_CMD_SF #define CONFIG_DAVINCI_SPI #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index 2251f59..944e82f 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -49,7 +49,6 @@ #define MACH_TYPE_DALMORE 4304 /* not yet in mach-types.h */ /* SPI */ -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 #define CONFIG_CMD_SPI diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index 9a0596c..3673e5e 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -60,7 +60,6 @@ /* SPI NOR flash default params, used by sf commands */ #define CONFIG_SF_DEFAULT_SPEED 1000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 -#define CONFIG_SPI_FLASH_STMICRO /* * SDIO/MMC Card Configuration diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index b3b2de9..ab6e5a5 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -56,7 +56,6 @@ /* SPI NOR flash default params, used by sf commands */ #define CONFIG_SF_DEFAULT_SPEED 1000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 -#define CONFIG_SPI_FLASH_STMICRO /* Environment in SPI NOR flash */ #define CONFIG_ENV_IS_IN_SPI_FLASH diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index cb9544b..81070b1 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -135,8 +135,6 @@ /* SPI */ #undef CONFIG_OMAP3_SPI -#define CONFIG_TI_QSPI -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #define CONFIG_CMD_SPI #define CONFIG_TI_SPI_MMAP diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h index 3f35616..0b7d89b 100644 --- a/include/configs/dreamplug.h +++ b/include/configs/dreamplug.h @@ -61,7 +61,6 @@ #ifdef CONFIG_CMD_SF #define CONFIG_HARD_SPI 1 #define CONFIG_KIRKWOOD_SPI 1 -#define CONFIG_SPI_FLASH_MACRONIX 1 #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_CS 0 #define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50 MHz */ diff --git a/include/configs/e2220-1170.h b/include/configs/e2220-1170.h index 998a69a..18a63d7 100644 --- a/include/configs/e2220-1170.h +++ b/include/configs/e2220-1170.h @@ -35,7 +35,6 @@ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) /* SPI */ -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 #define CONFIG_CMD_SPI diff --git a/include/configs/ea20.h b/include/configs/ea20.h index 53ad302..10b30c1 100644 --- a/include/configs/ea20.h +++ b/include/configs/ea20.h @@ -58,7 +58,6 @@ /* * Serial Driver info */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */ @@ -67,7 +66,6 @@ #define CONFIG_BAUDRATE 115200 /* Default baud rate */ #define CONFIG_SPI -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_DAVINCI_SPI #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index 7fb1894..1dfa721 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -88,7 +88,6 @@ * NS16550 Configuration */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK diff --git a/include/configs/efi-x86.h b/include/configs/efi-x86.h index 1c955d9..258a83f 100644 --- a/include/configs/efi-x86.h +++ b/include/configs/efi-x86.h @@ -15,7 +15,6 @@ #undef CONFIG_CMD_IMLS -#undef CONFIG_SYS_NS16550 #undef CONFIG_X86_SERIAL #undef CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_IS_NOWHERE diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index f55ba9f..90cd959 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -65,7 +65,6 @@ #define CONFIG_CMD_SF #ifdef CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_SST #define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_CS 0 diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index d6e0456..23a2935 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -59,7 +59,6 @@ /* 512kB DataFlash at NPCS0 */ #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 #define CONFIG_HAS_DATAFLASH -#define CONFIG_SPI_FLASH_ATMEL #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 #define DATAFLASH_TCSS (0x1a << 16) diff --git a/include/configs/evb_rk3036.h b/include/configs/evb_rk3036.h new file mode 100644 index 0000000..aa07889 --- /dev/null +++ b/include/configs/evb_rk3036.h @@ -0,0 +1,12 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/rk3036_common.h> + +#endif diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 5d2b4f3..9c3ea88 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -129,11 +129,8 @@ /* SPI */ #ifdef CONFIG_SPI_FLASH -#define CONFIG_EXYNOS_SPI #define CONFIG_CMD_SF #define CONFIG_CMD_SPI -#define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_SPI_FLASH_GIGADEVICE #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 50000000 #endif diff --git a/include/configs/firefly-rk3288.h b/include/configs/firefly-rk3288.h index a82adc8..4c5c4dd 100644 --- a/include/configs/firefly-rk3288.h +++ b/include/configs/firefly-rk3288.h @@ -11,4 +11,12 @@ #define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +/* SPL @ 32k for ~36k + * ENV @ 96k + * u-boot @ 128K + */ +#define CONFIG_ENV_OFFSET (96 * 1024) + #endif diff --git a/include/configs/gdppc440etx.h b/include/configs/gdppc440etx.h index b514278..8d79ea8 100644 --- a/include/configs/gdppc440etx.h +++ b/include/configs/gdppc440etx.h @@ -66,7 +66,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 2 /* Use UART1 */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() diff --git a/include/configs/gose.h b/include/configs/gose.h index c08e73a..4e29825 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -44,7 +44,6 @@ #define CONFIG_SYS_NO_FLASH #define CONFIG_SPI #define CONFIG_SH_QSPI -#define CONFIG_SPI_FLASH_SPANSION /* SH Ether */ #define CONFIG_SH_ETHER diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h index f2fd2ae..52c67d5 100644 --- a/include/configs/gplugd.h +++ b/include/configs/gplugd.h @@ -91,7 +91,6 @@ /* Flash Support */ #define CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_ATMEL /* * mv-common.h should be defined after CMD configs since it used them diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 48010eb..b7b9c78 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -70,7 +70,6 @@ #define CONFIG_MXC_SPI #define CONFIG_SPI_FLASH_MTD #define CONFIG_SPI_FLASH_BAR - #define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_CS 0 /* GPIO 3-19 (21248) */ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 84d0928..801be68 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -304,7 +304,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 2 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/icon.h b/include/configs/icon.h index bbe9b59..d9a3671 100644 --- a/include/configs/icon.h +++ b/include/configs/icon.h @@ -107,7 +107,6 @@ #define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index ecb7f10..0a5a9f1 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -323,7 +323,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/intip.h b/include/configs/intip.h index a676a20..60c9e2c 100644 --- a/include/configs/intip.h +++ b/include/configs/intip.h @@ -214,7 +214,6 @@ */ #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 diff --git a/include/configs/iocon.h b/include/configs/iocon.h index 385a644..8663c17 100644 --- a/include/configs/iocon.h +++ b/include/configs/iocon.h @@ -35,8 +35,6 @@ #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ /* new uImage format support */ -#define CONFIG_FIT -#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ #define CONFIG_FIT_DISABLE_SHA256 #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ diff --git a/include/configs/ip04.h b/include/configs/ip04.h index dd2a618..0993ffa 100644 --- a/include/configs/ip04.h +++ b/include/configs/ip04.h @@ -91,8 +91,6 @@ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_WINBOND /* diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h index 583f7b3..3c4a70c 100644 --- a/include/configs/ipam390.h +++ b/include/configs/ipam390.h @@ -133,7 +133,6 @@ /* * Serial Driver info */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */ diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index f63957a..23b2e43 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -39,7 +39,6 @@ #define CONFIG_SYS_MMC_ENV_PART 2 /* SPI */ -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 #define CONFIG_CMD_SPI @@ -59,10 +58,8 @@ /* PCI host support */ #define CONFIG_PCI -#define CONFIG_PCI_TEGRA #define CONFIG_PCI_PNP #define CONFIG_CMD_PCI -#define CONFIG_CMD_PCI_ENUM /* PCI networking support */ #define CONFIG_RTL8169 diff --git a/include/configs/katmai.h b/include/configs/katmai.h index fa72eb0..664896b 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -109,7 +109,6 @@ #define IIC0_BOOTPROM_ADDR 0x50 #define IIC0_ALT_BOOTPROM_ADDR 0x54 -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR (0x50) #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h index 3f045f2..eba7479 100644 --- a/include/configs/km/km-powerpc.h +++ b/include/configs/km/km-powerpc.h @@ -25,7 +25,6 @@ #define CONFIG_KM_COMMON_ETH_INIT /* EEprom support 24C08, 24C16, 24C64 */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 Byte write page */ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h index 30cf60c..d86b7fc 100644 --- a/include/configs/km/km83xx-common.h +++ b/include/configs/km/km83xx-common.h @@ -144,7 +144,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 54aa6fb..d1f0b12 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -99,7 +99,6 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK @@ -221,7 +220,6 @@ int get_scl(void); #define CONFIG_SYS_I2C_SOFT_SPEED 100000 /* EEprom support 24C128, 24C256 valid for environment eeprom */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 Byte write page */ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 @@ -254,7 +252,6 @@ int get_scl(void); #define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_SPI_FLASH_STMICRO /* SPI bus claim MPP configuration */ #define CONFIG_SYS_KW_SPI_MPP 0x0 diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index e163edb..6860ad2 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -244,7 +244,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -297,10 +296,7 @@ int get_scl(void); /* * eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI #define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */ -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 20000000 #define CONFIG_SF_DEFAULT_MODE 0 diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index c905cc2..caeb14d 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -44,7 +44,6 @@ #define CONFIG_SYS_NO_FLASH #define CONFIG_SPI #define CONFIG_SH_QSPI -#define CONFIG_SPI_FLASH_SPANSION /* SH Ether */ #define CONFIG_SH_ETHER diff --git a/include/configs/lager.h b/include/configs/lager.h index 1450e8f..ad8b12f 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -43,7 +43,6 @@ /* SPI */ #define CONFIG_SPI #define CONFIG_SH_QSPI -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_SYS_NO_FLASH /* SH Ether */ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 562e78f..2e8dbc7 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -375,7 +375,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_LPUART_32B_REG #else #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() @@ -414,14 +413,11 @@ unsigned long get_board_ddr_clk(void); /* SPI */ #ifdef CONFIG_QSPI_BOOT /* QSPI */ -#define CONFIG_FSL_QSPI #define QSPI0_AMBA_BASE 0x40000000 #define FSL_QSPI_FLASH_SIZE (1 << 24) #define FSL_QSPI_FLASH_NUM 2 -#define CONFIG_SPI_FLASH_SPANSION /* DSPI */ -#define CONFIG_FSL_DSPI /* DM SPI */ #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) @@ -579,14 +575,14 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_LPUART #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ - "fdt_high=0xcfffffff\0" \ - "initrd_high=0xcfffffff\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" #else #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ - "fdt_high=0xcfffffff\0" \ - "initrd_high=0xcfffffff\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" #endif diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index fdbbfc1..c12ba3a 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -270,7 +270,6 @@ #define CONFIG_LPUART_32B_REG #else #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() @@ -311,15 +310,11 @@ /* SPI */ #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) /* QSPI */ -#define CONFIG_FSL_QSPI #define QSPI0_AMBA_BASE 0x40000000 #define FSL_QSPI_FLASH_SIZE (1 << 24) #define FSL_QSPI_FLASH_NUM 2 -#define CONFIG_SPI_FLASH_STMICRO /* DSPI */ -#define CONFIG_FSL_DSPI -#define CONFIG_SPI_FLASH_ATMEL #endif /* DM SPI */ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 1f22dd3..6b9856a 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -55,7 +55,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h new file mode 100644 index 0000000..4aeb238 --- /dev/null +++ b/include/configs/ls1043aqds.h @@ -0,0 +1,387 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1043AQDS_H__ +#define __LS1043AQDS_H__ + +#include "ls1043a_common.h" + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) +#define CONFIG_SYS_TEXT_BASE 0x82000000 +#else +#define CONFIG_SYS_TEXT_BASE 0x60100000 +#endif + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_LAYERSCAPE_NS_ACCESS + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +/* Physical Memory Map */ +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_DDR_SPD +#define SPD_EEPROM_ADDRESS 0x51 +#define CONFIG_SYS_SPD_BUS_NUM 0 + +#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#ifndef CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ +#endif + +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_SYS_HAS_SERDES + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHYLIB +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_REALTEK +#define CONFIG_PHYLIB_10G +#define RGMII_PHY1_ADDR 0x1 +#define RGMII_PHY2_ADDR 0x2 +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C +#define SGMII_CARD_PORT2_PHY_ADDR 0x1D +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F +/* PHY address on QSGMII riser card on slot 1 */ +#define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4 +#define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5 +#define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6 +#define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7 +/* PHY address on QSGMII riser card on slot 2 */ +#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 +#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 +#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA +#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB +#endif + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg +#endif + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg +#endif + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg +#endif + +/* + * IFC Definitions + */ +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) + +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_TRHZ_80) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1a) | \ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0xe) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0 + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ + CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} + +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_WRITE_SWAPPED_DATA + +/* + * NAND Flash Definitions + */ +#define CONFIG_NAND_FSL_IFC + +#define CONFIG_SYS_NAND_BASE 0x7e800000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) + +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_NAND \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x7) | \ + FTIM0_NAND_TWH(0xa)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0xe) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ + FTIM2_NAND_TREH(0xa) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) +#endif + +/* + * QIXIS Definitions + */ +#define CONFIG_FSL_QIXIS + +#ifdef CONFIG_FSL_QIXIS +#define QIXIS_BASE 0x7fb00000 +#define QIXIS_BASE_PHYS QIXIS_BASE +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define QIXIS_LBMAP_SWITCH 6 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_RST_CTL_RESET 0x44 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 + +#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) +#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_NOR_MODE_AVD_NOR | \ + CSOR_NOR_TRHZ_80) + +/* + * QIXIS Timing parameters for IFC GPCM + */ +#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ + FTIM0_GPCM_TEADC(0x20) | \ + FTIM0_GPCM_TEAHC(0x10)) +#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ + FTIM2_GPCM_TCH(0x8) | \ + FTIM2_GPCM_TWP(0xf0)) +#define CONFIG_SYS_FPGA_FTIM3 0x0 +#endif + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#endif + +/* + * I2C bus multiplexer + */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 +#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ +#define I2C_RETIMER_ADDR 0x18 +#define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH_CH7301 0xC +#define I2C_MUX_CH5 0xD +#define I2C_MUX_CH7 0xF + +#define I2C_MUX_CH_VOL_MONITOR 0xa + +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_ADDR 0x40 +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 + +#define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_VID +#endif +#define CONFIG_VOL_MONITOR_IR36021_SET +#define CONFIG_VOL_MONITOR_INA220 +/* The lowest and highest voltage allowed for LS1043AQDS */ +#define VDD_MV_MIN 819 +#define VDD_MV_MAX 1212 + +/* + * Miscellaneous configurable options + */ +#define CONFIG_MISC_INIT_R +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MEMINFO +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff + +#define CONFIG_SYS_HZ 1000 + +/* + * Stack sizes + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (30 * 1024) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +/* + * Environment + */ +#define CONFIG_ENV_OVERWRITE + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SD_BOOT) +#define CONFIG_ENV_OFFSET (1024 * 1024) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE 0x20000 +#endif + +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_MII +#define CONFIG_CMDLINE_TAG + +#endif /* __LS1043AQDS_H__ */ diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 307d947..7d113a0 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -222,6 +222,16 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +/* DSPI */ +#define CONFIG_FSL_DSPI +#ifdef CONFIG_FSL_DSPI +#define CONFIG_CMD_SF +#define CONFIG_DM_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SF_DEFAULT_BUS 1 +#define CONFIG_SF_DEFAULT_CS 0 +#endif + /* * Environment */ @@ -268,4 +278,17 @@ #define CONFIG_ETHPRIME "FM1@DTSEC3" #endif +/* USB */ +#define CONFIG_HAS_FSL_XHCI_USB +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_EXT2 +#endif + #endif /* __LS1043ARDB_H__ */ diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2080a_common.h index 0011e72..2e1fe7a 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2080a_common.h @@ -11,7 +11,6 @@ #define CONFIG_REMAKE_ELF #define CONFIG_FSL_LAYERSCAPE #define CONFIG_FSL_LSCH3 -#define CONFIG_LS2085A #define CONFIG_MP #define CONFIG_GICV3 #define CONFIG_FSL_TZPC_BP147 @@ -20,7 +19,7 @@ #define CONFIG_ARM_ERRATA_828024 #define CONFIG_ARM_ERRATA_826974 -#include <asm/arch/ls2085a_stream_id.h> +#include <asm/arch/ls2080a_stream_id.h> #include <asm/arch/config.h> #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2)) #define CONFIG_SYS_HAS_SERDES @@ -80,6 +79,7 @@ #define CPU_RELEASE_ADDR secondary_boot_func #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL /* * DDR controller use 0 as the base address for binding. @@ -88,6 +88,7 @@ #define CONFIG_SYS_DP_DDR_BASE_PHY 0 #define CONFIG_DP_DDR_CTRL 2 #define CONFIG_DP_DDR_NUM_CTRLS 1 +#endif /* Generic Timer Definitions */ /* @@ -110,7 +111,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -183,8 +183,10 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 +#ifdef CONFIG_LS2085A #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 +#endif /* * Carve out a DDR region which will not be used by u-boot/Linux @@ -205,7 +207,13 @@ unsigned long long get_qixis_addr(void); #define CONFIG_PCIE3 /* PCIE controler 3 */ #define CONFIG_PCIE4 /* PCIE controler 4 */ #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ +#ifdef CONFIG_LS2080A +#define FSL_PCIE_COMPAT "fsl,ls2080a-pcie" +#endif + +#ifdef CONFIG_LS2085A #define FSL_PCIE_COMPAT "fsl,ls2085a-pcie" +#endif #define CONFIG_SYS_PCI_64BIT @@ -245,6 +253,9 @@ unsigned long long get_qixis_addr(void); #define CONFIG_DISPLAY_CPUINFO +/* Allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ diff --git a/include/configs/ls2085a_emu.h b/include/configs/ls2080a_emu.h index 2d68e1b..4a7ba24 100644 --- a/include/configs/ls2085a_emu.h +++ b/include/configs/ls2080a_emu.h @@ -7,10 +7,17 @@ #ifndef __LS2_EMU_H #define __LS2_EMU_H -#include "ls2085a_common.h" +#include "ls2080a_common.h" +#ifdef CONFIG_LS2080A +#define CONFIG_IDENT_STRING " LS2080A-EMU" +#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2080A-EMU" +#endif + +#ifdef CONFIG_LS2085A #define CONFIG_IDENT_STRING " LS2085A-EMU" #define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-EMU" +#endif #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 133333333 @@ -27,7 +34,9 @@ #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 +#endif #define CONFIG_FSL_DDR_SYNC_REFRESH diff --git a/include/configs/ls2085a_simu.h b/include/configs/ls2080a_simu.h index bd15b3d..876ee30 100644 --- a/include/configs/ls2085a_simu.h +++ b/include/configs/ls2080a_simu.h @@ -7,10 +7,17 @@ #ifndef __LS2_SIMU_H #define __LS2_SIMU_H -#include "ls2085a_common.h" +#include "ls2080a_common.h" +#ifdef CONFIG_LS2080A +#define CONFIG_IDENT_STRING " LS2080A-SIMU" +#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2080A-SIMU" +#endif + +#ifdef CONFIG_LS2085A #define CONFIG_IDENT_STRING " LS2085A-SIMU" #define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-SIMU" +#endif #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 133333333 @@ -20,7 +27,9 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 +#endif /* SMSC 91C111 ethernet configuration */ #define CONFIG_SMC91111 diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2080aqds.h index 406d0e6..54bcae9 100644 --- a/include/configs/ls2085aqds.h +++ b/include/configs/ls2080aqds.h @@ -7,7 +7,7 @@ #ifndef __LS2_QDS_H #define __LS2_QDS_H -#include "ls2085a_common.h" +#include "ls2080a_common.h" #define CONFIG_DISPLAY_BOARDINFO @@ -35,7 +35,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ #define CONFIG_DIMM_SLOTS_PER_CTLR 2 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 +#endif #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ @@ -250,19 +252,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL -/* MC firmware */ -#define CONFIG_SYS_LS_MC_FW_IN_NOR -#define CONFIG_SYS_LS_MC_FW_ADDR 0x580300000ULL - -#define CONFIG_SYS_LS_MC_DPL_IN_NOR -#define CONFIG_SYS_LS_MC_DPL_ADDR 0x580700000ULL - -#define CONFIG_SYS_LS_MC_DPC_IN_NOR -#define CONFIG_SYS_LS_MC_DPC_ADDR 0x580800000ULL - #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 -#define CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR -#define CONFIG_SYS_LS_MC_AIOP_IMG_ADDR 0x580900000ULL /* * I2C @@ -277,9 +267,6 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_FSL_DSPI #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_SST -#define CONFIG_SPI_FLASH_EON #endif /* diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2080ardb.h index f95d7b2..44a47d5 100644 --- a/include/configs/ls2085ardb.h +++ b/include/configs/ls2080ardb.h @@ -7,7 +7,7 @@ #ifndef __LS2_RDB_H #define __LS2_RDB_H -#include "ls2085a_common.h" +#include "ls2080a_common.h" #undef CONFIG_CONS_INDEX #define CONFIG_CONS_INDEX 2 @@ -37,7 +37,9 @@ unsigned long get_board_sys_clk(void); #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ #define CONFIG_DIMM_SLOTS_PER_CTLR 2 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 +#endif #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ @@ -223,19 +225,7 @@ unsigned long get_board_sys_clk(void); #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL -/* MC firmware */ -#define CONFIG_SYS_LS_MC_FW_IN_NOR -#define CONFIG_SYS_LS_MC_FW_ADDR 0x580300000ULL - -#define CONFIG_SYS_LS_MC_DPL_IN_NOR -#define CONFIG_SYS_LS_MC_DPL_ADDR 0x580700000ULL - -#define CONFIG_SYS_LS_MC_DPC_IN_NOR -#define CONFIG_SYS_LS_MC_DPC_ADDR 0x580800000ULL - #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 -#define CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR -#define CONFIG_SYS_LS_MC_AIOP_IMG_ADDR 0x580900000ULL /* * I2C @@ -250,7 +240,6 @@ unsigned long get_board_sys_clk(void); #ifdef CONFIG_FSL_DSPI #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SPI_FLASH_BAR #endif diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h index 4194a0f..19ee5bc 100644 --- a/include/configs/lsxl.h +++ b/include/configs/lsxl.h @@ -78,8 +78,6 @@ #define CONFIG_SUPPORT_RAW_INITRD /* ST M25P40 */ -#undef CONFIG_SPI_FLASH_MACRONIX -#define CONFIG_SPI_FLASH_STMICRO #undef CONFIG_ENV_SPI_MAX_HZ #define CONFIG_ENV_SPI_MAX_HZ 25000000 #undef CONFIG_SF_DEFAULT_SPEED diff --git a/include/configs/luan.h b/include/configs/luan.h index 15e4a7e..e22d0e8 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -119,7 +119,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 66d9710..69172bb 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -102,7 +102,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 2 /* Use UART1 */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 24b5489..8063a1e 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -91,7 +91,6 @@ /* EEPROM */ #ifdef CONFIG_CMD_EEPROM -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #endif @@ -124,7 +123,6 @@ /* SPI FLASH */ #ifdef CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SF_DEFAULT_BUS 2 #define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 40000000 diff --git a/include/configs/malta.h b/include/configs/malta.h index 4d3751a..3faac37 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -80,7 +80,6 @@ */ #define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (115200 * 16) diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index 3c4beeb..da49243 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -47,8 +47,6 @@ /* SPI NOR flash default params, used by sf commands */ #define CONFIG_SF_DEFAULT_SPEED 1000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_SPANSION /* Environment in SPI NOR flash */ #define CONFIG_ENV_IS_IN_SPI_FLASH diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 882f3db..4eea06d 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -78,7 +78,6 @@ */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 6f20a82..06f6ed1 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -39,7 +39,6 @@ # define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } # define CONSOLE_ARG "console=console=ttyUL0,115200\0" #elif XILINX_UART16550_BASEADDR -# define CONFIG_SYS_NS16550 1 # define CONFIG_SYS_NS16550_SERIAL # if defined(__MICROBLAZEEL__) # define CONFIG_SYS_NS16550_REG_SIZE -4 @@ -175,9 +174,7 @@ #ifdef SPIFLASH # define CONFIG_SYS_NO_FLASH 1 # define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR -# define CONFIG_XILINX_SPI 1 # define CONFIG_SPI 1 -# define CONFIG_SPI_FLASH_STMICRO 1 # define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 # define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ # define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 95d356a..1cb135b 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -29,7 +29,6 @@ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT} -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_MMC #define CONFIG_SDHCI diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index 97c614b..a8cf201 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -285,7 +285,6 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 1 /* 2 bytes per write cycle */ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* 2ms/cycle + 3ms extra */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* 2 EEPROMs (addr:50,52) */ /* * RTC configuration diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 1a627fc..a90083f 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -292,7 +292,6 @@ */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index 1ecbd35..d12d725 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -39,11 +39,6 @@ /* * NS16550 Configuration */ -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM_SERIAL) -#define CONFIG_DW_SERIAL -#endif - -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK #if !defined(CONFIG_DM_SERIAL) @@ -128,7 +123,6 @@ * Common SPI Flash configuration */ #ifdef CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_MACRONIX 1 #endif /* diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 10867a7..a52c8c9 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -129,7 +129,6 @@ #define CONFIG_SF_DEFAULT_BUS 2 #define CONFIG_SF_DEFAULT_CS 0 /* this may vary and depends on the installed chip */ -#define CONFIG_SPI_FLASH_SST #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 #endif diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 3e045ef..29d1f91 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -39,7 +39,6 @@ #define CONFIG_CMD_SF #ifdef CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_CS 0 diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index ae39503..6937924 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -171,7 +171,6 @@ #define CONFIG_CMD_SF #ifdef CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_CS 0 diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index edf7d3f..0aec296 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -182,12 +182,9 @@ #define CONFIG_CMD_TIME -#define CONFIG_FSL_QSPI #ifdef CONFIG_FSL_QSPI #define CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_SPANSION -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SYS_FSL_QSPI_LE #define CONFIG_SYS_FSL_QSPI_AHB #ifdef CONFIG_MX6SX_SABRESD_REVA diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 5779632..2712b27 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -195,11 +195,9 @@ #define CONFIG_CMD_CACHE #endif -#define CONFIG_FSL_QSPI #ifdef CONFIG_FSL_QSPI #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SPI_FLASH_BAR #define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_CS 0 diff --git a/include/configs/neo.h b/include/configs/neo.h index a60b3f7..bc01416 100644 --- a/include/configs/neo.h +++ b/include/configs/neo.h @@ -91,7 +91,6 @@ * set Linux BASE_BAUD to 403200. */ #define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 9160971..3416ce3 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -31,7 +31,6 @@ #define CONFIG_CMD_SF #ifdef CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_SST #define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_CS 0 diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index f071c59..b11e43a 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -85,7 +85,6 @@ */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK diff --git a/include/configs/nsa310s.h b/include/configs/nsa310s.h new file mode 100644 index 0000000..4510b16 --- /dev/null +++ b/include/configs/nsa310s.h @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2015 + * Gerald Kerma <dreagle@doukki.net> + * Tony Dinh <mibodhi@gmail.com> + * Luka Perkov <luka.perkov@sartura.hr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_NSA310S_H +#define _CONFIG_NSA310S_H + +/* high level configuration options */ +#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ +#define CONFIG_KW88F6192 1 /* SOC Name */ +#define CONFIG_KW88F6702 1 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* add target to build it automatically upon "make" */ +#define CONFIG_BUILD_TARGET "u-boot.kwb" + +/* compression configuration */ +#define CONFIG_BZIP2 +#define CONFIG_LZMA + +/* commands configuration */ +#define CONFIG_SYS_NO_FLASH /* declare no flash (NOR/SPI) */ +#define CONFIG_SYS_MVFS +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_IDE +#define CONFIG_CMD_MII + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* environment variables configuration */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE 0x20000 +#else +#define CONFIG_ENV_IS_NOWHERE +#endif +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_OFFSET 0xe0000 + +/* default environment variables */ +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ + "ubi part root; " \ + "ubifsmount ubi:rootfs; " \ + "ubifsload 0x800000 ${kernel}; " \ + "ubifsload 0x700000 ${fdt}; " \ + "ubifsumount; " \ + "fdt addr 0x700000; fdt resize; fdt chosen; " \ + "bootz 0x800000 - 0x700000" + +#define CONFIG_MTDPARTS \ + "mtdparts=orion_nand:" \ + "0xe0000@0x0(uboot)," \ + "0x20000@0xe0000(uboot_env)," \ + "0x100000@0x100000(second_stage_uboot)," \ + "-@0x200000(root)\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=console=ttyS0,115200\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts="CONFIG_MTDPARTS \ + "kernel=/boot/zImage\0" \ + "fdt=/boot/nsa310s.dtb\0" \ + "bootargs_root=ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs rw\0" + +/* Ethernet driver configuration */ +#ifdef CONFIG_CMD_NET +#define CONFIG_NETCONSOLE +#define CONFIG_NET_MULTI +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 1 +#define CONFIG_PHY_GIGE +#define CONFIG_RESET_PHY_R +#endif /* CONFIG_CMD_NET */ + +/* SATA driver configuration */ +#ifdef CONFIG_CMD_IDE +#define __io +#define CONFIG_IDE_PREINIT +#define CONFIG_DOS_PARTITION +#define CONFIG_MVSATA_IDE_USE_PORT0 +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#endif /* CONFIG_CMD_IDE */ + +/* RTC driver configuration */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#endif /* CONFIG_CMD_DATE */ + +#endif /* _CONFIG_NSA310S_H */ diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index 4b693e8..9464153 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -51,7 +51,6 @@ #define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE /* SPI */ -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 #define CONFIG_CMD_SPI diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index 7e7f6f2..2004d14 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -72,7 +72,6 @@ */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 4e93705..803f4b8 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -49,7 +49,7 @@ /* * NS16550 Configuration */ -#undef CONFIG_OMAP_SERIAL +#undef CONFIG_SYS_NS16550_CLK #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 80d57f4..4633fec 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -93,7 +93,6 @@ /* * Serial Driver info */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ @@ -103,8 +102,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CONFIG_SPI -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_DAVINCI_SPI #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) diff --git a/include/configs/openrisc-generic.h b/include/configs/openrisc-generic.h index d53e419..c854189 100644 --- a/include/configs/openrisc-generic.h +++ b/include/configs/openrisc-generic.h @@ -31,7 +31,6 @@ /* * SERIAL */ -# define CONFIG_SYS_NS16550 # define CONFIG_SYS_NS16550_SERIAL # define CONFIG_SYS_NS16550_REG_SIZE 1 # define CONFIG_CONS_INDEX 1 diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h index 426ec72..3da454a 100644 --- a/include/configs/ot1200.h +++ b/include/configs/ot1200.h @@ -23,10 +23,6 @@ /* SF Configs */ #define CONFIG_CMD_SF #define CONFIG_SPI -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_SPI_FLASH_MACRONIX -#define CONFIG_SPI_FLASH_SST #define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_BUS 2 #define CONFIG_SF_DEFAULT_CS 0 diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 433c409..60bedaa 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -649,7 +649,6 @@ */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -701,7 +700,6 @@ /* enable read and write access to EEPROM */ #define CONFIG_CMD_EEPROM -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 @@ -710,10 +708,8 @@ * eSPI - Enhanced SPI */ #define CONFIG_HARD_SPI -#define CONFIG_FSL_ESPI #if defined(CONFIG_SPI_FLASH) -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index d83daa0..77ba2d8 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -215,7 +215,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -262,7 +261,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* enable read and write access to EEPROM */ #define CONFIG_CMD_EEPROM -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 @@ -271,7 +269,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * eSPI - Enhanced SPI */ #define CONFIG_HARD_SPI -#define CONFIG_FSL_ESPI #if defined(CONFIG_PCI) /* diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h index f2a713d..fffe5c9 100644 --- a/include/configs/p2371-0000.h +++ b/include/configs/p2371-0000.h @@ -35,7 +35,6 @@ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) /* SPI */ -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 #define CONFIG_CMD_SPI diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h index 94f8085..7dbf422 100644 --- a/include/configs/p2371-2180.h +++ b/include/configs/p2371-2180.h @@ -35,7 +35,6 @@ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) /* SPI */ -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 #define CONFIG_CMD_SPI @@ -55,10 +54,8 @@ /* PCI host support */ #define CONFIG_PCI -#define CONFIG_PCI_TEGRA #define CONFIG_PCI_PNP #define CONFIG_CMD_PCI -#define CONFIG_CMD_PCI_ENUM /* PCI networking support */ #define CONFIG_RTL8169 diff --git a/include/configs/p2571.h b/include/configs/p2571.h index a5de411..f3357d1 100644 --- a/include/configs/p2571.h +++ b/include/configs/p2571.h @@ -36,7 +36,6 @@ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) /* SPI */ -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 #define CONFIG_CMD_SPI diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index 275e952..45c140d 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -97,7 +97,6 @@ #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \ + (8 * 1024 * 1024)) -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 24000000 @@ -115,7 +114,6 @@ #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \ 4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 } diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 046ddb8..b851bba 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -97,12 +97,10 @@ #define CONFIG_PHY_MICREL /* QSPI Configs*/ -#define CONFIG_FSL_QSPI #ifdef CONFIG_FSL_QSPI #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_STMICRO #define FSL_QSPI_FLASH_SIZE (1 << 24) #define FSL_QSPI_FLASH_NUM 2 #define CONFIG_SYS_FSL_QSPI_LE diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h index d68cded..bfc1c1e 100644 --- a/include/configs/pengwyn.h +++ b/include/configs/pengwyn.h @@ -112,7 +112,6 @@ #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_MULTI_EEPROMS /* SPL */ #define CONFIG_SPL_POWER_SUPPORT diff --git a/include/configs/porter.h b/include/configs/porter.h index 59b14e9..e34cd05 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -43,7 +43,6 @@ /* FLASH */ #define CONFIG_SPI #define CONFIG_SH_QSPI -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_SPI_FLASH_QUAD #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/pr1.h b/include/configs/pr1.h index f76e023..2e5ce75 100644 --- a/include/configs/pr1.h +++ b/include/configs/pr1.h @@ -83,7 +83,6 @@ #define CONFIG_BFIN_SPI #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_STMICRO /* diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index 9395bda..5a043d5 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -52,7 +52,6 @@ #define CONFIG_DRIVER_NE2000 #define CONFIG_DRIVER_NE2000_BASE 0xb4000300 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK 115200 diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h index 53ff802..070b5de 100644 --- a/include/configs/qemu-mips64.h +++ b/include/configs/qemu-mips64.h @@ -52,7 +52,6 @@ #define CONFIG_DRIVER_NE2000 #define CONFIG_DRIVER_NE2000_BASE 0xffffffffb4000300 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK 115200 diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index f45789f..2dfea33 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -103,7 +103,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h index e3445dd..4258dcb 100644 --- a/include/configs/qemu-x86.h +++ b/include/configs/qemu-x86.h @@ -54,7 +54,6 @@ #undef CONFIG_INTEL_ICH6_GPIO /* SPI is not supported */ -#undef CONFIG_ICH_SPI #undef CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_IS_NOWHERE diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h new file mode 100644 index 0000000..f753e68 --- /dev/null +++ b/include/configs/rk3036_common.h @@ -0,0 +1,99 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_RK3036_COMMON_H +#define __CONFIG_RK3036_COMMON_H + +#include <asm/arch/hardware.h> + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_THUMB_BUILD +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) +#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */ +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_SYS_TEXT_BASE 0x60000000 +#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 +#define CONFIG_SYS_LOAD_ADDR 0x60800800 +#define CONFIG_SPL_STACK 0x10081fff +#define CONFIG_SPL_TEXT_BASE 0x10081004 + +#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (4 << 10) +#define CONFIG_ROCKCHIP_CHIP_TAG "RK30" + +#define CONFIG_ROCKCHIP_COMMON + +/* MMC/SD IP block */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_MMC +#define CONFIG_SDHCI +#define CONFIG_DWMMC +#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_TIME + +#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CONFIG_NR_DRAM_BANKS 1 +#define SDRAM_BANK_SIZE (512UL << 20UL) + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_SPI_FLASH_GIGADEVICE +#define CONFIG_SF_DEFAULT_SPEED 20000000 + +#define CONFIG_CMD_I2C + +#ifndef CONFIG_SPL_BUILD +#include <config_distro_defaults.h> + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x60000000\0" \ + "pxefile_addr_r=0x60100000\0" \ + "fdt_addr_r=0x61f00000\0" \ + "kernel_addr_r=0x62000000\0" \ + "ramdisk_addr_r=0x64000000\0" + +/* First try to boot from SD (index 0), then eMMC (index 1 */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) + +#include <config_distro_bootcmd.h> + +/* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board, + * so limit the fdt reallocation to that */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x7fffffff\0" \ + ENV_MEM_LAYOUT_SETTINGS \ + BOOTENV +#endif + +#endif diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 36408b9..238711a 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -11,7 +11,6 @@ #define CONFIG_SYS_NO_FLASH #define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_BAUDRATE 115200 @@ -23,26 +22,25 @@ #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) -#define CONFIG_SYS_TIMER_COUNTER (TIMER7_BASE + 8) +#define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */ +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SPL_BOARD_INIT -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - #define CONFIG_SYS_TEXT_BASE 0x00100000 #define CONFIG_SYS_INIT_SP_ADDR 0x00100000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 #define CONFIG_SPL_STACK 0xff718000 #define CONFIG_SPL_TEXT_BASE 0xff704004 +#define CONFIG_ROCKCHIP_COMMON +#define CONFIG_SPL_ROCKCHIP_COMMON + /* MMC/SD IP block */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC @@ -84,7 +82,6 @@ #define CONFIG_SPI #define CONFIG_CMD_SF #define CONFIG_CMD_SPI -#define CONFIG_SPI_FLASH_GIGADEVICE #define CONFIG_SF_DEFAULT_SPEED 20000000 #define CONFIG_CMD_I2C @@ -110,6 +107,7 @@ * limit the fdt reallocation to that */ #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0x1fffffff\0" \ + "initrd_high=0x1fffffff\0" \ ENV_MEM_LAYOUT_SETTINGS \ BOOTENV #endif diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h new file mode 100644 index 0000000..ae5ba3d --- /dev/null +++ b/include/configs/sama5d2_xplained.h @@ -0,0 +1,122 @@ +/* + * Configuration file for the SAMA5D2 Xplained Board. + * + * Copyright (C) 2015 Atmel Corporation + * Wenyou Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* No NOR flash, this definition should put before common header */ +#define CONFIG_SYS_NO_FLASH + +#include "at91-sama5_common.h" + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_UART1 +#define CONFIG_USART_ID ATMEL_ID_UART1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#undef CONFIG_AT91_GPIO +#define CONFIG_ATMEL_PIO4 + +/* SerialFlash */ +#ifdef CONFIG_CMD_SF +#define CONFIG_ATMEL_SPI +#define CONFIG_ATMEL_SPI0 +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#endif + +/* NAND flash */ +#undef CONFIG_CMD_NAND + +/* MMC */ +#define CONFIG_CMD_MMC + +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_SDHCI +#define CONFIG_ATMEL_SDHCI +#define CONFIG_ATMEL_SDHCI0 +#define CONFIG_ATMEL_SDHCI1 +#define CONFIG_SUPPORT_EMMC_BOOT +#endif + +/* USB */ +#define CONFIG_CMD_USB + +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_STORAGE +#endif + +/* USB device */ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_ATMEL_USBA +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_RNDIS +#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D2 XPlained" + +#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Ethernet Hardware */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY + +/* LCD */ +/* #define CONFIG_LCD */ + +#ifdef CONFIG_LCD +#define LCD_BPP LCD_COLOR16 +#define LCD_OUTPUT_BPP 24 +#define CONFIG_LCD_LOGO +#define CONFIG_LCD_INFO +#define CONFIG_LCD_INFO_BELOW_LOGO +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_ATMEL_HLCD +#define CONFIG_ATMEL_LCD_RGB565 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#endif + +#ifdef CONFIG_SYS_USE_MMC + +/* bootstrap + u-boot + env in sd card */ +#undef FAT_ENV_DEVICE_AND_PART +#undef CONFIG_BOOTCOMMAND + +#define FAT_ENV_DEVICE_AND_PART "1" +#define CONFIG_BOOTCOMMAND "fatload mmc 1:1 0x21000000 at91-sama5d2_xplained.dtb; " \ + "fatload mmc 1:1 0x22000000 zImage; " \ + "bootz 0x22000000 - 0x21000000" +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk root=/dev/mmcblk1p2 rw rootwait" + +#endif + +#endif diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index 61b4bda..bd5f4ee 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -80,7 +80,6 @@ #ifdef CONFIG_CMD_SF #define CONFIG_ATMEL_SPI -#define CONFIG_SPI_FLASH_ATMEL #define CONFIG_SF_DEFAULT_SPEED 30000000 #endif diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index 139031d..52b4584 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -40,7 +40,6 @@ #ifdef CONFIG_CMD_SF #define CONFIG_ATMEL_SPI #define CONFIG_ATMEL_SPI0 -#define CONFIG_SPI_FLASH_ATMEL #define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 30000000 diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index cde549a..ce96a7c 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -40,7 +40,6 @@ #ifdef CONFIG_CMD_SF #define CONFIG_ATMEL_SPI #define CONFIG_ATMEL_SPI0 -#define CONFIG_SPI_FLASH_ATMEL #define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 30000000 diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 1c75c38..d3112e1 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -83,14 +83,6 @@ #define CONFIG_CMD_SF #define CONFIG_CMD_SF_TEST #define CONFIG_CMD_SPI -#define CONFIG_SPI_FLASH_ATMEL -#define CONFIG_SPI_FLASH_EON -#define CONFIG_SPI_FLASH_GIGADEVICE -#define CONFIG_SPI_FLASH_MACRONIX -#define CONFIG_SPI_FLASH_SPANSION -#define CONFIG_SPI_FLASH_SST -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_CMD_I2C #define CONFIG_I2C_EDID diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index c8b14e9..25ec7bc 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -267,7 +267,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 1c309a4..9783804 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -406,7 +406,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV) diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 0b22ce0..f88d685 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -247,7 +247,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 1f1beea..f32459b 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -151,7 +151,6 @@ */ #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h index f1f9ca8..fc9d246 100644 --- a/include/configs/sh7752evb.h +++ b/include/configs/sh7752evb.h @@ -97,8 +97,6 @@ /* SPI */ #define CONFIG_SH_SPI 1 #define CONFIG_SH_SPI_BASE 0xfe002000 -#define CONFIG_SPI_FLASH_STMICRO 1 -#define CONFIG_SPI_FLASH_MACRONIX 1 /* MMCIF */ #define CONFIG_MMC 1 diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h index d7ed65b..31dd984 100644 --- a/include/configs/sh7753evb.h +++ b/include/configs/sh7753evb.h @@ -97,8 +97,6 @@ /* SPI */ #define CONFIG_SH_SPI 1 #define CONFIG_SH_SPI_BASE 0xfe002000 -#define CONFIG_SPI_FLASH_STMICRO 1 -#define CONFIG_SPI_FLASH_MACRONIX 1 /* MMCIF */ #define CONFIG_MMC 1 diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h index cf514b6..26d70f4 100644 --- a/include/configs/sh7757lcr.h +++ b/include/configs/sh7757lcr.h @@ -98,7 +98,6 @@ /* SPI */ #define CONFIG_SH_SPI 1 #define CONFIG_SH_SPI_BASE 0xfe002000 -#define CONFIG_SPI_FLASH_STMICRO 1 /* MMCIF */ #define CONFIG_MMC 1 diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 9ab0457..eac7270 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -97,7 +97,6 @@ #define CONFIG_SPI #define CONFIG_OMAP3_SPI #define CONFIG_MTD_DEVICE -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED (75000000) @@ -113,7 +112,6 @@ #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK (48000000) diff --git a/include/configs/silk.h b/include/configs/silk.h index cd839aa..93c3d0d 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -43,7 +43,6 @@ /* FLASH */ #define CONFIG_SPI #define CONFIG_SH_QSPI -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_SPI_FLASH_QUAD #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/sniper.h b/include/configs/sniper.h index f168e8f..08046b5 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -196,15 +196,12 @@ */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_OMAP_SERIAL -#else +#ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK #endif -#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 #define CONFIG_CONS_INDEX 3 #define CONFIG_SERIAL3 3 diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h index 8364c66..ebb6ed5 100644 --- a/include/configs/socfpga_arria5_socdk.h +++ b/include/configs/socfpga_arria5_socdk.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_SOCFPGA_ARRIA5_H__ #define __CONFIG_SOCFPGA_ARRIA5_H__ -#include <asm/arch/socfpga_base_addrs.h> +#include <asm/arch/base_addr_ac5.h> /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH @@ -79,7 +79,6 @@ "bootimage=zImage\0" \ "fdt_addr=100\0" \ "fdtimage=socfpga.dtb\0" \ - "fsloadcmd=ext2load\0" \ "bootm ${loadaddr} - ${fdt_addr}\0" \ "mmcroot=/dev/mmcblk0p2\0" \ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 3374683..b3f65b6 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -88,7 +88,6 @@ #define CONFIG_CMD_SPI #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SPI_FLASH_BAR /* * The base address is configurable in QSys, each board must specify the @@ -153,8 +152,6 @@ #define CONFIG_DWMMC #define CONFIG_SOCFPGA_DWMMC #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 -#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 -#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 /* FIXME */ /* using smaller max blk cnt to avoid flooding the limited stack we have */ #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ @@ -190,10 +187,7 @@ unsigned int cm_get_l4_sp_clk_hz(void); /* * QSPI support */ -#define CONFIG_CADENCE_QSPI /* Enable multiple SPI NOR flash manufacturers */ -#define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */ -#define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */ #ifndef CONFIG_SPL_BUILD #define CONFIG_SPI_FLASH_MTD #define CONFIG_CMD_MTDPARTS @@ -213,13 +207,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* * Designware SPI support */ -#define CONFIG_DESIGNWARE_SPI #define CONFIG_CMD_SPI /* * Serial Driver */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h index 86b53e2..67bb35f 100644 --- a/include/configs/socfpga_cyclone5_socdk.h +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_SOCFPGA_CYCLONE5_H__ #define __CONFIG_SOCFPGA_CYCLONE5_H__ -#include <asm/arch/socfpga_base_addrs.h> +#include <asm/arch/base_addr_ac5.h> /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH @@ -79,7 +79,6 @@ "bootimage=zImage\0" \ "fdt_addr=100\0" \ "fdtimage=socfpga.dtb\0" \ - "fsloadcmd=ext2load\0" \ "bootm ${loadaddr} - ${fdt_addr}\0" \ "mmcroot=/dev/mmcblk0p2\0" \ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h index 3ae9b3e..16e146c 100644 --- a/include/configs/socfpga_de0_nano_soc.h +++ b/include/configs/socfpga_de0_nano_soc.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_TERASIC_DE0_H__ #define __CONFIG_TERASIC_DE0_H__ -#include <asm/arch/socfpga_base_addrs.h> +#include <asm/arch/base_addr_ac5.h> /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH @@ -74,7 +74,6 @@ "bootimage=zImage\0" \ "fdt_addr=100\0" \ "fdtimage=socfpga.dtb\0" \ - "fsloadcmd=ext2load\0" \ "bootm ${loadaddr} - ${fdt_addr}\0" \ "mmcroot=/dev/mmcblk0p2\0" \ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h index 4b270ce..d051eec 100644 --- a/include/configs/socfpga_mcvevk.h +++ b/include/configs/socfpga_mcvevk.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_DENX_MCVEVK_H__ #define __CONFIG_DENX_MCVEVK_H__ -#include <asm/arch/socfpga_base_addrs.h> +#include <asm/arch/base_addr_ac5.h> /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h index 742c5ae..5bcee05 100644 --- a/include/configs/socfpga_sockit.h +++ b/include/configs/socfpga_sockit.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_TERASIC_SOCKIT_H__ #define __CONFIG_TERASIC_SOCKIT_H__ -#include <asm/arch/socfpga_base_addrs.h> +#include <asm/arch/base_addr_ac5.h> /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH @@ -79,7 +79,6 @@ "bootimage=zImage\0" \ "fdt_addr=100\0" \ "fdtimage=socfpga.dtb\0" \ - "fsloadcmd=ext2load\0" \ "bootm ${loadaddr} - ${fdt_addr}\0" \ "mmcroot=/dev/mmcblk0p2\0" \ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h new file mode 100644 index 0000000..16a2a86 --- /dev/null +++ b/include/configs/socfpga_socrates.h @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2015 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_SOCFPGA_SOCRATES_H__ +#define __CONFIG_SOCFPGA_SOCRATES_H__ + +#include <asm/arch/base_addr_ac5.h> + +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_HW_WATCHDOG + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DFU +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +#define CONFIG_CMD_USB_MASS_STORAGE + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCrates */ + +/* Booting Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "zImage" +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) +#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Ethernet on SoC (EMAC) */ +#if defined(CONFIG_CMD_NET) + +/* PHY */ +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 +#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" +#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 +#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" +#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 + +#endif + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS +#endif +#define CONFIG_G_DNL_MANUFACTURER "EBV" + +/* Extra Environment */ +#define CONFIG_HOSTNAME socfpga_socrates + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "bootimage=zImage\0" \ + "fdt_addr=100\0" \ + "fdtimage=socfpga.dtb\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootimage};" \ + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "qspiroot=/dev/mtdblock0\0" \ + "qspirootfstype=jffs2\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ + "bootm ${loadaddr} - ${fdt_addr}\0" + +/* The rest of the configuration is shared */ +#include <configs/socfpga_common.h> + +#endif /* __CONFIG_SOCFPGA_SOCRATES_H__ */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 019cf30..f8bddca 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -198,7 +198,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/stout.h b/include/configs/stout.h index 87ea530..70fedf1 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -48,7 +48,6 @@ /* SPI */ #define CONFIG_SPI #define CONFIG_SH_QSPI -#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_SPI_FLASH_QUAD #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/strider.h b/include/configs/strider.h index fb7b7f9..8771cdc 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -308,7 +308,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 2 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index 1526d13..14c6a9e 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -78,13 +78,10 @@ + * QSPI support + */ #ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ -#define CONFIG_CADENCE_QSPI #define CONFIG_CQSPI_DECODER 0 #define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000 #define CONFIG_CMD_SPI -#define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */ -#define CONFIG_SPI_FLASH_WINBOND /* WINBOND */ #define CONFIG_CMD_SF #endif diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h index 4fc6365..113e320 100644 --- a/include/configs/sun8i.h +++ b/include/configs/sun8i.h @@ -25,6 +25,8 @@ #define CONFIG_ARMV7_PSCI_NR_CPUS 2 #elif defined(CONFIG_MACH_SUN8I_A33) #define CONFIG_ARMV7_PSCI_NR_CPUS 4 +#elif defined(CONFIG_MACH_SUN8I_H3) +#define CONFIG_ARMV7_PSCI_NR_CPUS 4 #else #error Unsupported sun8i variant #endif diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index d7d5d25..98a2c74 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -41,13 +41,10 @@ #endif /* Serial & console */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL /* ns16550 reg in the low bits of cpu reg */ #define CONFIG_SYS_NS16550_CLK 24000000 -#ifdef CONFIG_DM_SERIAL -# define CONFIG_DW_SERIAL -#else +#ifndef CONFIG_DM_SERIAL # define CONFIG_SYS_NS16550_REG_SIZE -4 # define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE # define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE @@ -335,6 +332,7 @@ extern int soft_i2c_gpio_scl; #define CONFIG_USB_GADGET_VBUS_DRAW 0 #define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_USB_FUNCTION_DFU #define CONFIG_USB_FUNCTION_FASTBOOT #define CONFIG_USB_FUNCTION_MASS_STORAGE #endif @@ -345,6 +343,11 @@ extern int soft_i2c_gpio_scl; #define CONFIG_G_DNL_MANUFACTURER "Allwinner Technology" #endif +#ifdef CONFIG_USB_FUNCTION_DFU +#define CONFIG_CMD_DFU +#define CONFIG_DFU_RAM +#endif + #ifdef CONFIG_USB_FUNCTION_FASTBOOT #define CONFIG_CMD_FASTBOOT #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR @@ -392,13 +395,26 @@ extern int soft_i2c_gpio_scl; * 32M uncompressed kernel, 16M compressed kernel, 1M fdt, * 1M script, 1M pxe and the ramdisk at the end. */ + +#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000)) +#define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000)) +#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000)) +#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000)) +#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3300000)) + #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0xa000000\0" \ - "kernel_addr_r=" __stringify(SDRAM_OFFSET(2000000)) "\0" \ - "fdt_addr_r=" __stringify(SDRAM_OFFSET(3000000)) "\0" \ - "scriptaddr=" __stringify(SDRAM_OFFSET(3100000)) "\0" \ - "pxefile_addr_r=" __stringify(SDRAM_OFFSET(3200000)) "\0" \ - "ramdisk_addr_r=" __stringify(SDRAM_OFFSET(3300000)) "\0" + "kernel_addr_r=" KERNEL_ADDR_R "\0" \ + "fdt_addr_r=" FDT_ADDR_R "\0" \ + "scriptaddr=" SCRIPT_ADDR_R "\0" \ + "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \ + "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" + +#define DFU_ALT_INFO_RAM \ + "dfu_alt_info_ram=" \ + "kernel ram " KERNEL_ADDR_R " 0x1000000;" \ + "fdt ram " FDT_ADDR_R " 0x100000;" \ + "ramdisk ram " RAMDISK_ADDR_R " 0x4000000\0" #ifdef CONFIG_MMC #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) @@ -480,6 +496,7 @@ extern int soft_i2c_gpio_scl; #define CONFIG_EXTRA_ENV_SETTINGS \ CONSOLE_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ + DFU_ALT_INFO_RAM \ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ "console=ttyS0,115200\0" \ BOOTCMD_SUNXI_COMPAT \ diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h index 502e795..7942865 100644 --- a/include/configs/t3corp.h +++ b/include/configs/t3corp.h @@ -307,7 +307,6 @@ */ #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 5754369..5788a70 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -141,7 +141,6 @@ * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 4cb7902..ec0a812 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -66,7 +66,6 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 97fe796..c1bd179 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -66,7 +66,6 @@ */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK diff --git a/include/configs/taurus.h b/include/configs/taurus.h index a5e7090..1d6f9c3 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -159,7 +159,6 @@ #define CONFIG_CMD_SPI #define CONFIG_CMD_SF #define CONFIG_ATMEL_SPI -#define CONFIG_SPI_FLASH_STMICRO #define TAURUS_SPI_MASK (1 << 4) #define TAURUS_SPI_CS_PIN AT91_PIN_PA3 diff --git a/include/configs/tb100.h b/include/configs/tb100.h index e3c41ef..8660ed4 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -35,8 +35,6 @@ /* * UART configuration */ -#define CONFIG_DW_SERIAL -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 166666666 #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h index 3297424..a9e3e66 100644 --- a/include/configs/tec-ng.h +++ b/include/configs/tec-ng.h @@ -34,9 +34,7 @@ #define CONFIG_SYS_MMC_ENV_PART 2 /* SPI */ -#define CONFIG_TEGRA20_SLINK #define CONFIG_TEGRA_SLINK_CTRLS 6 -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 #define CONFIG_CMD_SPI diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 5bb9e48..ba819c4 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -39,8 +39,7 @@ /* * NS16550 Configuration */ -#define CONFIG_TEGRA_SERIAL -#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* * Common HW configuration. diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 7fa35a1..e726040 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -145,7 +145,6 @@ #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK (48000000) diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 01d8233..ba652ca 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -108,7 +108,6 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK (48000000) diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 9697431..edbd820 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -19,14 +19,9 @@ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC -#ifndef CONFIG_SPL_BUILD -# define CONFIG_OMAP_SERIAL -#endif - #include <asm/arch/omap.h> /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550 #ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 2b2c060..de45e71 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -58,13 +58,10 @@ #define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO /* UART Configuration */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_MEM32 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE -4 -#else -#define CONFIG_KEYSTONE_SERIAL #endif #define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE #define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE @@ -77,7 +74,6 @@ #endif /* SPI Configuration */ -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_DAVINCI_SPI #define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_CLK1_6) #define CONFIG_SF_DEFAULT_SPEED 30000000 @@ -252,7 +248,7 @@ "get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ "get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0" \ "get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0" \ - "burn_uboot_spi=sf probe; sf erase 0 0x100000; " \ + "burn_uboot_spi=sf probe; sf erase 0 0x80000; " \ "sf write ${loadaddr} 0 ${filesize}\0" \ "burn_uboot_nand=nand erase 0 0x100000; " \ "nand write ${loadaddr} 0 ${filesize}\0" \ diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index e399a87..1c71cb6 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -18,10 +18,6 @@ #include <asm/arch/cpu.h> #include <asm/arch/omap.h> -#ifndef CONFIG_SPL_BUILD -# define CONFIG_OMAP_SERIAL -#endif - /* Common ARM Erratas */ #define CONFIG_ARM_ERRATA_454179 #define CONFIG_ARM_ERRATA_430973 @@ -36,11 +32,10 @@ /* NS16550 Configuration */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ -#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK #ifdef CONFIG_SPL_BUILD # define CONFIG_SYS_NS16550_SERIAL # define CONFIG_SYS_NS16550_REG_SIZE (-4) -# define CONFIG_SYS_NS16550_CLK V_NS16550_CLK #endif #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 115200} diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 741f71f..08130eb 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -57,14 +57,11 @@ /* * Hardware drivers */ -#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_CLK 48000000 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK 48000000 #define CONFIG_SYS_NS16550_COM3 UART3_BASE -#else -#define CONFIG_OMAP_SERIAL #endif #define CONFIG_CONS_INDEX 3 diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 5acbc92..2d492f8 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -50,13 +50,10 @@ /* * Hardware drivers */ -#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_CLK 48000000 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK 48000000 -#else -#define CONFIG_OMAP_SERIAL #endif /* diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 295e163..31d7757 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -48,7 +48,6 @@ #define CONFIG_MXC_SPI /* SPI Flash */ -#define CONFIG_SPI_FLASH_STMICRO #define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 0ab69e6..f5f5324 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -86,7 +86,6 @@ #define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ @@ -113,7 +112,6 @@ /* EEPROM */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_CMD_EEPROM #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_EEPROM_BUS_NUM 1 diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index 2ab5511..8761f8d 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -22,8 +22,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_TRIMSLICE /* SPI */ -#define CONFIG_TEGRA20_SFLASH -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_CMD_SPI #define CONFIG_CMD_SF @@ -58,10 +56,8 @@ /* PCI host support */ #define CONFIG_PCI -#define CONFIG_PCI_TEGRA #define CONFIG_PCI_PNP #define CONFIG_CMD_PCI -#define CONFIG_CMD_PCI_ENUM /* PCI networking support */ #define CONFIG_RTL8169 diff --git a/include/configs/tseries.h b/include/configs/tseries.h index 4265b8a..93e3454 100644 --- a/include/configs/tseries.h +++ b/include/configs/tseries.h @@ -266,7 +266,6 @@ MMCARGS #define CONFIG_OMAP3_SPI #define CONFIG_CMD_SPI #define CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SF_DEFAULT_SPEED 24000000 #define CONFIG_SPL_SPI_SUPPORT diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 1e71703..0562598 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -13,7 +13,6 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 #ifdef CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE #define CONFIG_SYS_NS16550_CLK 12288000 #define CONFIG_SYS_NS16550_REG_SIZE -2 diff --git a/include/configs/vct.h b/include/configs/vct.h index 92726c8..872f2f0 100644 --- a/include/configs/vct.h +++ b/include/configs/vct.h @@ -54,7 +54,6 @@ #endif #define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM1 UART_1_BASE #define CONFIG_CONS_INDEX 1 diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index f5df4fb..bc2d441 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -251,7 +251,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/venice2.h b/include/configs/venice2.h index a374cd9..4a0b448 100644 --- a/include/configs/venice2.h +++ b/include/configs/venice2.h @@ -36,7 +36,6 @@ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) /* SPI */ -#define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 #define CONFIG_CMD_SPI diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index a99d712..c767f90 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -35,8 +35,6 @@ #elif CONFIG_TARGET_VEXPRESS64_JUNO #define CONFIG_SYS_TEXT_BASE 0xe0000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) -#else -#error "Unknown board variant" #endif #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ @@ -108,8 +106,6 @@ #elif CONFIG_TARGET_VEXPRESS64_JUNO #define GICD_BASE (0x2C010000) #define GICC_BASE (0x2C02f000) -#else -#error "Unknown board variant" #endif #endif /* !CONFIG_GICV3 */ @@ -165,15 +161,20 @@ #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) /* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 2 #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ -#define PHYS_SDRAM_2 (0x880000000) /* Top 16MB reserved for secure world use */ #define DRAM_SEC_SIZE 0x01000000 #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE -#define PHYS_SDRAM_2_SIZE 0x180000000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_2 (0x880000000) +#define PHYS_SDRAM_2_SIZE 0x180000000 +#else +#define CONFIG_NR_DRAM_BANKS 1 +#endif + /* Enable memtest */ #define CONFIG_CMD_MEMTEST #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 @@ -273,14 +274,8 @@ #define CONFIG_BOOTDELAY 1 -#else -#error "Unknown board variant" #endif -/* Do not preserve environment */ -#define CONFIG_ENV_IS_NOWHERE 1 -#define CONFIG_ENV_SIZE 0x1000 - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ @@ -291,28 +286,35 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_SYS_MAXARGS 64 /* max command args */ -/* Flash memory is available on the Juno board only */ -#ifndef CONFIG_TARGET_VEXPRESS64_JUNO -#define CONFIG_SYS_NO_FLASH +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO +#define CONFIG_SYS_FLASH_BASE 0x08000000 +/* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */ +#define CONFIG_SYS_MAX_FLASH_SECT 259 +/* Store environment at top of flash in the same location as blank.img */ +/* in the Juno firmware. */ +#define CONFIG_ENV_ADDR 0x0BFC0000 +#define CONFIG_ENV_SECT_SIZE 0x00010000 #else +#define CONFIG_SYS_FLASH_BASE 0x0C000000 +/* 256 x 256KiB sectors */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 +/* Store environment at top of flash */ +#define CONFIG_ENV_ADDR 0x0FFC0000 +#define CONFIG_ENV_SECT_SIZE 0x00040000 +#endif + #define CONFIG_CMD_ARMFLASH #define CONFIG_SYS_FLASH_CFI 1 #define CONFIG_FLASH_CFI_DRIVER 1 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT -#define CONFIG_SYS_FLASH_BASE 0x08000000 -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MiB */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* Timeout values in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ - -/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */ -#define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ #define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ +#define FLASH_MAX_SECTOR_SIZE 0x00040000 +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_IS_IN_FLASH 1 -#endif #endif /* __VEXPRESS_AEMV8A_H */ diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index a3ea2e0..34df6f0 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -96,11 +96,9 @@ #define CONFIG_PHY_MICREL /* QSPI Configs*/ -#define CONFIG_FSL_QSPI #ifdef CONFIG_FSL_QSPI #define CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_SPANSION #define FSL_QSPI_FLASH_SIZE (1 << 24) #define FSL_QSPI_FLASH_NUM 2 #define CONFIG_SYS_FSL_QSPI_LE diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 7f5f089..714ebee 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -200,7 +200,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/walnut.h b/include/configs/walnut.h index 8b803a2..dd6b519 100644 --- a/include/configs/walnut.h +++ b/include/configs/walnut.h @@ -80,7 +80,6 @@ */ #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 3a18f69..70ec103 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -59,7 +59,6 @@ /*----------------------------------------------------------------------- * Serial Configuration */ -#define CONFIG_SYS_NS16550 #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \ 9600, 19200, 38400, 115200} @@ -153,8 +152,6 @@ * CPU Features */ -#define CONFIG_SYS_X86_TSC_TIMER - #define CONFIG_SYS_STACK_SIZE (32 * 1024) #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MALLOC_LEN 0x200000 @@ -165,10 +162,6 @@ /*----------------------------------------------------------------------- * FLASH configuration */ -#define CONFIG_ICH_SPI -#define CONFIG_SPI_FLASH_MACRONIX -#define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_SPI_FLASH_GIGADEVICE #define CONFIG_SYS_NO_FLASH #define CONFIG_CMD_SF #define CONFIG_CMD_SF_TEST diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h index 1abd0ef..eb400d0 100644 --- a/include/configs/xilinx-ppc.h +++ b/include/configs/xilinx-ppc.h @@ -109,7 +109,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } #else #ifdef XPAR_UARTNS550_0_BASEADDR -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 4 #define CONFIG_CONS_INDEX 1 diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index e990512..6b8b9f8 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -84,7 +84,6 @@ /* SPI */ #ifdef CONFIG_ZYNQ_SPI -# define CONFIG_SPI_FLASH_SST # define CONFIG_CMD_SF #endif diff --git a/include/configs/xpedite1000.h b/include/configs/xpedite1000.h index 005f149..5bc926f 100644 --- a/include/configs/xpedite1000.h +++ b/include/configs/xpedite1000.h @@ -97,7 +97,6 @@ extern void out32(unsigned int, unsigned long); * Serial Port */ #define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h index 3e09635..96b357b 100644 --- a/include/configs/xpedite517x.h +++ b/include/configs/xpedite517x.h @@ -214,7 +214,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h index 39bdb88..b2d6a1e 100644 --- a/include/configs/xpedite520x.h +++ b/include/configs/xpedite520x.h @@ -177,7 +177,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index c687555..8b4d4d9 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -213,7 +213,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index f971f8b..c7e25d9 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -204,7 +204,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * Serial Port */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 8508a80..0cffab8 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -122,7 +122,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index d10f1dd..fa83ac7 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -67,7 +67,6 @@ /* SPI */ #ifdef CONFIG_ZYNQ_SPI -# define CONFIG_SPI_FLASH_SST # define CONFIG_CMD_SF #endif @@ -75,9 +74,6 @@ #ifdef CONFIG_ZYNQ_QSPI # define CONFIG_SF_DEFAULT_SPEED 30000000 # define CONFIG_SPI_FLASH_ISSI -# define CONFIG_SPI_FLASH_SPANSION -# define CONFIG_SPI_FLASH_STMICRO -# define CONFIG_SPI_FLASH_WINBOND # define CONFIG_SPI_FLASH_BAR # define CONFIG_CMD_SF #endif diff --git a/include/configs/zynq_zc770.h b/include/configs/zynq_zc770.h index 63224dd..dbc829e 100644 --- a/include/configs/zynq_zc770.h +++ b/include/configs/zynq_zc770.h @@ -18,7 +18,6 @@ # define CONFIG_ZYNQ_GEM0 # define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 # define CONFIG_ZYNQ_SDHCI0 -# define CONFIG_ZYNQ_SPI #elif defined(CONFIG_ZC770_XM011) diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h new file mode 100644 index 0000000..87acf4a --- /dev/null +++ b/include/dt-bindings/clock/rk3036-cru.h @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2014 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_GPLL 3 +#define ARMCLK 4 + +/* sclk gates (special clocks) */ +#define SCLK_GPU 64 +#define SCLK_SPI 65 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_NANDC 76 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_I2S 82 +#define SCLK_SPDIF 83 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_OTGPHY0 93 +#define SCLK_LCDC 100 +#define SCLK_HDMI 109 +#define SCLK_HEVC 111 +#define SCLK_I2S_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO_SAMPLE 119 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_PVTM_CORE 123 +#define SCLK_PVTM_GPU 124 +#define SCLK_PVTM_VIDEO 125 +#define SCLK_MAC 151 +#define SCLK_MACREF 152 +#define SCLK_SFC 160 + +#define DCLK_LCDC 190 + +/* aclk gates */ +#define ACLK_DMAC2 194 +#define ACLK_LCDC 197 +#define ACLK_VIO 203 +#define ACLK_VCODEC 208 +#define ACLK_CPU 209 +#define ACLK_PERI 210 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GRF 329 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_SPI 338 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_PWM 350 +#define PCLK_TIMER 353 +#define PCLK_HDMI 360 +#define PCLK_CPU 362 +#define PCLK_PERI 363 +#define PCLK_DDRUPCTL 364 +#define PCLK_WDT 368 + +/* hclk gates */ +#define HCLK_OTG0 449 +#define HCLK_OTG1 450 +#define HCLK_NANDC 453 +#define HCLK_SDMMC 456 +#define HCLK_SDIO 457 +#define HCLK_EMMC 459 +#define HCLK_I2S 462 +#define HCLK_LCDC 465 +#define HCLK_ROM 467 +#define HCLK_VIO_BUS 472 +#define HCLK_VCODEC 476 +#define HCLK_CPU 477 +#define HCLK_PERI 478 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_CORE0 0 +#define SRST_CORE1 1 +#define SRST_CORE0_DBG 4 +#define SRST_CORE1_DBG 5 +#define SRST_CORE0_POR 8 +#define SRST_CORE1_POR 9 +#define SRST_L2C 12 +#define SRST_TOPDBG 13 +#define SRST_STRC_SYS_A 14 +#define SRST_PD_CORE_NIU 15 + +#define SRST_TIMER2 16 +#define SRST_CPUSYS_H 17 +#define SRST_AHB2APB_H 19 +#define SRST_TIMER3 20 +#define SRST_INTMEM 21 +#define SRST_ROM 22 +#define SRST_PERI_NIU 23 +#define SRST_I2S 24 +#define SRST_DDR_PLL 25 +#define SRST_GPU_DLL 26 +#define SRST_TIMER0 27 +#define SRST_TIMER1 28 +#define SRST_CORE_DLL 29 +#define SRST_EFUSE_P 30 +#define SRST_ACODEC_P 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_UART0 39 +#define SRST_UART1 40 +#define SRST_UART2 41 +#define SRST_I2C0 43 +#define SRST_I2C1 44 +#define SRST_I2C2 45 +#define SRST_SFC 47 + +#define SRST_PWM0 48 +#define SRST_DAP 51 +#define SRST_DAP_SYS 52 +#define SRST_GRF 55 +#define SRST_PERIPHSYS_A 57 +#define SRST_PERIPHSYS_H 58 +#define SRST_PERIPHSYS_P 59 +#define SRST_CPU_PERI 61 +#define SRST_EMEM_PERI 62 +#define SRST_USB_PERI 63 + +#define SRST_DMA2 64 +#define SRST_MAC 66 +#define SRST_NANDC 68 +#define SRST_USBOTG0 69 +#define SRST_OTGC0 71 +#define SRST_USBOTG1 72 +#define SRST_OTGC1 74 +#define SRST_DDRMSCH 79 + +#define SRST_MMC0 81 +#define SRST_SDIO 82 +#define SRST_EMMC 83 +#define SRST_SPI0 84 +#define SRST_WDT 86 +#define SRST_DDRPHY 88 +#define SRST_DDRPHY_P 89 +#define SRST_DDRCTRL 90 +#define SRST_DDRCTRL_P 91 + +#define SRST_HDMI_P 96 +#define SRST_VIO_BUS_H 99 +#define SRST_UTMI0 103 +#define SRST_UTMI1 104 +#define SRST_USBPOR 105 + +#define SRST_VCODEC_A 112 +#define SRST_VCODEC_H 113 +#define SRST_VIO1_A 114 +#define SRST_HEVC 115 +#define SRST_VCODEC_NIU_A 116 +#define SRST_LCDC1_A 117 +#define SRST_LCDC1_H 118 +#define SRST_LCDC1_D 119 +#define SRST_GPU 120 +#define SRST_GPU_NIU_A 122 + +#define SRST_DBG_P 131 + +#endif diff --git a/include/dwmmc.h b/include/dwmmc.h index 25cf42c..05b0817 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -105,6 +105,8 @@ /* Status Register */ #define DWMCI_BUSY (1 << 9) +#define DWMCI_FIFO_MASK 0x1ff +#define DWMCI_FIFO_SHIFT 17 /* FIFOTH Register */ #define MSIZE(x) ((x) << 28) @@ -180,6 +182,9 @@ struct dwmci_host { unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq); struct mmc_config cfg; + + /* use fifo mode to read and write data */ + bool fifo_mode; }; struct dwmci_idmac { diff --git a/include/fdtdec.h b/include/fdtdec.h index 79826d7..7fe657d 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -128,10 +128,6 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */ COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */ COMPAT_NVIDIA_TEGRA20_SDMMC, /* Tegra20 SDMMC controller */ - COMPAT_NVIDIA_TEGRA124_PCIE, /* Tegra 124 PCIe controller */ - COMPAT_NVIDIA_TEGRA210_PCIE, /* Tegra 210 PCIe controller */ - COMPAT_NVIDIA_TEGRA30_PCIE, /* Tegra 30 PCIe controller */ - COMPAT_NVIDIA_TEGRA20_PCIE, /* Tegra 20 PCIe controller */ COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL, /* Tegra124 XUSB pad controller */ COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL, diff --git a/include/flash.h b/include/flash.h index 13e0384..f53ace7 100644 --- a/include/flash.h +++ b/include/flash.h @@ -8,7 +8,10 @@ #ifndef _FLASH_H_ #define _FLASH_H_ -#ifndef CONFIG_SYS_NO_FLASH +#ifndef CONFIG_SYS_MAX_FLASH_SECT +#define CONFIG_SYS_MAX_FLASH_SECT 512 +#endif + /*----------------------------------------------------------------------- * FLASH Info: contains chip specific data, per FLASH bank */ @@ -503,6 +506,4 @@ extern flash_info_t *flash_get_info(ulong base); #define FLASH_ERASE_TIMEOUT 120000 /* timeout for erasing in ms */ #define FLASH_WRITE_TIMEOUT 500 /* timeout for writes in ms */ -#endif /* !CONFIG_SYS_NO_FLASH */ - #endif /* _FLASH_H_ */ diff --git a/include/fsl-mc/fsl_dpbp.h b/include/fsl-mc/fsl_dpbp.h index 3cdc94e..92c5437 100644 --- a/include/fsl-mc/fsl_dpbp.h +++ b/include/fsl-mc/fsl_dpbp.h @@ -20,6 +20,8 @@ /* Command IDs */ #define DPBP_CMDID_CLOSE 0x800 #define DPBP_CMDID_OPEN 0x804 +#define DPBP_CMDID_CREATE 0x904 +#define DPBP_CMDID_DESTROY 0x900 #define DPBP_CMDID_ENABLE 0x002 #define DPBP_CMDID_DISABLE 0x003 @@ -83,6 +85,52 @@ int dpbp_close(struct fsl_mc_io *mc_io, uint16_t token); /** + * struct dpbp_cfg - Structure representing DPBP configuration + * @options: place holder + */ +struct dpbp_cfg { + uint32_t options; +}; + +/** + * dpbp_create() - Create the DPBP object. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @cfg: Configuration structure + * @token: Returned token; use in subsequent API calls + * + * Create the DPBP object, allocate required resources and + * perform required initialization. + * + * The object can be created either by declaring it in the + * DPL file, or by calling this function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent calls to + * this specific object. For objects that are created using the + * DPL file, call dpbp_open function to get an authentication + * token first. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_create(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + const struct dpbp_cfg *cfg, + uint16_t *token); + +/** + * dpbp_destroy() - Destroy the DPBP object and release all its resources. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPBP object + * + * Return: '0' on Success; error code otherwise. + */ +int dpbp_destroy(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token); + +/** * dpbp_enable() - Enable the DPBP. * @mc_io: Pointer to MC portal's I/O object * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' diff --git a/include/fsl-mc/fsl_dpio.h b/include/fsl-mc/fsl_dpio.h index 9e83a2e..0bc0b44 100644 --- a/include/fsl-mc/fsl_dpio.h +++ b/include/fsl-mc/fsl_dpio.h @@ -14,6 +14,8 @@ /* Command IDs */ #define DPIO_CMDID_CLOSE 0x800 #define DPIO_CMDID_OPEN 0x803 +#define DPIO_CMDID_CREATE 0x903 +#define DPIO_CMDID_DESTROY 0x900 #define DPIO_CMDID_ENABLE 0x002 #define DPIO_CMDID_DISABLE 0x003 @@ -25,6 +27,14 @@ MC_CMD_OP(cmd, 0, 0, 32, int, dpio_id) /* cmd, param, offset, width, type, arg_name */ +#define DPIO_CMD_CREATE(cmd, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 16, 2, enum dpio_channel_mode, \ + cfg->channel_mode);\ + MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->num_priorities);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ #define DPIO_RSP_GET_ATTR(cmd, attr) \ do { \ MC_RSP_OP(cmd, 0, 0, 32, int, attr->id);\ @@ -90,6 +100,56 @@ enum dpio_channel_mode { }; /** + * struct dpio_cfg - Structure representing DPIO configuration + * @channel_mode: Notification channel mode + * @num_priorities: Number of priorities for the notification channel (1-8); + * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL' + */ +struct dpio_cfg { + enum dpio_channel_mode channel_mode; + uint8_t num_priorities; +}; + +/** + * dpio_create() - Create the DPIO object. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @cfg: Configuration structure + * @token: Returned token; use in subsequent API calls + * + * Create the DPIO object, allocate required resources and + * perform required initialization. + * + * The object can be created either by declaring it in the + * DPL file, or by calling this function. + * + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent calls to + * this specific object. For objects that are created using the + * DPL file, call dpio_open() function to get an authentication + * token first. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpio_create(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + const struct dpio_cfg *cfg, + uint16_t *token); + +/** + * dpio_destroy() - Destroy the DPIO object and release all its resources. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPIO object + * + * Return: '0' on Success; Error code otherwise + */ +int dpio_destroy(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token); + +/** * dpio_enable() - Enable the DPIO, allow I/O portal operations. * @mc_io: Pointer to MC portal's I/O object * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' diff --git a/include/fsl-mc/fsl_dpmac.h b/include/fsl-mc/fsl_dpmac.h new file mode 100644 index 0000000..24f0b48 --- /dev/null +++ b/include/fsl-mc/fsl_dpmac.h @@ -0,0 +1,468 @@ +/* + * Freescale Layerscape MC I/O wrapper + * + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Author: Prabhakar Kushwaha <prabhakar@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_DPMAC_H +#define __FSL_DPMAC_H + +/* DPMAC Version */ +#define DPMAC_VER_MAJOR 3 +#define DPMAC_VER_MINOR 1 + +/* Command IDs */ +#define DPMAC_CMDID_CLOSE 0x800 +#define DPMAC_CMDID_OPEN 0x80c +#define DPMAC_CMDID_CREATE 0x90c +#define DPMAC_CMDID_DESTROY 0x900 + +#define DPMAC_CMDID_GET_ATTR 0x004 +#define DPMAC_CMDID_RESET 0x005 + +#define DPMAC_CMDID_MDIO_READ 0x0c0 +#define DPMAC_CMDID_MDIO_WRITE 0x0c1 +#define DPMAC_CMDID_GET_LINK_CFG 0x0c2 +#define DPMAC_CMDID_SET_LINK_STATE 0x0c3 +#define DPMAC_CMDID_GET_COUNTER 0x0c4 + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_CMD_CREATE(cmd, cfg) \ + MC_CMD_OP(cmd, 0, 0, 32, int, cfg->mac_id) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_CMD_OPEN(cmd, dpmac_id) \ + MC_CMD_OP(cmd, 0, 0, 32, int, dpmac_id) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_RSP_GET_ATTRIBUTES(cmd, attr) \ +do { \ + MC_RSP_OP(cmd, 0, 0, 32, int, attr->phy_id);\ + MC_RSP_OP(cmd, 0, 32, 32, int, attr->id);\ + MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->version.major);\ + MC_RSP_OP(cmd, 1, 16, 16, uint16_t, attr->version.minor);\ + MC_RSP_OP(cmd, 1, 32, 8, enum dpmac_link_type, attr->link_type);\ + MC_RSP_OP(cmd, 1, 40, 8, enum dpmac_eth_if, attr->eth_if);\ + MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->max_rate);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_CMD_MDIO_READ(cmd, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->phy_addr); \ + MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->reg); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_RSP_MDIO_READ(cmd, data) \ + MC_RSP_OP(cmd, 0, 16, 16, uint16_t, data) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_CMD_MDIO_WRITE(cmd, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->phy_addr); \ + MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->reg); \ + MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->data); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_RSP_GET_LINK_CFG(cmd, cfg) \ +do { \ + MC_RSP_OP(cmd, 0, 0, 64, uint64_t, cfg->options); \ + MC_RSP_OP(cmd, 1, 0, 32, uint32_t, cfg->rate); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_CMD_SET_LINK_STATE(cmd, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 64, uint64_t, cfg->options); \ + MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->rate); \ + MC_CMD_OP(cmd, 2, 0, 1, int, cfg->up); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_CMD_GET_COUNTER(cmd, type) \ + MC_CMD_OP(cmd, 0, 0, 8, enum dpmac_counter, type) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMAC_RSP_GET_COUNTER(cmd, counter) \ + MC_RSP_OP(cmd, 1, 0, 64, uint64_t, counter) + +/* Data Path MAC API + * Contains initialization APIs and runtime control APIs for DPMAC + */ + +struct fsl_mc_io; + +/** + * dpmac_open() - Open a control session for the specified object. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @dpmac_id: DPMAC unique ID + * @token: Returned token; use in subsequent API calls + * + * This function can be used to open a control session for an + * already created object; an object may have been declared in + * the DPL or by calling the dpmac_create function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent commands for + * this specific object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_open(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + int dpmac_id, + uint16_t *token); + +/** + * dpmac_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * + * After this function is called, no further operations are + * allowed on the object without opening a new control session. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_close(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token); + +/** + * enum dpmac_link_type - DPMAC link type + * @DPMAC_LINK_TYPE_NONE: No link + * @DPMAC_LINK_TYPE_FIXED: Link is fixed type + * @DPMAC_LINK_TYPE_PHY: Link by PHY ID + * @DPMAC_LINK_TYPE_BACKPLANE: Backplane link type + */ +enum dpmac_link_type { + DPMAC_LINK_TYPE_NONE, + DPMAC_LINK_TYPE_FIXED, + DPMAC_LINK_TYPE_PHY, + DPMAC_LINK_TYPE_BACKPLANE +}; + +/** + * enum dpmac_eth_if - DPMAC Ethrnet interface + * @DPMAC_ETH_IF_MII: MII interface + * @DPMAC_ETH_IF_RMII: RMII interface + * @DPMAC_ETH_IF_SMII: SMII interface + * @DPMAC_ETH_IF_GMII: GMII interface + * @DPMAC_ETH_IF_RGMII: RGMII interface + * @DPMAC_ETH_IF_SGMII: SGMII interface + * @DPMAC_ETH_IF_QSGMII: QSGMII interface + * @DPMAC_ETH_IF_XAUI: XAUI interface + * @DPMAC_ETH_IF_XFI: XFI interface + */ +enum dpmac_eth_if { + DPMAC_ETH_IF_MII, + DPMAC_ETH_IF_RMII, + DPMAC_ETH_IF_SMII, + DPMAC_ETH_IF_GMII, + DPMAC_ETH_IF_RGMII, + DPMAC_ETH_IF_SGMII, + DPMAC_ETH_IF_QSGMII, + DPMAC_ETH_IF_XAUI, + DPMAC_ETH_IF_XFI +}; + +/** + * struct dpmac_cfg - Structure representing DPMAC configuration + * @mac_id: Represents the Hardware MAC ID; in case of multiple WRIOP, + * the MAC IDs are continuous. + * For example: 2 WRIOPs, 16 MACs in each: + * MAC IDs for the 1st WRIOP: 1-16, + * MAC IDs for the 2nd WRIOP: 17-32. + */ +struct dpmac_cfg { + int mac_id; +}; + +/** + * dpmac_create() - Create the DPMAC object. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @cfg: Configuration structure + * @token: Returned token; use in subsequent API calls + * + * Create the DPMAC object, allocate required resources and + * perform required initialization. + * + * The object can be created either by declaring it in the + * DPL file, or by calling this function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent calls to + * this specific object. For objects that are created using the + * DPL file, call dpmac_open function to get an authentication + * token first. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_create(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + const struct dpmac_cfg *cfg, + uint16_t *token); + +/** + * dpmac_destroy() - Destroy the DPMAC object and release all its resources. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * + * Return: '0' on Success; error code otherwise. + */ +int dpmac_destroy(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token); + +/* DPMAC IRQ Index and Events */ + +/* IRQ index */ +#define DPMAC_IRQ_INDEX 0 +/* IRQ event - indicates a change in link state */ +#define DPMAC_IRQ_EVENT_LINK_CFG_REQ 0x00000001 +/* irq event - Indicates that the link state changed */ +#define DPMAC_IRQ_EVENT_LINK_CHANGED 0x00000002 + +/** + * struct dpmac_attr - Structure representing DPMAC attributes + * @id: DPMAC object ID + * @phy_id: PHY ID + * @link_type: link type + * @eth_if: Ethernet interface + * @max_rate: Maximum supported rate - in Mbps + * @version: DPMAC version + */ +struct dpmac_attr { + int id; + int phy_id; + enum dpmac_link_type link_type; + enum dpmac_eth_if eth_if; + uint32_t max_rate; + /** + * struct version - Structure representing DPMAC version + * @major: DPMAC major version + * @minor: DPMAC minor version + */ + struct { + uint16_t major; + uint16_t minor; + } version; +}; + +/** + * dpmac_get_attributes - Retrieve DPMAC attributes. + * + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * @attr: Returned object's attributes + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_get_attributes(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpmac_attr *attr); + +/** + * struct dpmac_mdio_cfg - DPMAC MDIO read/write parameters + * @phy_addr: MDIO device address + * @reg: Address of the register within the Clause 45 PHY device from which data + * is to be read + * @data: Data read/write from/to MDIO + */ +struct dpmac_mdio_cfg { + uint8_t phy_addr; + uint8_t reg; + uint16_t data; +}; + +/** + * dpmac_mdio_read() - Perform MDIO read transaction + * @mc_io: Pointer to opaque I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * @cfg: Structure with MDIO transaction parameters + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_mdio_read(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpmac_mdio_cfg *cfg); + +/** + * dpmac_mdio_write() - Perform MDIO write transaction + * @mc_io: Pointer to opaque I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * @cfg: Structure with MDIO transaction parameters + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_mdio_write(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpmac_mdio_cfg *cfg); + +/* DPMAC link configuration/state options */ + +/* Enable auto-negotiation */ +#define DPMAC_LINK_OPT_AUTONEG 0x0000000000000001ULL +/* Enable half-duplex mode */ +#define DPMAC_LINK_OPT_HALF_DUPLEX 0x0000000000000002ULL +/* Enable pause frames */ +#define DPMAC_LINK_OPT_PAUSE 0x0000000000000004ULL +/* Enable a-symmetric pause frames */ +#define DPMAC_LINK_OPT_ASYM_PAUSE 0x0000000000000008ULL + +/** + * struct dpmac_link_cfg - Structure representing DPMAC link configuration + * @rate: Link's rate - in Mbps + * @options: Enable/Disable DPMAC link cfg features (bitmap) + */ +struct dpmac_link_cfg { + uint32_t rate; + uint64_t options; +}; + +/** + * dpmac_get_link_cfg() - Get Ethernet link configuration + * @mc_io: Pointer to opaque I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * @cfg: Returned structure with the link configuration + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_get_link_cfg(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpmac_link_cfg *cfg); + +/** + * struct dpmac_link_state - DPMAC link configuration request + * @rate: Rate in Mbps + * @options: Enable/Disable DPMAC link cfg features (bitmap) + * @up: Link state + */ +struct dpmac_link_state { + uint32_t rate; + uint64_t options; + int up; +}; + +/** + * dpmac_set_link_state() - Set the Ethernet link status + * @mc_io: Pointer to opaque I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * @link_state: Link state configuration + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_set_link_state(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpmac_link_state *link_state); + +/** + * enum dpni_counter - DPNI counter types + * @DPMAC_CNT_ING_FRAME_64: counts 64-octet frame, good or bad. + * @DPMAC_CNT_ING_FRAME_127: counts 65- to 127-octet frame, good or bad. + * @DPMAC_CNT_ING_FRAME_255: counts 128- to 255-octet frame, good or bad. + * @DPMAC_CNT_ING_FRAME_511: counts 256- to 511-octet frame, good or bad. + * @DPMAC_CNT_ING_FRAME_1023: counts 512- to 1023-octet frame, good or bad. + * @DPMAC_CNT_ING_FRAME_1518: counts 1024- to 1518-octet frame, good or bad. + * @DPMAC_CNT_ING_FRAME_1519_MAX: counts 1519-octet frame and larger + * (up to max frame length specified), + * good or bad. + * @DPMAC_CNT_ING_FRAG: counts packet which is shorter than 64 octets received + * with a wrong CRC + * @DPMAC_CNT_ING_JABBER: counts packet longer than the maximum frame length + * specified, with a bad frame check sequence. + * @DPMAC_CNT_ING_FRAME_DISCARD: counts dropped packet due to internal errors. + * Occurs when a receive FIFO overflows. + * Includes also packets truncated as a result of + * the receive FIFO overflow. + * @DPMAC_CNT_ING_ALIGN_ERR: counts frame with an alignment error + * (optional used for wrong SFD) + * @DPMAC_CNT_EGR_UNDERSIZED: counts packet transmitted that was less than 64 + * octets long with a good CRC. + * @DPMAC_CNT_ING_OVERSIZED: counts packet longer than the maximum frame length + * specified, with a good frame check sequence. + * @DPMAC_CNT_ING_VALID_PAUSE_FRAME: counts valid pause frame (regular and PFC). + * @DPMAC_CNT_EGR_VALID_PAUSE_FRAME: counts valid pause frame transmitted + * (regular and PFC). + * @DPMAC_CNT_ING_BYTE: counts octet received except preamble for all valid + * frames and valid pause frames. + * @DPMAC_CNT_ING_MCAST_FRAME: counts received multicast frame + * @DPMAC_CNT_ING_BCAST_FRAME: counts received broadcast frame + * @DPMAC_CNT_ING_ALL_FRAME: counts each good or bad packet received. + * @DPMAC_CNT_ING_UCAST_FRAME: counts received unicast frame + * @DPMAC_CNT_ING_ERR_FRAME: counts frame received with an error + * (except for undersized/fragment frame) + * @DPMAC_CNT_EGR_BYTE: counts octet transmitted except preamble for all valid + * frames and valid pause frames transmitted. + * @DPMAC_CNT_EGR_MCAST_FRAME: counts transmitted multicast frame + * @DPMAC_CNT_EGR_BCAST_FRAME: counts transmitted broadcast frame + * @DPMAC_CNT_EGR_UCAST_FRAME: counts transmitted unicast frame + * @DPMAC_CNT_EGR_ERR_FRAME: counts frame transmitted with an error + * @DPMAC_CNT_ING_GOOD_FRAME: counts frame received without error, including + * pause frames. + */ +enum dpmac_counter { + DPMAC_CNT_ING_FRAME_64, + DPMAC_CNT_ING_FRAME_127, + DPMAC_CNT_ING_FRAME_255, + DPMAC_CNT_ING_FRAME_511, + DPMAC_CNT_ING_FRAME_1023, + DPMAC_CNT_ING_FRAME_1518, + DPMAC_CNT_ING_FRAME_1519_MAX, + DPMAC_CNT_ING_FRAG, + DPMAC_CNT_ING_JABBER, + DPMAC_CNT_ING_FRAME_DISCARD, + DPMAC_CNT_ING_ALIGN_ERR, + DPMAC_CNT_EGR_UNDERSIZED, + DPMAC_CNT_ING_OVERSIZED, + DPMAC_CNT_ING_VALID_PAUSE_FRAME, + DPMAC_CNT_EGR_VALID_PAUSE_FRAME, + DPMAC_CNT_ING_BYTE, + DPMAC_CNT_ING_MCAST_FRAME, + DPMAC_CNT_ING_BCAST_FRAME, + DPMAC_CNT_ING_ALL_FRAME, + DPMAC_CNT_ING_UCAST_FRAME, + DPMAC_CNT_ING_ERR_FRAME, + DPMAC_CNT_EGR_BYTE, + DPMAC_CNT_EGR_MCAST_FRAME, + DPMAC_CNT_EGR_BCAST_FRAME, + DPMAC_CNT_EGR_UCAST_FRAME, + DPMAC_CNT_EGR_ERR_FRAME, + DPMAC_CNT_ING_GOOD_FRAME +}; + +/** + * dpmac_get_counter() - Read a specific DPMAC counter + * @mc_io: Pointer to opaque I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * @type: The requested counter + * @counter: Returned counter value + * + * Return: The requested counter; '0' otherwise. + */ +int dpmac_get_counter(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + enum dpmac_counter type, + uint64_t *counter); + +#endif /* __FSL_DPMAC_H */ diff --git a/include/fsl-mc/fsl_dpni.h b/include/fsl-mc/fsl_dpni.h index e9a4712..140a009 100644 --- a/include/fsl-mc/fsl_dpni.h +++ b/include/fsl-mc/fsl_dpni.h @@ -13,6 +13,8 @@ /* Command IDs */ #define DPNI_CMDID_OPEN 0x801 #define DPNI_CMDID_CLOSE 0x800 +#define DPNI_CMDID_CREATE 0x901 +#define DPNI_CMDID_DESTROY 0x900 #define DPNI_CMDID_ENABLE 0x002 #define DPNI_CMDID_DISABLE 0x003 @@ -48,6 +50,46 @@ #define DPNI_CMD_OPEN(cmd, dpni_id) \ MC_CMD_OP(cmd, 0, 0, 32, int, dpni_id) +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_CREATE(cmd, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->adv.max_tcs); \ + MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->adv.max_senders); \ + MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->mac_addr[5]); \ + MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->mac_addr[4]); \ + MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->mac_addr[3]); \ + MC_CMD_OP(cmd, 0, 40, 8, uint8_t, cfg->mac_addr[2]); \ + MC_CMD_OP(cmd, 0, 48, 8, uint8_t, cfg->mac_addr[1]); \ + MC_CMD_OP(cmd, 0, 56, 8, uint8_t, cfg->mac_addr[0]); \ + MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->adv.options); \ + MC_CMD_OP(cmd, 2, 0, 8, uint8_t, cfg->adv.max_unicast_filters); \ + MC_CMD_OP(cmd, 2, 8, 8, uint8_t, cfg->adv.max_multicast_filters); \ + MC_CMD_OP(cmd, 2, 16, 8, uint8_t, cfg->adv.max_vlan_filters); \ + MC_CMD_OP(cmd, 2, 24, 8, uint8_t, cfg->adv.max_qos_entries); \ + MC_CMD_OP(cmd, 2, 32, 8, uint8_t, cfg->adv.max_qos_key_size); \ + MC_CMD_OP(cmd, 2, 48, 8, uint8_t, cfg->adv.max_dist_key_size); \ + MC_CMD_OP(cmd, 2, 56, 8, enum net_prot, cfg->adv.start_hdr); \ + MC_CMD_OP(cmd, 3, 0, 8, uint8_t, cfg->adv.max_dist_per_tc[0]); \ + MC_CMD_OP(cmd, 3, 8, 8, uint8_t, cfg->adv.max_dist_per_tc[1]); \ + MC_CMD_OP(cmd, 3, 16, 8, uint8_t, cfg->adv.max_dist_per_tc[2]); \ + MC_CMD_OP(cmd, 3, 24, 8, uint8_t, cfg->adv.max_dist_per_tc[3]); \ + MC_CMD_OP(cmd, 3, 32, 8, uint8_t, cfg->adv.max_dist_per_tc[4]); \ + MC_CMD_OP(cmd, 3, 40, 8, uint8_t, cfg->adv.max_dist_per_tc[5]); \ + MC_CMD_OP(cmd, 3, 48, 8, uint8_t, cfg->adv.max_dist_per_tc[6]); \ + MC_CMD_OP(cmd, 3, 56, 8, uint8_t, cfg->adv.max_dist_per_tc[7]); \ + MC_CMD_OP(cmd, 4, 0, 16, uint16_t, \ + cfg->adv.ipr_cfg.max_reass_frm_size); \ + MC_CMD_OP(cmd, 4, 16, 16, uint16_t, \ + cfg->adv.ipr_cfg.min_frag_size_ipv4); \ + MC_CMD_OP(cmd, 4, 32, 16, uint16_t, \ + cfg->adv.ipr_cfg.min_frag_size_ipv6); \ + MC_CMD_OP(cmd, 4, 48, 8, uint8_t, cfg->adv.max_policers); \ + MC_CMD_OP(cmd, 4, 56, 8, uint8_t, cfg->adv.max_congestion_ctrl); \ + MC_CMD_OP(cmd, 5, 0, 16, uint16_t, \ + cfg->adv.ipr_cfg.max_open_frames_ipv4); \ + MC_CMD_OP(cmd, 5, 16, 16, uint16_t, \ + cfg->adv.ipr_cfg.max_open_frames_ipv6); \ +} while (0) /* cmd, param, offset, width, type, arg_name */ #define DPNI_CMD_SET_POOLS(cmd, cfg) \ @@ -475,6 +517,53 @@ int dpni_close(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token); +/* DPNI configuration options */ + +/** + * Allow different distribution key profiles for different traffic classes; + * if not set, a single key profile is assumed + */ +#define DPNI_OPT_ALLOW_DIST_KEY_PER_TC 0x00000001 + +/** + * Disable all non-error transmit confirmation; error frames are reported + * back to a common Tx error queue + */ +#define DPNI_OPT_TX_CONF_DISABLED 0x00000002 + +/* Disable per-sender private Tx confirmation/error queue */ +#define DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED 0x00000004 + +/** + * Support distribution based on hashed key; + * allows statistical distribution over receive queues in a traffic class + */ +#define DPNI_OPT_DIST_HASH 0x00000010 + +/** + * Support distribution based on flow steering; + * allows explicit control of distribution over receive queues in a traffic + * class + */ +#define DPNI_OPT_DIST_FS 0x00000020 + +/* Unicast filtering support */ +#define DPNI_OPT_UNICAST_FILTER 0x00000080 +/* Multicast filtering support */ +#define DPNI_OPT_MULTICAST_FILTER 0x00000100 +/* VLAN filtering support */ +#define DPNI_OPT_VLAN_FILTER 0x00000200 +/* Support IP reassembly on received packets */ +#define DPNI_OPT_IPR 0x00000800 +/* Support IP fragmentation on transmitted packets */ +#define DPNI_OPT_IPF 0x00001000 +/* VLAN manipulation support */ +#define DPNI_OPT_VLAN_MANIPULATION 0x00010000 +/* Support masking of QoS lookup keys */ +#define DPNI_OPT_QOS_MASK_SUPPORT 0x00020000 +/* Support masking of Flow Steering lookup keys */ +#define DPNI_OPT_FS_MASK_SUPPORT 0x00040000 + /** * struct dpni_ipr_cfg - Structure representing IP reassembly configuration * @max_reass_frm_size: Maximum size of the reassembled frame @@ -492,6 +581,106 @@ struct dpni_ipr_cfg { }; /** + * struct dpni_cfg - Structure representing DPNI configuration + * @mac_addr: Primary MAC address + * @adv: Advanced parameters; default is all zeros; + * use this structure to change default settings + */ +struct dpni_cfg { + uint8_t mac_addr[6]; + /** + * struct adv - Advanced parameters + * @options: Mask of available options; use 'DPNI_OPT_<X>' values + * @start_hdr: Selects the packet starting header for parsing; + * 'NET_PROT_NONE' is treated as default: 'NET_PROT_ETH' + * @max_senders: Maximum number of different senders; used as the number + * of dedicated Tx flows; Non-power-of-2 values are rounded + * up to the next power-of-2 value as hardware demands it; + * '0' will be treated as '1' + * @max_tcs: Maximum number of traffic classes (for both Tx and Rx); + * '0' will e treated as '1' + * @max_dist_per_tc: Maximum distribution size per Rx traffic class; + * Must be set to the required value minus 1; + * i.e. 0->1, 1->2, ... ,255->256; + * Non-power-of-2 values are rounded up to the next + * power-of-2 value as hardware demands it + * @max_unicast_filters: Maximum number of unicast filters; + * '0' is treated as '16' + * @max_multicast_filters: Maximum number of multicast filters; + * '0' is treated as '64' + * @max_qos_entries: if 'max_tcs > 1', declares the maximum entries in + * the QoS table; '0' is treated as '64' + * @max_qos_key_size: Maximum key size for the QoS look-up; + * '0' is treated as '24' which is enough for IPv4 + * 5-tuple + * @max_dist_key_size: Maximum key size for the distribution; + * '0' is treated as '24' which is enough for IPv4 5-tuple + * @max_policers: Maximum number of policers; + * should be between '0' and max_tcs + * @max_congestion_ctrl: Maximum number of congestion control groups + * (CGs); covers early drop and congestion notification + * requirements for traffic classes; + * should be between '0' and max_tcs + * @ipr_cfg: IP reassembly configuration + */ + struct { + uint32_t options; + enum net_prot start_hdr; + uint8_t max_senders; + uint8_t max_tcs; + uint8_t max_dist_per_tc[DPNI_MAX_TC]; + uint8_t max_unicast_filters; + uint8_t max_multicast_filters; + uint8_t max_vlan_filters; + uint8_t max_qos_entries; + uint8_t max_qos_key_size; + uint8_t max_dist_key_size; + uint8_t max_policers; + uint8_t max_congestion_ctrl; + struct dpni_ipr_cfg ipr_cfg; + } adv; +}; + +/** + * dpni_create() - Create the DPNI object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @cfg: Configuration structure + * @token: Returned token; use in subsequent API calls + * + * Create the DPNI object, allocate required resources and + * perform required initialization. + * + * The object can be created either by declaring it in the + * DPL file, or by calling this function. + * + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent calls to + * this specific object. For objects that are created using the + * DPL file, call dpni_open() function to get an authentication + * token first. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_create(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + const struct dpni_cfg *cfg, + uint16_t *token); + +/** + * dpni_destroy() - Destroy the DPNI object and release all its resources. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * + * Return: '0' on Success; error code otherwise. + */ +int dpni_destroy(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token); + +/** * struct dpni_pools_cfg - Structure representing buffer pools configuration * @num_dpbp: Number of DPBPs * @pools: Array of buffer pools parameters; The number of valid entries diff --git a/include/fsl-mc/fsl_dprc.h b/include/fsl-mc/fsl_dprc.h index b2cd2cb..a87179d 100644 --- a/include/fsl-mc/fsl_dprc.h +++ b/include/fsl-mc/fsl_dprc.h @@ -16,10 +16,13 @@ /* Command IDs */ #define DPRC_CMDID_CLOSE 0x800 #define DPRC_CMDID_OPEN 0x805 +#define DPRC_CMDID_CREATE 0x905 #define DPRC_CMDID_GET_ATTR 0x004 #define DPRC_CMDID_RESET_CONT 0x005 +#define DPRC_CMDID_CREATE_CONT 0x151 +#define DPRC_CMDID_DESTROY_CONT 0x152 #define DPRC_CMDID_GET_CONT_ID 0x830 #define DPRC_CMDID_GET_OBJ_COUNT 0x159 #define DPRC_CMDID_GET_OBJ 0x15A @@ -40,6 +43,41 @@ MC_CMD_OP(cmd, 0, 0, 32, int, container_id) /* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_CREATE_CONTAINER(cmd, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 32, 16, uint16_t, cfg->icid); \ + MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->options); \ + MC_CMD_OP(cmd, 1, 32, 32, int, cfg->portal_id); \ + MC_CMD_OP(cmd, 2, 0, 8, char, cfg->label[0]);\ + MC_CMD_OP(cmd, 2, 8, 8, char, cfg->label[1]);\ + MC_CMD_OP(cmd, 2, 16, 8, char, cfg->label[2]);\ + MC_CMD_OP(cmd, 2, 24, 8, char, cfg->label[3]);\ + MC_CMD_OP(cmd, 2, 32, 8, char, cfg->label[4]);\ + MC_CMD_OP(cmd, 2, 40, 8, char, cfg->label[5]);\ + MC_CMD_OP(cmd, 2, 48, 8, char, cfg->label[6]);\ + MC_CMD_OP(cmd, 2, 56, 8, char, cfg->label[7]);\ + MC_CMD_OP(cmd, 3, 0, 8, char, cfg->label[8]);\ + MC_CMD_OP(cmd, 3, 8, 8, char, cfg->label[9]);\ + MC_CMD_OP(cmd, 3, 16, 8, char, cfg->label[10]);\ + MC_CMD_OP(cmd, 3, 24, 8, char, cfg->label[11]);\ + MC_CMD_OP(cmd, 3, 32, 8, char, cfg->label[12]);\ + MC_CMD_OP(cmd, 3, 40, 8, char, cfg->label[13]);\ + MC_CMD_OP(cmd, 3, 48, 8, char, cfg->label[14]);\ + MC_CMD_OP(cmd, 3, 56, 8, char, cfg->label[15]);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_RSP_CREATE_CONTAINER(cmd, child_container_id, child_portal_offset)\ +do { \ + MC_RSP_OP(cmd, 1, 0, 32, int, child_container_id); \ + MC_RSP_OP(cmd, 2, 0, 64, uint64_t, child_portal_offset);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_DESTROY_CONTAINER(cmd, child_container_id) \ + MC_CMD_OP(cmd, 0, 0, 32, int, child_container_id) + +/* cmd, param, offset, width, type, arg_name */ #define DPRC_CMD_RESET_CONTAINER(cmd, child_container_id) \ MC_CMD_OP(cmd, 0, 0, 32, int, child_container_id) @@ -467,6 +505,52 @@ struct dprc_cfg { }; /** + * dprc_create_container() - Create child container + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @cfg: Child container configuration + * @child_container_id: Returned child container ID + * @child_portal_offset: Returned child portal offset from MC portal base + * + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_create_container(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dprc_cfg *cfg, + int *child_container_id, + uint64_t *child_portal_offset); + +/** + * dprc_destroy_container() - Destroy child container. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @child_container_id: ID of the container to destroy + * + * This function terminates the child container, so following this call the + * child container ID becomes invalid. + * + * Notes: + * - All resources and objects of the destroyed container are returned to the + * parent container or destroyed if were created be the destroyed container. + * - This function destroy all the child containers of the specified + * container prior to destroying the container itself. + * + * warning: Only the parent container is allowed to destroy a child policy + * Container 0 can't be destroyed + * + * Return: '0' on Success; Error code otherwise. + * + */ +int dprc_destroy_container(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + int child_container_id); + +/** * dprc_reset_container - Reset child container. * @mc_io: Pointer to MC portal's I/O object * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h index 9517a4a..ffe6da5 100644 --- a/include/fsl-mc/fsl_mc.h +++ b/include/fsl-mc/fsl_mc.h @@ -29,6 +29,9 @@ ((void __iomem *)((uintptr_t)SOC_MC_PORTALS_BASE_ADDR + \ (_portal_id) * SOC_MC_PORTAL_STRIDE)) +#define MC_PORTAL_OFFSET_TO_PORTAL_ID(_portal_offset) \ + ((_portal_offset) / SOC_MC_PORTAL_STRIDE) + struct mc_ccsr_registers { u32 reg_gcr1; u32 reserved1; @@ -50,7 +53,12 @@ struct mc_ccsr_registers { }; int get_mc_boot_status(void); +int get_dpl_apply_status(void); +#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET +int get_aiop_apply_status(void); +#endif +u64 mc_get_dram_addr(void); unsigned long mc_get_dram_block_size(void); int fsl_mc_ldpaa_init(bd_t *bis); -void fsl_mc_ldpaa_exit(bd_t *bis); +int fsl_mc_ldpaa_exit(bd_t *bd); #endif diff --git a/include/fsl-mc/fsl_mc_private.h b/include/fsl-mc/fsl_mc_private.h index 9f06978..17e0611 100644 --- a/include/fsl-mc/fsl_mc_private.h +++ b/include/fsl-mc/fsl_mc_private.h @@ -13,18 +13,20 @@ #include <linux/compat.h> #include <linux/types.h> #include <linux/stringify.h> +#include <phy.h> #include <fsl-mc/fsl_mc_sys.h> #include <fsl-mc/fsl_mc_cmd.h> #include <fsl-mc/fsl_dprc.h> #include <fsl-mc/fsl_dpbp.h> +#include <fsl-mc/fsl_dpni.h> extern struct fsl_mc_io *dflt_mc_io; /** * struct dpbp_node - DPBP strucuture * @uint16_t handle: DPBP object handle - * @int dpbp_id: DPBP id + * @struct dpbp_attr: DPBP attribute */ struct fsl_dpbp_obj { uint16_t dpbp_handle; @@ -40,11 +42,29 @@ extern struct fsl_dpbp_obj *dflt_dpbp; */ struct fsl_dpio_obj { int dpio_id; + uint16_t dpio_handle; struct qbman_swp *sw_portal; /** SW portal object */ }; extern struct fsl_dpio_obj *dflt_dpio; -int mc_init(void); -int ldpaa_eth_init(struct dprc_obj_desc obj_desc); +/** + * struct dpni_node - DPNI strucuture + * @int dpni_id: DPNI id + * @uint16_t handle: DPNI object handle + * @struct dpni_attr: DPNI attributes + * @struct dpni_buffer_layout: DPNI buffer layout + */ +struct fsl_dpni_obj { + int dpni_id; + uint16_t dpni_handle; + struct dpni_attr dpni_attrs; + struct dpni_buffer_layout buf_layout; +}; + +extern struct fsl_dpni_obj *dflt_dpni; + +int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr); +int ldpaa_eth_init(int dpmac_id, phy_interface_t enet_if); +int mc_apply_dpl(u64 mc_dpl_addr); #endif /* _FSL_MC_PRIVATE_H_ */ diff --git a/include/fsl-mc/ldpaa_wriop.h b/include/fsl-mc/ldpaa_wriop.h index ca8e440..6dc159d 100644 --- a/include/fsl-mc/ldpaa_wriop.h +++ b/include/fsl-mc/ldpaa_wriop.h @@ -40,8 +40,8 @@ enum wriop_port { struct wriop_dpmac_info { u8 enabled; u8 id; - u8 phy_addr; u8 board_mux; + int phy_addr; void *phy_regs; phy_interface_t enet_if; struct phy_device *phydev; @@ -56,6 +56,7 @@ extern struct wriop_dpmac_info dpmac_info[NUM_WRIOP_PORTS]; void wriop_init_dpmac(int, int, int); void wriop_disable_dpmac(int); void wriop_enable_dpmac(int); +u8 wriop_is_enabled_dpmac(int dpmac_id); void wriop_set_mdio(int, struct mii_dev *); struct mii_dev *wriop_get_mdio(int); void wriop_set_phy_address(int, int); diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index 1ac092b..9aaf6b3 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -131,6 +131,7 @@ void board_add_ram_info(int use_default); /* processor specific function */ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int ctrl_num, int step); +void remove_unused_controllers(fsl_ddr_info_t *info); /* board specific function */ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, diff --git a/include/i2c.h b/include/i2c.h index 6493931..1f5ae45 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -499,7 +499,8 @@ int i2c_get_chip(struct udevice *bus, uint chip_addr, uint offset_len, struct udevice **devp); /** - * i2c_get_chip() - get a device to use to access a chip on a bus number + * i2c_get_chip_for_busnum() - get a device to use to access a chip on + * a bus number * * This returns the device for the given chip address on a particular bus * number. diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h index 602a413..e922e32 100644 --- a/include/linux/usb/xhci-fsl.h +++ b/include/linux/usb/xhci-fsl.h @@ -54,11 +54,18 @@ struct fsl_xhci { #if defined(CONFIG_LS102XA) #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0 -#elif defined(CONFIG_LS2085A) -#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2085A_XHCI_USB1_ADDR -#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2085A_XHCI_USB2_ADDR +#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 +#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR +#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR +#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 +#elif defined(CONFIG_LS1043A) +#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR +#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR +#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR #endif #define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \ - CONFIG_SYS_FSL_XHCI_USB2_ADDR} + CONFIG_SYS_FSL_XHCI_USB2_ADDR, \ + CONFIG_SYS_FSL_XHCI_USB3_ADDR} #endif /* _ASM_ARCH_XHCI_FSL_H_ */ diff --git a/include/part.h b/include/part.h index 8b5ac12..720a867 100644 --- a/include/part.h +++ b/include/part.h @@ -267,6 +267,41 @@ int is_valid_gpt_buf(block_dev_desc_t *dev_desc, void *buf); * @return - '0' on success, otherwise error */ int write_mbr_and_gpt_partitions(block_dev_desc_t *dev_desc, void *buf); + +/** + * gpt_verify_headers() - Function to read and CRC32 check of the GPT's header + * and partition table entries (PTE) + * + * As a side effect if sets gpt_head and gpt_pte so they point to GPT data. + * + * @param dev_desc - block device descriptor + * @param gpt_head - pointer to GPT header data read from medium + * @param gpt_pte - pointer to GPT partition table enties read from medium + * + * @return - '0' on success, otherwise error + */ +int gpt_verify_headers(block_dev_desc_t *dev_desc, gpt_header *gpt_head, + gpt_entry **gpt_pte); + +/** + * gpt_verify_partitions() - Function to check if partitions' name, start and + * size correspond to '$partitions' env variable + * + * This function checks if on medium stored GPT data is in sync with information + * provided in '$partitions' environment variable. Specificially, name, start + * and size of the partition is checked. + * + * @param dev_desc - block device descriptor + * @param partitions - partition data read from '$partitions' env variable + * @param parts - number of partitions read from '$partitions' env variable + * @param gpt_head - pointer to GPT header data read from medium + * @param gpt_pte - pointer to GPT partition table enties read from medium + * + * @return - '0' on success, otherwise error + */ +int gpt_verify_partitions(block_dev_desc_t *dev_desc, + disk_partition_t *partitions, int parts, + gpt_header *gpt_head, gpt_entry **gpt_pte); #endif #endif /* _PART_H */ diff --git a/include/pci.h b/include/pci.h index ed135a5..2adca85 100644 --- a/include/pci.h +++ b/include/pci.h @@ -537,6 +537,8 @@ extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev /* * Structure of a PCI controller (host bridge) + * + * With driver model this is dev_get_uclass_priv(bus) */ struct pci_controller { #ifdef CONFIG_DM_PCI @@ -654,6 +656,7 @@ extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose, pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags)) /* For driver model these are defined in macros in pci_compat.c */ +#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) extern int pci_hose_read_config_byte(struct pci_controller *hose, pci_dev_t dev, int where, u8 *val); extern int pci_hose_read_config_word(struct pci_controller *hose, @@ -666,6 +669,7 @@ extern int pci_hose_write_config_word(struct pci_controller *hose, pci_dev_t dev, int where, u16 val); extern int pci_hose_write_config_dword(struct pci_controller *hose, pci_dev_t dev, int where, u32 val); +#endif #ifndef CONFIG_DM_PCI extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val); @@ -676,6 +680,13 @@ extern int pci_write_config_word(pci_dev_t dev, int where, u16 val); extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val); #endif +void pciauto_region_init(struct pci_region *res); +void pciauto_region_align(struct pci_region *res, pci_size_t size); +void pciauto_config_init(struct pci_controller *hose); +int pciauto_region_allocate(struct pci_region *res, pci_size_t size, + pci_addr_t *bar); + +#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose, pci_dev_t dev, int where, u8 *val); extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose, @@ -694,9 +705,6 @@ extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev); extern int pci_hose_scan(struct pci_controller *hose); extern int pci_hose_scan_bus(struct pci_controller *hose, int bus); -extern void pciauto_region_init(struct pci_region* res); -extern void pciauto_region_align(struct pci_region *res, pci_size_t size); -extern int pciauto_region_allocate(struct pci_region* res, pci_size_t size, pci_addr_t *bar); extern void pciauto_setup_device(struct pci_controller *hose, pci_dev_t dev, int bars_num, struct pci_region *mem, @@ -706,7 +714,6 @@ extern void pciauto_prescan_setup_bridge(struct pci_controller *hose, pci_dev_t dev, int sub_bus); extern void pciauto_postscan_setup_bridge(struct pci_controller *hose, pci_dev_t dev, int sub_bus); -extern void pciauto_config_init(struct pci_controller *hose); extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index); @@ -737,6 +744,7 @@ extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, unsigned short device, unsigned short class); #endif +#endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */ const char * pci_class_str(u8 class); int pci_last_busno(void); @@ -745,6 +753,7 @@ int pci_last_busno(void); extern void pci_mpc85xx_init (struct pci_controller *hose); #endif +#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) /** * pci_write_bar32() - Write the address of a BAR including control bits * @@ -781,6 +790,7 @@ u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum); */ pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum, struct pci_device_id *ids, int *indexp); +#endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */ /* Access sizes for PCI reads and writes */ enum pci_size_t { @@ -1039,6 +1049,7 @@ int dm_pci_write_config32(struct udevice *dev, int offset, u32 value); */ int pci_write_config32(pci_dev_t pcidev, int offset, u32 value); +#ifdef CONFIG_DM_PCI_COMPAT /* Compatibility with old naming */ static inline int pci_write_config_dword(pci_dev_t pcidev, int offset, u32 value) @@ -1091,6 +1102,70 @@ static inline int pci_read_config_byte(pci_dev_t pcidev, int offset, return pci_read_config8(pcidev, offset, valuep); } +#endif /* CONFIG_DM_PCI_COMPAT */ + +/** + * dm_pciauto_config_device() - configure a device ready for use + * + * Space is allocated for each PCI base address register (BAR) so that the + * devices are mapped into memory and I/O space ready for use. + * + * @dev: Device to configure + * @return 0 if OK, -ve on error + */ +int dm_pciauto_config_device(struct udevice *dev); + +/** + * pci_conv_32_to_size() - convert a 32-bit read value to the given size + * + * Some PCI buses must always perform 32-bit reads. The data must then be + * shifted and masked to reflect the required access size and offset. This + * function performs this transformation. + * + * @value: Value to transform (32-bit value read from @offset & ~3) + * @offset: Register offset that was read + * @size: Required size of the result + * @return the value that would have been obtained if the read had been + * performed at the given offset with the correct size + */ +ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size); + +/** + * pci_conv_size_to_32() - update a 32-bit value to prepare for a write + * + * Some PCI buses must always perform 32-bit writes. To emulate a smaller + * write the old 32-bit data must be read, updated with the required new data + * and written back as a 32-bit value. This function performs the + * transformation from the old value to the new value. + * + * @value: Value to transform (32-bit value read from @offset & ~3) + * @offset: Register offset that should be written + * @size: Required size of the write + * @return the value that should be written as a 32-bit access to @offset & ~3. + */ +ulong pci_conv_size_to_32(ulong old, ulong value, uint offset, + enum pci_size_t size); + +/** + * pci_get_controller() - obtain the controller to use for a bus + * + * @dev: Device to check + * @return pointer to the controller device for this bus + */ +struct udevice *pci_get_controller(struct udevice *dev); + +/** + * pci_get_regions() - obtain pointers to all the region types + * + * @dev: Device to check + * @iop: Returns a pointer to the I/O region, or NULL if none + * @memp: Returns a pointer to the memory region, or NULL if none + * @prefp: Returns a pointer to the pre-fetch region, or NULL if none + * @return the number of non-NULL regions returned, normally 3 + */ +int pci_get_regions(struct udevice *dev, struct pci_region **iop, + struct pci_region **memp, struct pci_region **prefp); + /** * struct dm_pci_emul_ops - PCI device emulator operations */ diff --git a/include/timer.h b/include/timer.h index cdf385d..7fee17e 100644 --- a/include/timer.h +++ b/include/timer.h @@ -8,36 +8,45 @@ #define _TIMER_H_ /* + * timer_conv_64 - convert 32-bit counter value to 64-bit + * + * @count: 32-bit counter value + * @return: 64-bit counter value + */ +u64 timer_conv_64(u32 count); + +/* * Get the current timer count * - * @dev: The Timer device + * @dev: The timer device * @count: pointer that returns the current timer count * @return: 0 if OK, -ve on error */ -int timer_get_count(struct udevice *dev, unsigned long *count); +int timer_get_count(struct udevice *dev, u64 *count); + /* * Get the timer input clock frequency * - * @dev: The Timer device + * @dev: The timer device * @return: the timer input clock frequency */ unsigned long timer_get_rate(struct udevice *dev); /* - * struct timer_ops - Driver model Timer operations + * struct timer_ops - Driver model timer operations * - * The uclass interface is implemented by all Timer devices which use + * The uclass interface is implemented by all timer devices which use * driver model. */ struct timer_ops { /* * Get the current timer count * - * @dev: The Timer device - * @count: pointer that returns the current timer count + * @dev: The timer device + * @count: pointer that returns the current 64-bit timer count * @return: 0 if OK, -ve on error */ - int (*get_count)(struct udevice *dev, unsigned long *count); + int (*get_count)(struct udevice *dev, u64 *count); }; /* |