diff options
Diffstat (limited to 'include')
110 files changed, 1896 insertions, 341 deletions
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 0abcbe4..a6d1d2a 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -55,20 +55,6 @@ typedef struct global_data { unsigned long relocaddr; /* Start address of U-Boot in RAM */ phys_size_t ram_size; /* RAM size */ -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE -#define MEM_RESERVE_SECURE_SECURED 0x1 -#define MEM_RESERVE_SECURE_MAINTAINED 0x2 -#define MEM_RESERVE_SECURE_ADDR_MASK (~0x3) - /* - * Secure memory addr - * This variable needs maintenance if the RAM base is not zero, - * or if RAM splits into non-consecutive banks. It also has a - * flag indicating the secure memory is marked as secure by MMU. - * Flags used: 0x1 secured - * 0x2 maintained - */ - phys_addr_t secure_ram; -#endif unsigned long mon_len; /* monitor len */ unsigned long irq_sp; /* irq stack pointer */ unsigned long start_addr_sp; /* start_addr_stackpointer */ diff --git a/include/clk.h b/include/clk.h index 2f31cf7..161bc28 100644 --- a/include/clk.h +++ b/include/clk.h @@ -60,6 +60,10 @@ struct clk { }; #if CONFIG_IS_ENABLED(OF_CONTROL) +struct phandle_2_cell; +int clk_get_by_index_platdata(struct udevice *dev, int index, + struct phandle_2_cell *cells, struct clk *clk); + /** * clock_get_by_index - Get/request a clock by integer index. * diff --git a/include/common.h b/include/common.h index 3feaae6..e9f0dea 100644 --- a/include/common.h +++ b/include/common.h @@ -101,6 +101,13 @@ typedef volatile unsigned char vu_char; #define _DEBUG 0 #endif +#ifdef CONFIG_SPL_BUILD +#define _SPL_BUILD 1 +#else +#define _SPL_BUILD 0 +#endif + +/* Define this at the top of a file to add a prefix to debug messages */ #ifndef pr_fmt #define pr_fmt(fmt) fmt #endif @@ -116,9 +123,14 @@ typedef volatile unsigned char vu_char; printf(pr_fmt(fmt), ##args); \ } while (0) +/* Show a message if DEBUG is defined in a file */ #define debug(fmt, args...) \ debug_cond(_DEBUG, fmt, ##args) +/* Show a message if not in SPL */ +#define warn_non_spl(fmt, args...) \ + debug_cond(!_SPL_BUILD, fmt, ##args) + /* * An assertion is run-time check done in debug mode only. If DEBUG is not * defined then it is skipped. If DEBUG is defined and the assertion fails, diff --git a/include/config_fsl_chain_trust.h b/include/config_fsl_chain_trust.h index 566fd80..eb45e98 100644 --- a/include/config_fsl_chain_trust.h +++ b/include/config_fsl_chain_trust.h @@ -74,23 +74,27 @@ #ifdef CONFIG_BOOTSCRIPT_COPY_RAM #define CONFIG_BS_COPY_ENV \ "setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \ - "setenv bs_hdr_flash " __stringify(CONFIG_BS_HDR_ADDR_FLASH)";" \ + "setenv bs_hdr_device " __stringify(CONFIG_BS_HDR_ADDR_DEVICE)";" \ "setenv bs_hdr_size " __stringify(CONFIG_BS_HDR_SIZE)";" \ "setenv bs_ram " __stringify(CONFIG_BS_ADDR_RAM)";" \ - "setenv bs_flash " __stringify(CONFIG_BS_ADDR_FLASH)";" \ + "setenv bs_device " __stringify(CONFIG_BS_ADDR_DEVICE)";" \ "setenv bs_size " __stringify(CONFIG_BS_SIZE)";" /* For secure boot flow, default environment used will be used */ #if defined(CONFIG_SYS_RAMBOOT) #if defined(CONFIG_RAMBOOT_NAND) #define CONFIG_BS_COPY_CMD \ - "nand read $bs_hdr_ram $bs_hdr_flash $bs_hdr_size ;" \ - "nand read $bs_ram $bs_flash $bs_size ;" + "nand read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \ + "nand read $bs_ram $bs_device $bs_size ;" #endif /* CONFIG_RAMBOOT_NAND */ -#else +#elif defined(CONFIG_SD_BOOT) +#define CONFIG_BS_COPY_CMD \ + "mmc read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \ + "mmc read $bs_ram $bs_device $bs_size ;" +#else /* CONFIG_SD_BOOT */ #define CONFIG_BS_COPY_CMD \ - "cp.b $bs_hdr_flash $bs_hdr_ram $bs_hdr_size ;" \ - "cp.b $bs_flash $bs_ram $bs_size ;" + "cp.b $bs_hdr_device $bs_hdr_ram $bs_hdr_size ;" \ + "cp.b $bs_device $bs_ram $bs_size ;" #endif #endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 2c3c4ac..5de9bb7 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -830,7 +830,7 @@ unsigned long get_board_ddr_clk(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=b4860qds/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=b4860qds/b4860qds.dtb\0" \ "bdev=sda3\0" @@ -868,7 +868,7 @@ unsigned long get_board_ddr_clk(void); "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "setenv ramdiskaddr 0x02000000;" \ - "setenv fdtaddr 0x00c00000;" \ + "setenv fdtaddr 0x01e00000;" \ "setenv loadaddr 0x1000000;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 0a9d8a6..f2a7c69 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -403,7 +403,7 @@ extern unsigned long get_sdram_size(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=bsc9131rdb.dtb\0" \ "bdev=sda1\0" \ "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 756beec..4744f08 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -647,7 +647,7 @@ combinations. this should be removed later "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=bsc9132qds.dtb\0" \ "bdev=sda1\0" \ CONFIG_DEF_HWCONFIG\ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 69a9798..cc5359f 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -530,7 +530,7 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=name/of/device-tree.dtb\0" \ "othbootargs=ramdisk_size=600000\0" \ diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 578325c..5b80464 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -203,7 +203,7 @@ */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* @@ -452,6 +452,7 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Core HID Setup diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 5613a4a..1c4e082 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -241,7 +241,7 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* @@ -268,7 +268,7 @@ #define CONFIG_CMD_MTDPARTS #define MTDIDS_DEFAULT "nand0=e2800000.flash" #define MTDPARTS_DEFAULT \ - "mtdparts=e2800000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" + "mtdparts=e2800000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)" #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_CMD_NAND 1 @@ -502,6 +502,7 @@ */ /* Initial Memory map for Linux*/ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 7ce5f59..23a2e34 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -169,7 +169,7 @@ /* * The reserved memory */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* @@ -241,7 +241,7 @@ #define CONFIG_CMD_MTDPARTS #define MTDIDS_DEFAULT "nand0=e0600000.flash" #define MTDPARTS_DEFAULT \ - "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" + "mtdparts=e0600000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)" #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_CMD_NAND 1 @@ -489,6 +489,7 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Core HID Setup diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 13f954d..095c0d8 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -156,7 +156,7 @@ #endif /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* @@ -359,6 +359,7 @@ */ /* Initial Memory map for Linux */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Core HID Setup diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index fd48260..18418e3 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -168,7 +168,7 @@ #endif /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* @@ -441,6 +441,7 @@ */ /* Initial Memory map for Linux */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Core HID Setup diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 288b126..a2fa783 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -225,7 +225,7 @@ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* @@ -508,6 +508,7 @@ */ /* Initial Memory map for Linux*/ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 2721255..c11c0cf 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -330,7 +330,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* @@ -544,6 +544,7 @@ boards, we say we have two, but don't display a message if we find only one. */ */ /* Initial Memory map for Linux*/ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #define CONFIG_SYS_HRCW_LOW (\ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 921d5f3..b2dc189 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -200,7 +200,7 @@ #endif /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* @@ -522,6 +522,7 @@ extern int board_pci_host_broken(void); * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Core HID Setup diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index bb06e89..8eb87eb 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -225,7 +225,7 @@ #undef CONFIG_SYS_RAMBOOT #endif -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* @@ -533,6 +533,7 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Core HID Setup diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 7c19ff8..874261a 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -727,7 +727,7 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=8536ds/ramdisk.uboot\0" \ -"fdtaddr=c00000\0" \ +"fdtaddr=1e00000\0" \ "fdtfile=8536ds/mpc8536ds.dtb\0" \ "bdev=sda3\0" \ "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index b9d97c1..cd10432 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -209,7 +209,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 400000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 @@ -462,7 +462,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=8544ds/ramdisk.uboot\0" \ -"fdtaddr=c00000\0" \ +"fdtaddr=1e00000\0" \ "fdtfile=8544ds/mpc8544ds.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index e73be48..b81a4ed 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -562,7 +562,7 @@ extern unsigned long get_clock_freq(void); "consoledev=ttyS1\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=mpc8548cds.dtb\0" #define CONFIG_NFSBOOTCOMMAND \ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 2e6989f..390b1ef 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -668,7 +668,7 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=8572ds/ramdisk.uboot\0" \ -"fdtaddr=c00000\0" \ +"fdtaddr=1e00000\0" \ "fdtfile=8572ds/mpc8572ds.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 5384584..5b6b4bd 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -862,7 +862,7 @@ extern unsigned long get_sdram_size(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=p1010rdb.dtb\0" \ "bdev=sda1\0" \ "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index bdf0323..fe19957 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -731,7 +731,7 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=p1022ds.dtb\0" \ "bdev=sda3\0" \ "hwconfig=esdhc;audclk:12\0" diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index 07a594d..d044c7b 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -375,7 +375,7 @@ extern unsigned long get_clock_freq(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=p1023rdb.dtb\0" \ "othbootargs=ramdisk_size=600000\0" \ "bdev=sda1\0" \ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 24e5431..8479410 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -698,7 +698,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); "usb_dr_mode=host\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=p2041rdb/p2041rdb.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 06d1d0f..25a0652 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -897,7 +897,7 @@ unsigned long get_board_ddr_clk(void); "cmp.b $loadaddr $ubootaddr $filesize\0" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "bdev=sda3\0" #define CONFIG_LINUX \ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 9f5063c..7ce6420 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -770,7 +770,7 @@ unsigned long get_board_ddr_clk(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=t1040qds/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=t1040qds/t1040qds.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index a8f4f74..ae1acbd 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -18,7 +18,14 @@ #include <asm/config_mpc85xx.h> #ifdef CONFIG_RAMBOOT_PBL + +#ifndef CONFIG_SECURE_BOOT #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg +#else +#define CONFIG_SYS_FSL_PBL_PBI \ + $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg +#endif + #ifdef CONFIG_T1040RDB #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg #endif @@ -62,7 +69,17 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg #ifdef CONFIG_NAND #define CONFIG_SPL_NAND_SUPPORT +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) +/* + * HDR would be appended at end of image and copied to DDR along + * with U-Boot image. + */ +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ + CONFIG_U_BOOT_HDR_SIZE) +#else #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#endif #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) @@ -161,6 +178,10 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (512 * 0x800) #elif defined(CONFIG_NAND) +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_RAMBOOT_NAND +#define CONFIG_BOOTSCRIPT_COPY_RAM +#endif #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE 0x2000 @@ -202,8 +223,14 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg * Config the L3 Cache as L3 SRAM */ #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +/* + * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence + * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address + * (CONFIG_SYS_INIT_L3_VADDR) will be different. + */ +#define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 #define CONFIG_SYS_L3_SIZE 256 << 10 -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) #endif @@ -873,7 +900,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=" __stringify(FDTFILE) "\0" \ "bdev=sda3\0" diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 1f07a83..6217555 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -840,7 +840,7 @@ unsigned long get_board_ddr_clk(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=t2080qds/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=t2080qds/t2080qds.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 0ded41e..7a7de97 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -792,7 +792,7 @@ unsigned long get_board_ddr_clk(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=t2080rdb/t2080rdb.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index f075dfb..85aab18 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -577,7 +577,7 @@ unsigned long get_board_ddr_clk(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=t4240qds/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=t4240qds/t4240qds.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 9ba69a1..4133165 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -770,7 +770,7 @@ unsigned long get_board_ddr_clk(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=t4240rdb/t4240rdb.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/arndale.h b/include/configs/arndale.h index b08f341..18e59fc 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -45,6 +45,7 @@ #define CONFIG_S5P_PA_SYSRAM 0x02020000 #define CONFIG_SMP_PEN_ADDR CONFIG_S5P_PA_SYSRAM +#define CONFIG_ARMV7_PSCI_NR_CPUS 4 /* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */ #define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000 diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h index d5888e8..50cd743 100644 --- a/include/configs/bcm_ep_board.h +++ b/include/configs/bcm_ep_board.h @@ -93,5 +93,6 @@ /* Misc utility code */ #define CONFIG_BOUNCE_BUFFER #define CONFIG_CRC32_VERIFY +#define CONFIG_ARMV7_PSCI_NR_CPUS 4 #endif /* __BCM_EP_BOARD_H */ diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index 30c2831..44e115d 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -447,7 +447,7 @@ "consoledev=ttyS1\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=controlcenterd.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 4a770b0..0c99e9f 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -708,7 +708,7 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=p4080ds/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=p4080ds/p4080ds.dtb\0" \ "bdev=sda3\0" diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h index 708d5f7..da38709 100644 --- a/include/configs/cyrus.h +++ b/include/configs/cyrus.h @@ -520,7 +520,7 @@ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ -"fdtaddr=c00000\0" \ +"fdtaddr=1e00000\0" \ "bdev=sda3\0" #define CONFIG_HDBOOT \ diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h index 4b00922..1dbe219 100644 --- a/include/configs/dragonboard410c.h +++ b/include/configs/dragonboard410c.h @@ -84,8 +84,8 @@ #define BOOT_TARGET_DEVICES(func) \ func(USB, usb, 0) \ - func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> @@ -126,6 +126,8 @@ REFLASH(dragonboard/u-boot.img, 8)\ "fdtfile=apq8016-sbc.dtb\0" \ "fdt_addr_r=0x83000000\0"\ "ramdisk_addr_r=0x84000000\0"\ + "scriptaddr=0x90000000\0"\ + "pxefile_addr_r=0x90100000\0"\ BOOTENV #define CONFIG_ENV_IS_NOWHERE diff --git a/include/configs/evb-rk3288.h b/include/configs/evb-rk3288.h new file mode 100644 index 0000000..342557f --- /dev/null +++ b/include/configs/evb-rk3288.h @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS +#include <configs/rk3288_common.h> + +#define CONFIG_SPL_MMC_SUPPORT + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 +/* SPL @ 32k for ~36k + * ENV @ 96k + * u-boot @ 128K + */ +#define CONFIG_ENV_OFFSET (96 * 1024) + +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_CONSOLE_SCROLL_LINES 10 + +#endif diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h new file mode 100644 index 0000000..047850a --- /dev/null +++ b/include/configs/evb_rk3399.h @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __EVB_RK3399_H +#define __EVB_RK3399_H + +#include <configs/rk3399_common.h> + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +/* + * SPL @ 32k for ~36k + * ENV @ 96k + * u-boot @ 128K + */ +#define CONFIG_ENV_OFFSET (96 * 1024) + +#define SDRAM_BANK_SIZE (2UL << 30) + +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_CONSOLE_SCROLL_LINES 10 + +#endif diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index 953c088..2b172a5 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -61,6 +61,7 @@ #include "tegra-common-post.h" #define CONFIG_ARMV7_PSCI 1 +#define CONFIG_ARMV7_PSCI_NR_CPUS 4 /* Reserve top 1M for secure RAM */ #define CONFIG_ARMV7_SECURE_BASE 0xfff00000 #define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000 diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index f8bba67..71b0037 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -73,4 +73,10 @@ #define CONFIG_SF_DEFAULT_BUS 1 #define CONFIG_SF_DEFAULT_CS 0 +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CADENCE_QSPI +#define CONFIG_CQSPI_REF_CLK 384000000 +#define CONFIG_CQSPI_DECODER 0x0 +#endif + #endif /* __CONFIG_K2G_EVM_H */ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index db684d2..47180f9 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -10,6 +10,10 @@ #define CONFIG_LS102XA #define CONFIG_ARMV7_PSCI +#define CONFIG_ARMV7_PSCI_1_0 +#define CONFIG_ARMV7_PSCI_NR_CPUS CONFIG_MAX_CPUS + +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR #define CONFIG_SYS_FSL_CLK @@ -279,6 +283,8 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_LBMAP_SHIFT 0 #define QIXIS_LBMAP_DFLTBANK 0x00 #define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_PWR_CTL 0x21 +#define QIXIS_PWR_CTL_POWEROFF 0x80 #define QIXIS_RST_CTL_RESET 0x44 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 0fb28ef..2f19950 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -10,6 +10,10 @@ #define CONFIG_LS102XA #define CONFIG_ARMV7_PSCI +#define CONFIG_ARMV7_PSCI_1_0 +#define CONFIG_ARMV7_PSCI_NR_CPUS CONFIG_MAX_CPUS + +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR #define CONFIG_SYS_FSL_CLK @@ -123,7 +127,18 @@ #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) +/* + * HDR would be appended at end of image and copied to DDR along + * with U-Boot image. + */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS (0x400 + \ + (CONFIG_U_BOOT_HDR_SIZE / 512) +#else #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 +#endif /* ifdef CONFIG_SECURE_BOOT */ #define CONFIG_SPL_TEXT_BASE 0x10000000 #define CONFIG_SPL_MAX_SIZE 0x1a000 @@ -136,7 +151,18 @@ #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 + +#ifdef CONFIG_U_BOOT_HDR_SIZE +/* + * HDR would be appended at end of image and copied to DDR along + * with U-Boot image. Here u-boot max. size is 512K. So if binary + * size increases then increase this size in case of secure boot as + * it uses raw u-boot image instead of fit image. + */ +#define CONFIG_SYS_MONITOR_LEN (0x80000 + CONFIG_U_BOOT_HDR_SIZE) +#else #define CONFIG_SYS_MONITOR_LEN 0x80000 +#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ #endif #ifdef CONFIG_QSPI_BOOT diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index b0d4a8d..0ad5261 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -241,22 +241,37 @@ #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \ + "5m(kernel),1m(dtb),9m(file_system)" +#else +#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \ + "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ + "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ + "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ + "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ + "40m(nor_bank4_fit);7e800000.flash:" \ + "1m(nand_uboot),1m(nand_uboot_env)," \ + "20m(nand_fit);spi0.0:1m(uboot)," \ + "5m(kernel),1m(dtb),9m(file_system)" +#endif + /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x80100000\0" \ - "kernel_addr=0x100000\0" \ - "ramdisk_addr=0x800000\0" \ - "ramdisk_size=0x2000000\0" \ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_start=0x61100000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ - "console=ttyAMA0,38400n8\0" + "console=ttyS0,115200\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ - "earlycon=uart8250,mmio,0x21c0500" + "earlycon=uart8250,mmio,0x21c0500 " \ + MTDPARTS_DEFAULT + #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ "e0000 f00000 && bootm $kernel_load" diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 94ddfb1..44f86fa 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -9,6 +9,17 @@ #include "ls1043a_common.h" +#if defined(CONFIG_FSL_LS_PPA) +#define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#define SEC_FIRMWARE_ERET_ADDR_REVERT +#define CONFIG_ARMV8_PSCI + +#define CONFIG_SYS_LS_PPA_FW_IN_NOR +#ifdef CONFIG_SYS_LS_PPA_FW_IN_NOR +#define CONFIG_SYS_LS_PPA_FW_ADDR 0x60500000 +#endif +#endif + #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 93fb166..047e756 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -175,10 +175,6 @@ #define CONFIG_CMD_IRQ #define CONFIG_CMD_MFSL -#if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE) -#else -#endif - #if defined(FLASH) # define CONFIG_CMD_JFFS2 # define CONFIG_CMD_UBI diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 0882d5d..238b16d 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -120,7 +120,7 @@ #define CONFIG_PL011_CLOCK 24000000 #define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } #define CONFIG_CONS_INDEX 0 -/* Default baudrate can be overriden by board! */ +/* Default baudrate can be overridden by board! */ #ifndef CONFIG_BAUDRATE #define CONFIG_BAUDRATE 115200 #endif diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 9bd8915..e0d2593 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -10,11 +10,8 @@ #ifndef __IGEP00X0_H #define __IGEP00X0_H -#ifdef CONFIG_BOOT_NAND -#define CONFIG_NAND -#endif - #define CONFIG_NR_DRAM_BANKS 2 +#define CONFIG_NAND #include <configs/ti_omap3_common.h> #include <asm/mach-types.h> @@ -76,9 +73,9 @@ #define CONFIG_USBD_MANUFACTURER "Texas Instruments" #define CONFIG_USBD_PRODUCT_NAME "IGEP" -#ifdef CONFIG_BOOT_ONENAND -#define CONFIG_CMD_ONENAND /* ONENAND support */ -#endif +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_ONENAND +#define CONFIG_CMD_UBI #ifndef CONFIG_SPL_BUILD @@ -106,27 +103,6 @@ #endif /* - * FLASH and environment organization - */ - -#ifdef CONFIG_BOOT_ONENAND -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP - -#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ - -#define CONFIG_ENV_IS_IN_ONENAND 1 -#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ -#define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET -#endif - -#ifdef CONFIG_NAND -#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ -#define CONFIG_ENV_IS_IN_NAND 1 -#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ -#define CONFIG_ENV_ADDR NAND_ENV_OFFSET -#endif - -/* * SMSC911x Ethernet */ #if defined(CONFIG_CMD_NET) @@ -135,19 +111,19 @@ #define CONFIG_SMC911X_BASE 0x2C000000 #endif /* (CONFIG_CMD_NET) */ -/* OneNAND boot config */ -#ifdef CONFIG_BOOT_ONENAND -#define CONFIG_SPL_ONENAND_SUPPORT -#define CONFIG_SYS_ONENAND_U_BOOT_OFFS 0x80000 -#define CONFIG_SYS_ONENAND_PAGE_SIZE 2048 -#define CONFIG_SPL_ONENAND_LOAD_ADDR 0x80000 -#define CONFIG_SPL_ONENAND_LOAD_SIZE \ - (512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR) +#define CONFIG_RBTREE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_SYS_MTDPARTS_RUNTIME -#endif +/* OneNAND config */ +#define CONFIG_SPL_ONENAND_SUPPORT +#define CONFIG_USE_ONENAND_BOARD_INIT +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP +#define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024) -/* NAND boot config */ -#ifdef CONFIG_NAND +/* NAND config */ +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_OMAP3_ID_NAND #define CONFIG_SYS_NAND_BUSWIDTH_16BIT #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 @@ -168,13 +144,29 @@ #define CONFIG_NAND_OMAP_GPMC #define CONFIG_BCH -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 -/* NAND: SPL falcon mode configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_CMD_SPL_NAND_OFS 0x240000 -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 -#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 -#endif -#endif +/* UBI configuration */ +#define CONFIG_SPL_UBI 1 +#define CONFIG_SPL_UBI_MAX_VOL_LEBS 256 +#define CONFIG_SPL_UBI_MAX_PEB_SIZE (256*1024) +#define CONFIG_SPL_UBI_MAX_PEBS 4096 +#define CONFIG_SPL_UBI_VOL_IDS 8 +#define CONFIG_SPL_UBI_LOAD_MONITOR_ID 0 +#define CONFIG_SPL_UBI_LOAD_KERNEL_ID 3 +#define CONFIG_SPL_UBI_LOAD_ARGS_ID 4 +#define CONFIG_SPL_UBI_PEB_OFFSET 4 +#define CONFIG_SPL_UBI_VID_OFFSET 512 +#define CONFIG_SPL_UBI_LEB_START 2048 +#define CONFIG_SPL_UBI_INFO_ADDR 0x88080000 + +/* environment organization */ +#define CONFIG_ENV_IS_IN_UBI 1 +#define CONFIG_ENV_UBI_PART "UBI" +#define CONFIG_ENV_UBI_VOLUME "config" +#define CONFIG_ENV_UBI_VOLUME_REDUND "config_r" +#define CONFIG_UBI_SILENCE_MSG 1 +#define CONFIG_UBIFS_SILENCE_MSG 1 +#define CONFIG_ENV_SIZE (32*1024) + +#undef CONFIG_SPL_EXT_SUPPORT #endif /* __IGEP00X0_H */ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 4f22d12..3d33421 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -989,7 +989,7 @@ i2c mw 18 3 __SW_BOOT_MASK 1; reset "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ -"fdtaddr=c00000\0" \ +"fdtaddr=1e00000\0" \ "bdev=sda1\0" \ "jffs2nor=mtdblock3\0" \ "norbootaddr=ef080000\0" \ diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index 30bfbf4..79e4991 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -513,7 +513,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ -"fdtaddr=c00000\0" \ +"fdtaddr=1e00000\0" \ "bdev=sda1\0" \ "norbootaddr=ef080000\0" \ "norfdtaddr=ef040000\0" \ diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 1bdcf9d..ae4b101 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -45,7 +45,6 @@ /* MMC/SD IP block */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC -#define CONFIG_SDHCI #define CONFIG_DWMMC #define CONFIG_BOUNCE_BUFFER diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 9d50d83..2a36c17 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -33,7 +33,12 @@ #define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SPL_BOARD_INIT +#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +/* Bootrom will load u-boot binary to 0x0 once return from SPL */ +#define CONFIG_SYS_TEXT_BASE 0x00000000 +#else #define CONFIG_SYS_TEXT_BASE 0x00100000 +#endif #define CONFIG_SYS_INIT_SP_ADDR 0x00100000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 #define CONFIG_SPL_STACK 0xff718000 @@ -51,7 +56,6 @@ /* MMC/SD IP block */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC -#define CONFIG_SDHCI #define CONFIG_DWMMC #define CONFIG_BOUNCE_BUFFER @@ -80,6 +84,32 @@ #define CONFIG_SPI #define CONFIG_SF_DEFAULT_SPEED 20000000 +/* usb otg */ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_DWC2_OTG +#define CONFIG_ROCKCHIP_USB2_PHY +#define CONFIG_USB_GADGET_VBUS_DRAW 0 + +/* fastboot */ +#define CONFIG_CMD_FASTBOOT +#define CONFIG_USB_FUNCTION_FASTBOOT +#define CONFIG_FASTBOOT_FLASH +#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 /* eMMC */ +/* stroe safely fastboot buffer data to the middle of bank */ +#define CONFIG_FASTBOOT_BUF_ADDR (CONFIG_SYS_SDRAM_BASE \ + + SDRAM_BANK_SIZE / 2) +#define CONFIG_FASTBOOT_BUF_SIZE 0x08000000 + +#define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_G_DNL_MANUFACTURER "Rockchip" +#define CONFIG_G_DNL_VENDOR_NUM 0x2207 +#define CONFIG_G_DNL_PRODUCT_NUM 0x320a + +/* Enable gpt partition table */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION + #ifndef CONFIG_SPL_BUILD #include <config_distro_defaults.h> diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h new file mode 100644 index 0000000..6ce1aa7 --- /dev/null +++ b/include/configs/rk3399_common.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_RK3399_COMMON_H +#define __CONFIG_RK3399_COMMON_H + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_BAUDRATE 1500000 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_SYS_TEXT_BASE 0x00200000 +#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 +#define CONFIG_SYS_LOAD_ADDR 0x00800800 + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +/* MMC/SD IP block */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_SDHCI +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000 + +#define CONFIG_FAT_WRITE + +/* RAW SD card / eMMC locations. */ +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 256 +#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) + +/* FAT sd card locations. */ +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI +#define CONFIG_SF_DEFAULT_SPEED 20000000 + +#ifndef CONFIG_SPL_BUILD +#include <config_distro_defaults.h> + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00000000\0" \ + "pxefile_addr_r=0x00100000\0" \ + "fdt_addr_r=0x01f00000\0" \ + "kernel_addr_r=0x02000000\0" \ + "ramdisk_addr_r=0x04000000\0" + +/* First try to boot from SD (index 0), then eMMC (index 1) */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) + +#include <config_distro_bootcmd.h> +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV + +#endif + +#endif diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 23a0c40..94e024b 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -16,8 +16,10 @@ #endif +#ifndef CONFIG_SPL_BUILD #define CONFIG_IO_TRACE #define CONFIG_CMD_IOTRACE +#endif #ifndef CONFIG_TIMER #define CONFIG_SYS_TIMER_RATE 1000000 @@ -25,7 +27,10 @@ #define CONFIG_SYS_STDIO_DEREGISTER -/* Number of bits in a C 'long' on this architecture */ +/* + * Number of bits in a C 'long' on this architecture. Set this to 32 when + * building on a 32-bit machine. + */ #define CONFIG_SANDBOX_BITS_PER_LONG 64 #define CONFIG_LMB @@ -80,7 +85,6 @@ #define CONFIG_CMD_SF_TEST #define CONFIG_I2C_EDID -#define CONFIG_I2C_EEPROM /* Memory things - we don't really want a memory test */ #define CONFIG_SYS_LOAD_ADDR 0x00000000 @@ -192,6 +196,7 @@ #define CONFIG_CMD_LZMADEC #define CONFIG_CMD_DATE +#ifndef CONFIG_SPL_BUILD #define CONFIG_CMD_IDE #define CONFIG_SYS_IDE_MAXBUS 1 #define CONFIG_SYS_ATA_IDE0_OFFSET 0 @@ -201,6 +206,7 @@ #define CONFIG_SYS_ATA_REG_OFFSET 1 #define CONFIG_SYS_ATA_ALT_OFFSET 2 #define CONFIG_SYS_ATA_STRIDE 4 +#endif #define CONFIG_SCSI #define CONFIG_SCSI_AHCI_PLAT diff --git a/include/configs/sandbox_spl.h b/include/configs/sandbox_spl.h new file mode 100644 index 0000000..ffc3098 --- /dev/null +++ b/include/configs/sandbox_spl.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2016 Google, Inc + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SANDBOX_SPL_CONFIG_H +#define __SANDBOX_SPL_CONFIG_H + +#include <configs/sandbox.h> + +#define CONFIG_SPL_BOARD_INIT + +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#endif diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 46766a6..ec9ad45 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -595,7 +595,7 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=uRamdisk\0" \ -"fdtaddr=c00000\0" \ +"fdtaddr=1e00000\0" \ "fdtfile=sbc8548.dtb\0" #define CONFIG_NFSBOOTCOMMAND \ diff --git a/include/configs/som-db5800-som-6867.h b/include/configs/som-db5800-som-6867.h new file mode 100644 index 0000000..a4b343e --- /dev/null +++ b/include/configs/som-db5800-som-6867.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/x86-common.h> + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_ARCH_EARLY_INIT_R +#define CONFIG_ARCH_MISC_INIT + +#define CONFIG_PCI_PNP +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd,vga\0" \ + "stdout=serial,vga\0" \ + "stderr=serial,vga\0" + +#define CONFIG_SCSI_DEV_LIST \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT} + +#define VIDEO_IO_OFFSET 0 +#define CONFIG_X86EMU_RAW_IO + +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_OFFSET 0x006ef000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index e544a21..4391bff 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -24,13 +24,13 @@ * Configuration of the external SDRAM memory */ #define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_RAM_SIZE ((64 + 192) << 10) +#define CONFIG_SYS_RAM_SIZE (8 * 1024 * 1024) #define CONFIG_SYS_RAM_CS 1 #define CONFIG_SYS_RAM_FREQ_DIV 2 -#define CONFIG_SYS_RAM_BASE 0x20000000 +#define CONFIG_SYS_RAM_BASE 0xC0000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE -#define CONFIG_SYS_LOAD_ADDR 0x20000000 -#define CONFIG_LOADADDR 0x20000000 +#define CONFIG_SYS_LOAD_ADDR 0xC0400000 +#define CONFIG_LOADADDR 0xC0400000 #define CONFIG_SYS_MAX_FLASH_SECT 8 #define CONFIG_SYS_MAX_FLASH_BANKS 1 @@ -42,7 +42,8 @@ #define CONFIG_STM32_FLASH #define CONFIG_STM32X7_SERIAL -#define CONFIG_SYS_CLK_FREQ 16*1000*1000 /* 180 MHz */ +#define CONFIG_STM32_HSE_HZ 25000000 +#define CONFIG_SYS_CLK_FREQ 200000000 /* 200 MHz */ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ #define CONFIG_CMDLINE_TAG diff --git a/include/configs/sun6i.h b/include/configs/sun6i.h index 95ccc35..0625502 100644 --- a/include/configs/sun6i.h +++ b/include/configs/sun6i.h @@ -25,6 +25,7 @@ #define CONFIG_ARMV7_PSCI 1 #define CONFIG_ARMV7_PSCI_NR_CPUS 4 #define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE +#define CONFIG_ARMV7_SECURE_MAX_SIZE (64 * 1024) /* 64 KB */ /* * Include common sunxi configuration where most the settings are diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h index 0dd2902..e9074d5 100644 --- a/include/configs/sun7i.h +++ b/include/configs/sun7i.h @@ -21,7 +21,9 @@ #define CONFIG_SUNXI_USB_PHYS 3 #define CONFIG_ARMV7_PSCI 1 +#define CONFIG_ARMV7_PSCI_NR_CPUS 2 #define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE +#define CONFIG_ARMV7_SECURE_MAX_SIZE (64 * 1024) /* 64 KB */ /* * Include common sunxi configuration where most the settings are diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 94275a7..b9aa62b 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -134,7 +134,15 @@ #define CONFIG_SERIAL_TAG #ifdef CONFIG_NAND_SUNXI +#define CONFIG_SYS_NAND_MAX_ECCPOS 1664 #define CONFIG_SPL_NAND_SUPPORT 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_MAX_NAND_DEVICE 8 +#endif + +#ifdef CONFIG_SPL_SPI_SUNXI +#define CONFIG_SPL_SPI_FLASH_SUPPORT 1 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 #endif /* mmc config */ diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index ba7cf15..9f947ee 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -108,9 +108,25 @@ /* Timer information. */ #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +/* + * Disable DM_* for SPL build and can be re-enabled after adding + * DM support in SPL + */ +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_DM_I2C +#endif + /* I2C IP block */ #define CONFIG_I2C +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C +#else +/* + * Enable CONFIG_DM_I2C_COMPAT temporarily until all the i2c client + * devices are adopted to DM + */ +#define CONFIG_DM_I2C_COMPAT +#endif /* MMC/SD IP block */ #define CONFIG_MMC diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 2ee26c4..4aa262e 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -89,6 +89,10 @@ #define CONFIG_SYS_SPI2 #define CONFIG_SYS_SPI2_BASE KS2_SPI2_BASE #define CONFIG_SYS_SPI2_NUM_CS 4 +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH +#endif /* Network Configuration */ #define CONFIG_PHYLIB diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 4ebaf84..e485583 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -9,7 +9,6 @@ #ifndef __CONFIG_UNIPHIER_COMMON_H__ #define __CONFIG_UNIPHIER_COMMON_H__ -#define CONFIG_I2C_EEPROM #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 #define CONFIG_SMC911X @@ -226,7 +225,6 @@ "run boot_common\0" \ "__nfsboot=tftpboot $kernel_addr_r $bootfile &&" \ "tftpboot $fdt_addr_r $fdt_file &&" \ - "tftpboot $fdt_addr_r $fdt_file &&" \ "setenv ramdisk_addr_r - &&" \ "run boot_common\0" #endif diff --git a/include/configs/v38b.h b/include/configs/v38b.h index 28c748d..5ebdf5b 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -55,7 +55,7 @@ #define SDRAM_TAPDELAY 0x10000000 /* - * PCI - no suport + * PCI - no support */ #undef CONFIG_PCI diff --git a/include/configs/vexpress_ca15_tc2.h b/include/configs/vexpress_ca15_tc2.h index b509a9c..9583e8c 100644 --- a/include/configs/vexpress_ca15_tc2.h +++ b/include/configs/vexpress_ca15_tc2.h @@ -16,5 +16,6 @@ #define CONFIG_SYSFLAGS_ADDR 0x1c010030 #define CONFIG_SMP_PEN_ADDR CONFIG_SYSFLAGS_ADDR +#define CONFIG_ARMV7_PSCI_NR_CPUS 4 #endif diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h index c5bd5da..44434aa 100644 --- a/include/configs/xilinx_zynqmp_ep.h +++ b/include/configs/xilinx_zynqmp_ep.h @@ -17,6 +17,7 @@ #define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ << 9) #define CONFIG_ZYNQ_EEPROM #define CONFIG_AHCI +#define CONFIG_SATA_CEVA #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \ ZYNQMP_USB1_XHCI_BASEADDR} diff --git a/include/configs/xpedite1000.h b/include/configs/xpedite1000.h index 73c8d5b..bc91714 100644 --- a/include/configs/xpedite1000.h +++ b/include/configs/xpedite1000.h @@ -304,7 +304,7 @@ extern void out32(unsigned int, unsigned long); "osfile=/home/user/board.uImage\0" \ "fdtfile=/home/user/board.dtb\0" \ "ubootfile=/home/user/u-boot.bin\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=0x1e00000\0" \ "osaddr=0x1000000\0" \ "loadaddr=0x1000000\0" \ "prog_uboot="CONFIG_PROG_UBOOT"\0" \ diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h index 9f3158d..eaea33b 100644 --- a/include/configs/xpedite517x.h +++ b/include/configs/xpedite517x.h @@ -699,7 +699,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); "osfile=/home/user/board.uImage\0" \ "fdtfile=/home/user/board.dtb\0" \ "ubootfile=/home/user/u-boot.bin\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=0x1e00000\0" \ "osaddr=0x1000000\0" \ "loadaddr=0x1000000\0" \ "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h index a418fc5..f7cfc9e 100644 --- a/include/configs/xpedite520x.h +++ b/include/configs/xpedite520x.h @@ -483,7 +483,7 @@ "osfile=/home/user/board.uImage\0" \ "fdtfile=/home/user/board.dtb\0" \ "ubootfile=/home/user/u-boot.bin\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=0x1e00000\0" \ "osaddr=0x1000000\0" \ "loadaddr=0x1000000\0" \ "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index 36df668..3306e44a 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -554,7 +554,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); "osfile=/home/user/board.uImage\0" \ "fdtfile=/home/user/board.dtb\0" \ "ubootfile=/home/user/u-boot.bin\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=0x1e00000\0" \ "osaddr=0x1000000\0" \ "loadaddr=0x1000000\0" \ "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 1794ba1..276dde7 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -538,7 +538,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); "osfile=/home/user/board.uImage\0" \ "fdtfile=/home/user/board.dtb\0" \ "ubootfile=/home/user/u-boot.bin\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=0x1e00000\0" \ "osaddr=0x1000000\0" \ "loadaddr=0x1000000\0" \ "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 8dbac87..e59e412 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -86,10 +86,7 @@ # define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000 #endif -#ifdef CONFIG_ZYNQ_USB -# define CONFIG_USB_EHCI -# define CONFIG_USB_STORAGE -# define CONFIG_USB_EHCI_ZYNQ +#ifdef CONFIG_USB_EHCI_ZYNQ # define CONFIG_EHCI_IS_TDI # define CONFIG_USB_MAX_CONTROLLER_COUNT 2 diff --git a/include/configs/zynq_microzed.h b/include/configs/zynq_microzed.h deleted file mode 100644 index ec7bb1c..0000000 --- a/include/configs/zynq_microzed.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * (C) Copyright 2013 Xilinx, Inc. - * - * Configuration for Micro Zynq Evaluation and Development Board - MicroZedBoard - * See zynq-common.h for Zynq common configs - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_ZYNQ_MICROZED_H -#define __CONFIG_ZYNQ_MICROZED_H - -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_ZYNQ_USB - -#include <configs/zynq-common.h> - -#endif /* __CONFIG_ZYNQ_MICROZED_H */ diff --git a/include/configs/zynq_picozed.h b/include/configs/zynq_picozed.h deleted file mode 100644 index adc4d0f..0000000 --- a/include/configs/zynq_picozed.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * (C) Copyright 2015 Xilinx, Inc. - * - * Configuration for PicoZed - * See zynq-common.h for Zynq common configs - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_ZYNQ_PICOZED_H -#define __CONFIG_ZYNQ_PICOZED_H - -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_ZYNQ_USB - -#include <configs/zynq-common.h> - -#endif /* __CONFIG_ZYNQ_PICOZED_H */ diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h index 8a04590..fc46fec 100644 --- a/include/configs/zynq_zc70x.h +++ b/include/configs/zynq_zc70x.h @@ -10,9 +10,6 @@ #ifndef __CONFIG_ZYNQ_ZC70X_H #define __CONFIG_ZYNQ_ZC70X_H -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_ZYNQ_USB #define CONFIG_ZYNQ_I2C0 #define CONFIG_ZYNQ_EEPROM diff --git a/include/configs/zynq_zc770.h b/include/configs/zynq_zc770.h deleted file mode 100644 index 35622ae..0000000 --- a/include/configs/zynq_zc770.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * (C) Copyright 2013 Xilinx, Inc. - * - * Configuration settings for the Xilinx Zynq ZC770 board. - * See zynq-common.h for Zynq common configs - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_ZYNQ_ZC770_H -#define __CONFIG_ZYNQ_ZC770_H - -#define CONFIG_SYS_NO_FLASH - -#if defined(CONFIG_ZC770_XM012) -# undef CONFIG_SYS_NO_FLASH - -#endif - -#include <configs/zynq-common.h> - -#endif /* __CONFIG_ZYNQ_ZC770_H */ diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h deleted file mode 100644 index 150cb4a..0000000 --- a/include/configs/zynq_zed.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * (C) Copyright 2013 Xilinx, Inc. - * - * Configuration for Zynq Evaluation and Development Board - ZedBoard - * See zynq-common.h for Zynq common configs - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_ZYNQ_ZED_H -#define __CONFIG_ZYNQ_ZED_H - -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_ZYNQ_USB - -#include <configs/zynq-common.h> - -#endif /* __CONFIG_ZYNQ_ZED_H */ diff --git a/include/configs/zynq_zybo.h b/include/configs/zynq_zybo.h index 637b1c5..b9ff391 100644 --- a/include/configs/zynq_zybo.h +++ b/include/configs/zynq_zybo.h @@ -11,9 +11,6 @@ #ifndef __CONFIG_ZYNQ_ZYBO_H #define __CONFIG_ZYNQ_ZYBO_H -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_ZYNQ_USB #define CONFIG_ZYNQ_I2C0 #define CONFIG_ZYNQ_I2C1 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 diff --git a/include/dm/device.h b/include/dm/device.h index f03bcd3..705849b 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -42,7 +42,9 @@ struct driver_info; #define DM_FLAG_BOUND (1 << 6) /* Device name is allocated and should be freed on unbind() */ -#define DM_NAME_ALLOCED (1 << 7) +#define DM_FLAG_NAME_ALLOCED (1 << 7) + +#define DM_FLAG_OF_PLATDATA (1 << 8) /** * struct udevice - An instance of a driver @@ -205,6 +207,10 @@ struct driver { #define U_BOOT_DRIVER(__name) \ ll_entry_declare(struct driver, __name, driver) +/* Get a pointer to a given driver */ +#define DM_GET_DRIVER(__name) \ + ll_entry_get(struct driver, __name, driver) + /** * dev_get_platdata() - Get the platform data for a device * @@ -467,6 +473,19 @@ fdt_addr_t dev_get_addr(struct udevice *dev); void *dev_get_addr_ptr(struct udevice *dev); /** + * dev_map_physmem() - Read device address from reg property of the + * device node and map the address into CPU address + * space. + * + * @dev: Pointer to device + * @size: size of the memory to map + * + * @return mapped address, or NULL if the device does not have reg + * property. + */ +void *dev_map_physmem(struct udevice *dev, unsigned long size); + +/** * dev_get_addr_index() - Get the indexed reg property of a device * * @dev: Pointer to a device @@ -540,7 +559,7 @@ int device_set_name(struct udevice *dev, const char *name); /** * device_set_name_alloced() - note that a device name is allocated * - * This sets the DM_NAME_ALLOCED flag for the device, so that when it is + * This sets the DM_FLAG_NAME_ALLOCED flag for the device, so that when it is * unbound the name will be freed. This avoids memory leaks. * * @dev: Device to update diff --git a/include/dm/platdata.h b/include/dm/platdata.h index 6f4f001..488b2ab 100644 --- a/include/dm/platdata.h +++ b/include/dm/platdata.h @@ -22,10 +22,15 @@ * * @name: Driver name * @platdata: Driver-specific platform data + * @platdata_size: Size of platform data structure + * @flags: Platform data flags (DM_FLAG_...) */ struct driver_info { const char *name; const void *platdata; +#if CONFIG_IS_ENABLED(OF_PLATDATA) + uint platdata_size; +#endif }; /** diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index b768660..c5cdfc7 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -33,7 +33,6 @@ enum uclass_id { UCLASS_CROS_EC, /* Chrome OS EC */ UCLASS_DISPLAY, /* Display (e.g. DisplayPort, HDMI) */ UCLASS_DMA, /* Direct Memory Access */ - UCLASS_RAM, /* RAM controller */ UCLASS_ETH, /* Ethernet device */ UCLASS_GPIO, /* Bank of general-purpose I/O pins */ UCLASS_I2C, /* I2C bus */ @@ -56,11 +55,12 @@ enum uclass_id { UCLASS_PCH, /* x86 platform controller hub */ UCLASS_PCI, /* PCI bus */ UCLASS_PCI_GENERIC, /* Generic PCI bus device */ - UCLASS_PINCTRL, /* Pinctrl (pin muxing/configuration) device */ UCLASS_PINCONFIG, /* Pin configuration node device */ + UCLASS_PINCTRL, /* Pinctrl (pin muxing/configuration) device */ UCLASS_PMIC, /* PMIC I/O device */ UCLASS_PWM, /* Pulse-width modulator */ UCLASS_PWRSEQ, /* Power sequence device */ + UCLASS_RAM, /* RAM controller */ UCLASS_REGULATOR, /* Regulator device */ UCLASS_REMOTEPROC, /* Remote Processor device */ UCLASS_RESET, /* Reset controller device */ diff --git a/include/dm/uclass.h b/include/dm/uclass.h index fd368b6..84f05bc 100644 --- a/include/dm/uclass.h +++ b/include/dm/uclass.h @@ -38,6 +38,7 @@ struct uclass { struct list_head sibling_node; }; +struct driver; struct udevice; /* Members of this uclass sequence themselves with aliases */ @@ -194,6 +195,23 @@ int uclass_get_device_by_phandle(enum uclass_id id, struct udevice *parent, const char *name, struct udevice **devp); /** + * uclass_get_device_by_driver() - Get a uclass device for a driver + * + * This searches the devices in the uclass for one that uses the given + * driver. Use DM_GET_DRIVER(name) for the @drv argument, where 'name' is + * the driver name - as used in U_BOOT_DRIVER(name). + * + * The device is probed to activate it ready for use. + * + * @id: ID to look up + * @drv: Driver to look for + * @devp: Returns pointer to the first device with that driver + * @return 0 if OK, -ve on error + */ +int uclass_get_device_by_driver(enum uclass_id id, const struct driver *drv, + struct udevice **devp); + +/** * uclass_first_device() - Get the first device in a uclass * * The device returned is probed if necessary, and ready for use diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h new file mode 100644 index 0000000..0a86aec --- /dev/null +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -0,0 +1,746 @@ +/* + * Copyright (c) 2016 Rockchip Electronics Co. Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H + +/* core clocks */ +#define PLL_APLLL 1 +#define PLL_APLLB 2 +#define PLL_DPLL 3 +#define PLL_CPLL 4 +#define PLL_GPLL 5 +#define PLL_NPLL 6 +#define PLL_VPLL 7 +#define ARMCLKL 8 +#define ARMCLKB 9 + +/* sclk gates (special clocks) */ +#define SCLK_I2C1 65 +#define SCLK_I2C2 66 +#define SCLK_I2C3 67 +#define SCLK_I2C5 68 +#define SCLK_I2C6 69 +#define SCLK_I2C7 70 +#define SCLK_SPI0 71 +#define SCLK_SPI1 72 +#define SCLK_SPI2 73 +#define SCLK_SPI4 74 +#define SCLK_SPI5 75 +#define SCLK_SDMMC 76 +#define SCLK_SDIO 77 +#define SCLK_EMMC 78 +#define SCLK_TSADC 79 +#define SCLK_SARADC 80 +#define SCLK_UART0 81 +#define SCLK_UART1 82 +#define SCLK_UART2 83 +#define SCLK_UART3 84 +#define SCLK_SPDIF_8CH 85 +#define SCLK_I2S0_8CH 86 +#define SCLK_I2S1_8CH 87 +#define SCLK_I2S2_8CH 88 +#define SCLK_I2S_8CH_OUT 89 +#define SCLK_TIMER00 90 +#define SCLK_TIMER01 91 +#define SCLK_TIMER02 92 +#define SCLK_TIMER03 93 +#define SCLK_TIMER04 94 +#define SCLK_TIMER05 95 +#define SCLK_TIMER06 96 +#define SCLK_TIMER07 97 +#define SCLK_TIMER08 98 +#define SCLK_TIMER09 99 +#define SCLK_TIMER10 100 +#define SCLK_TIMER11 101 +#define SCLK_MACREF 102 +#define SCLK_MAC_RX 103 +#define SCLK_MAC_TX 104 +#define SCLK_MAC 105 +#define SCLK_MACREF_OUT 106 +#define SCLK_VOP0_PWM 107 +#define SCLK_VOP1_PWM 108 +#define SCLK_RGA_CORE 109 +#define SCLK_ISP0 110 +#define SCLK_ISP1 111 +#define SCLK_HDMI_CEC 112 +#define SCLK_HDMI_SFR 113 +#define SCLK_DP_CORE 114 +#define SCLK_PVTM_CORE_L 115 +#define SCLK_PVTM_CORE_B 116 +#define SCLK_PVTM_GPU 117 +#define SCLK_PVTM_DDR 118 +#define SCLK_MIPIDPHY_REF 119 +#define SCLK_MIPIDPHY_CFG 120 +#define SCLK_HSICPHY 121 +#define SCLK_USBPHY480M 122 +#define SCLK_USB2PHY0_REF 123 +#define SCLK_USB2PHY1_REF 124 +#define SCLK_UPHY0_TCPDPHY_REF 125 +#define SCLK_UPHY0_TCPDCORE 126 +#define SCLK_UPHY1_TCPDPHY_REF 127 +#define SCLK_UPHY1_TCPDCORE 128 +#define SCLK_USB3OTG0_REF 129 +#define SCLK_USB3OTG1_REF 130 +#define SCLK_USB3OTG0_SUSPEND 131 +#define SCLK_USB3OTG1_SUSPEND 132 +#define SCLK_CRYPTO0 133 +#define SCLK_CRYPTO1 134 +#define SCLK_CCI_TRACE 135 +#define SCLK_CS 136 +#define SCLK_CIF_OUT 137 +#define SCLK_PCIEPHY_REF 138 +#define SCLK_PCIE_CORE 139 +#define SCLK_M0_PERILP 140 +#define SCLK_M0_PERILP_DEC 141 +#define SCLK_CM0S 142 +#define SCLK_DBG_NOC 143 +#define SCLK_DBG_PD_CORE_B 144 +#define SCLK_DBG_PD_CORE_L 145 +#define SCLK_DFIMON0_TIMER 146 +#define SCLK_DFIMON1_TIMER 147 +#define SCLK_INTMEM0 148 +#define SCLK_INTMEM1 149 +#define SCLK_INTMEM2 150 +#define SCLK_INTMEM3 151 +#define SCLK_INTMEM4 152 +#define SCLK_INTMEM5 153 +#define SCLK_SDMMC_DRV 154 +#define SCLK_SDMMC_SAMPLE 155 +#define SCLK_SDIO_DRV 156 +#define SCLK_SDIO_SAMPLE 157 +#define SCLK_VDU_CORE 158 +#define SCLK_VDU_CA 159 +#define SCLK_PCIE_PM 160 +#define SCLK_SPDIF_REC_DPTX 161 +#define SCLK_DPHY_PLL 162 +#define SCLK_DPHY_TX0_CFG 163 +#define SCLK_DPHY_TX1RX1_CFG 164 +#define SCLK_DPHY_RX0_CFG 165 +#define SCLK_RMII_SRC 166 +#define SCLK_PCIEPHY_REF100M 167 + +#define DCLK_VOP0 180 +#define DCLK_VOP1 181 +#define DCLK_VOP0_DIV 182 +#define DCLK_VOP1_DIV 183 +#define DCLK_M0_PERILP 184 + +#define FCLK_CM0S 190 + +/* aclk gates */ +#define ACLK_PERIHP 192 +#define ACLK_PERIHP_NOC 193 +#define ACLK_PERILP0 194 +#define ACLK_PERILP0_NOC 195 +#define ACLK_PERF_PCIE 196 +#define ACLK_PCIE 197 +#define ACLK_INTMEM 198 +#define ACLK_TZMA 199 +#define ACLK_DCF 200 +#define ACLK_CCI 201 +#define ACLK_CCI_NOC0 202 +#define ACLK_CCI_NOC1 203 +#define ACLK_CCI_GRF 204 +#define ACLK_CENTER 205 +#define ACLK_CENTER_MAIN_NOC 206 +#define ACLK_CENTER_PERI_NOC 207 +#define ACLK_GPU 208 +#define ACLK_PERF_GPU 209 +#define ACLK_GPU_GRF 210 +#define ACLK_DMAC0_PERILP 211 +#define ACLK_DMAC1_PERILP 212 +#define ACLK_GMAC 213 +#define ACLK_GMAC_NOC 214 +#define ACLK_PERF_GMAC 215 +#define ACLK_VOP0_NOC 216 +#define ACLK_VOP0 217 +#define ACLK_VOP1_NOC 218 +#define ACLK_VOP1 219 +#define ACLK_RGA 220 +#define ACLK_RGA_NOC 221 +#define ACLK_HDCP 222 +#define ACLK_HDCP_NOC 223 +#define ACLK_HDCP22 224 +#define ACLK_IEP 225 +#define ACLK_IEP_NOC 226 +#define ACLK_VIO 227 +#define ACLK_VIO_NOC 228 +#define ACLK_ISP0 229 +#define ACLK_ISP1 230 +#define ACLK_ISP0_NOC 231 +#define ACLK_ISP1_NOC 232 +#define ACLK_ISP0_WRAPPER 233 +#define ACLK_ISP1_WRAPPER 234 +#define ACLK_VCODEC 235 +#define ACLK_VCODEC_NOC 236 +#define ACLK_VDU 237 +#define ACLK_VDU_NOC 238 +#define ACLK_PERI 239 +#define ACLK_EMMC 240 +#define ACLK_EMMC_CORE 241 +#define ACLK_EMMC_NOC 242 +#define ACLK_EMMC_GRF 243 +#define ACLK_USB3 244 +#define ACLK_USB3_NOC 245 +#define ACLK_USB3OTG0 246 +#define ACLK_USB3OTG1 247 +#define ACLK_USB3_RKSOC_AXI_PERF 248 +#define ACLK_USB3_GRF 249 +#define ACLK_GIC 250 +#define ACLK_GIC_NOC 251 +#define ACLK_GIC_ADB400_CORE_L_2_GIC 252 +#define ACLK_GIC_ADB400_CORE_B_2_GIC 253 +#define ACLK_GIC_ADB400_GIC_2_CORE_L 254 +#define ACLK_GIC_ADB400_GIC_2_CORE_B 255 +#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256 +#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257 +#define ACLK_ADB400M_PD_CORE_L 258 +#define ACLK_ADB400M_PD_CORE_B 259 +#define ACLK_PERF_CORE_L 260 +#define ACLK_PERF_CORE_B 261 +#define ACLK_GIC_PRE 262 +#define ACLK_VOP0_PRE 263 +#define ACLK_VOP1_PRE 264 + +/* pclk gates */ +#define PCLK_PERIHP 320 +#define PCLK_PERIHP_NOC 321 +#define PCLK_PERILP0 322 +#define PCLK_PERILP1 323 +#define PCLK_PERILP1_NOC 324 +#define PCLK_PERILP_SGRF 325 +#define PCLK_PERIHP_GRF 326 +#define PCLK_PCIE 327 +#define PCLK_SGRF 328 +#define PCLK_INTR_ARB 329 +#define PCLK_CENTER_MAIN_NOC 330 +#define PCLK_CIC 331 +#define PCLK_COREDBG_B 332 +#define PCLK_COREDBG_L 333 +#define PCLK_DBG_CXCS_PD_CORE_B 334 +#define PCLK_DCF 335 +#define PCLK_GPIO2 336 +#define PCLK_GPIO3 337 +#define PCLK_GPIO4 338 +#define PCLK_GRF 339 +#define PCLK_HSICPHY 340 +#define PCLK_I2C1 341 +#define PCLK_I2C2 342 +#define PCLK_I2C3 343 +#define PCLK_I2C5 344 +#define PCLK_I2C6 345 +#define PCLK_I2C7 346 +#define PCLK_SPI0 347 +#define PCLK_SPI1 348 +#define PCLK_SPI2 349 +#define PCLK_SPI4 350 +#define PCLK_SPI5 351 +#define PCLK_UART0 352 +#define PCLK_UART1 353 +#define PCLK_UART2 354 +#define PCLK_UART3 355 +#define PCLK_TSADC 356 +#define PCLK_SARADC 357 +#define PCLK_GMAC 358 +#define PCLK_GMAC_NOC 359 +#define PCLK_TIMER0 360 +#define PCLK_TIMER1 361 +#define PCLK_EDP 362 +#define PCLK_EDP_NOC 363 +#define PCLK_EDP_CTRL 364 +#define PCLK_VIO 365 +#define PCLK_VIO_NOC 366 +#define PCLK_VIO_GRF 367 +#define PCLK_MIPI_DSI0 368 +#define PCLK_MIPI_DSI1 369 +#define PCLK_HDCP 370 +#define PCLK_HDCP_NOC 371 +#define PCLK_HDMI_CTRL 372 +#define PCLK_DP_CTRL 373 +#define PCLK_HDCP22 374 +#define PCLK_GASKET 375 +#define PCLK_DDR 376 +#define PCLK_DDR_MON 377 +#define PCLK_DDR_SGRF 378 +#define PCLK_ISP1_WRAPPER 379 +#define PCLK_WDT 380 +#define PCLK_EFUSE1024NS 381 +#define PCLK_EFUSE1024S 382 +#define PCLK_PMU_INTR_ARB 383 +#define PCLK_MAILBOX0 384 +#define PCLK_USBPHY_MUX_G 385 +#define PCLK_UPHY0_TCPHY_G 386 +#define PCLK_UPHY0_TCPD_G 387 +#define PCLK_UPHY1_TCPHY_G 388 +#define PCLK_UPHY1_TCPD_G 389 +#define PCLK_ALIVE 390 + +/* hclk gates */ +#define HCLK_PERIHP 448 +#define HCLK_PERILP0 449 +#define HCLK_PERILP1 450 +#define HCLK_PERILP0_NOC 451 +#define HCLK_PERILP1_NOC 452 +#define HCLK_M0_PERILP 453 +#define HCLK_M0_PERILP_NOC 454 +#define HCLK_AHB1TOM 455 +#define HCLK_HOST0 456 +#define HCLK_HOST0_ARB 457 +#define HCLK_HOST1 458 +#define HCLK_HOST1_ARB 459 +#define HCLK_HSIC 460 +#define HCLK_SD 461 +#define HCLK_SDMMC 462 +#define HCLK_SDMMC_NOC 463 +#define HCLK_M_CRYPTO0 464 +#define HCLK_M_CRYPTO1 465 +#define HCLK_S_CRYPTO0 466 +#define HCLK_S_CRYPTO1 467 +#define HCLK_I2S0_8CH 468 +#define HCLK_I2S1_8CH 469 +#define HCLK_I2S2_8CH 470 +#define HCLK_SPDIF 471 +#define HCLK_VOP0_NOC 472 +#define HCLK_VOP0 473 +#define HCLK_VOP1_NOC 474 +#define HCLK_VOP1 475 +#define HCLK_ROM 476 +#define HCLK_IEP 477 +#define HCLK_IEP_NOC 478 +#define HCLK_ISP0 479 +#define HCLK_ISP1 480 +#define HCLK_ISP0_NOC 481 +#define HCLK_ISP1_NOC 482 +#define HCLK_ISP0_WRAPPER 483 +#define HCLK_ISP1_WRAPPER 484 +#define HCLK_RGA 485 +#define HCLK_RGA_NOC 486 +#define HCLK_HDCP 487 +#define HCLK_HDCP_NOC 488 +#define HCLK_HDCP22 489 +#define HCLK_VCODEC 490 +#define HCLK_VCODEC_NOC 491 +#define HCLK_VDU 492 +#define HCLK_VDU_NOC 493 +#define HCLK_SDIO 494 +#define HCLK_SDIO_NOC 495 +#define HCLK_SDIOAUDIO_NOC 496 + +#define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1) + +/* pmu-clocks indices */ + +#define PLL_PPLL 1 + +#define SCLK_32K_SUSPEND_PMU 2 +#define SCLK_SPI3_PMU 3 +#define SCLK_TIMER12_PMU 4 +#define SCLK_TIMER13_PMU 5 +#define SCLK_UART4_PMU 6 +#define SCLK_PVTM_PMU 7 +#define SCLK_WIFI_PMU 8 +#define SCLK_I2C0_PMU 9 +#define SCLK_I2C4_PMU 10 +#define SCLK_I2C8_PMU 11 + +#define PCLK_SRC_PMU 19 +#define PCLK_PMU 20 +#define PCLK_PMUGRF_PMU 21 +#define PCLK_INTMEM1_PMU 22 +#define PCLK_GPIO0_PMU 23 +#define PCLK_GPIO1_PMU 24 +#define PCLK_SGRF_PMU 25 +#define PCLK_NOC_PMU 26 +#define PCLK_I2C0_PMU 27 +#define PCLK_I2C4_PMU 28 +#define PCLK_I2C8_PMU 29 +#define PCLK_RKPWM_PMU 30 +#define PCLK_SPI3_PMU 31 +#define PCLK_TIMER_PMU 32 +#define PCLK_MAILBOX_PMU 33 +#define PCLK_UART4_PMU 34 +#define PCLK_WDT_M0_PMU 35 + +#define FCLK_CM0S_SRC_PMU 44 +#define FCLK_CM0S_PMU 45 +#define SCLK_CM0S_PMU 46 +#define HCLK_CM0S_PMU 47 +#define DCLK_CM0S_PMU 48 +#define PCLK_INTR_ARB_PMU 49 +#define HCLK_NOC_PMU 50 + +#define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1) + +/* soft-reset indices */ + +/* cru_softrst_con0 */ +#define SRST_CORE_L0 0 +#define SRST_CORE_B0 1 +#define SRST_CORE_PO_L0 2 +#define SRST_CORE_PO_B0 3 +#define SRST_L2_L 4 +#define SRST_L2_B 5 +#define SRST_ADB_L 6 +#define SRST_ADB_B 7 +#define SRST_A_CCI 8 +#define SRST_A_CCIM0_NOC 9 +#define SRST_A_CCIM1_NOC 10 +#define SRST_DBG_NOC 11 + +/* cru_softrst_con1 */ +#define SRST_CORE_L0_T 16 +#define SRST_CORE_L1 17 +#define SRST_CORE_L2 18 +#define SRST_CORE_L3 19 +#define SRST_CORE_PO_L0_T 20 +#define SRST_CORE_PO_L1 21 +#define SRST_CORE_PO_L2 22 +#define SRST_CORE_PO_L3 23 +#define SRST_A_ADB400_GIC2COREL 24 +#define SRST_A_ADB400_COREL2GIC 25 +#define SRST_P_DBG_L 26 +#define SRST_L2_L_T 28 +#define SRST_ADB_L_T 29 +#define SRST_A_RKPERF_L 30 +#define SRST_PVTM_CORE_L 31 + +/* cru_softrst_con2 */ +#define SRST_CORE_B0_T 32 +#define SRST_CORE_B1 33 +#define SRST_CORE_PO_B0_T 36 +#define SRST_CORE_PO_B1 37 +#define SRST_A_ADB400_GIC2COREB 40 +#define SRST_A_ADB400_COREB2GIC 41 +#define SRST_P_DBG_B 42 +#define SRST_L2_B_T 43 +#define SRST_ADB_B_T 45 +#define SRST_A_RKPERF_B 46 +#define SRST_PVTM_CORE_B 47 + +/* cru_softrst_con3 */ +#define SRST_A_CCI_T 50 +#define SRST_A_CCIM0_NOC_T 51 +#define SRST_A_CCIM1_NOC_T 52 +#define SRST_A_ADB400M_PD_CORE_B_T 53 +#define SRST_A_ADB400M_PD_CORE_L_T 54 +#define SRST_DBG_NOC_T 55 +#define SRST_DBG_CXCS 56 +#define SRST_CCI_TRACE 57 +#define SRST_P_CCI_GRF 58 + +/* cru_softrst_con4 */ +#define SRST_A_CENTER_MAIN_NOC 64 +#define SRST_A_CENTER_PERI_NOC 65 +#define SRST_P_CENTER_MAIN 66 +#define SRST_P_DDRMON 67 +#define SRST_P_CIC 68 +#define SRST_P_CENTER_SGRF 69 +#define SRST_DDR0_MSCH 70 +#define SRST_DDRCFG0_MSCH 71 +#define SRST_DDR0 72 +#define SRST_DDRPHY0 73 +#define SRST_DDR1_MSCH 74 +#define SRST_DDRCFG1_MSCH 75 +#define SRST_DDR1 76 +#define SRST_DDRPHY1 77 +#define SRST_DDR_CIC 78 +#define SRST_PVTM_DDR 79 + +/* cru_softrst_con5 */ +#define SRST_A_VCODEC_NOC 80 +#define SRST_A_VCODEC 81 +#define SRST_H_VCODEC_NOC 82 +#define SRST_H_VCODEC 83 +#define SRST_A_VDU_NOC 88 +#define SRST_A_VDU 89 +#define SRST_H_VDU_NOC 90 +#define SRST_H_VDU 91 +#define SRST_VDU_CORE 92 +#define SRST_VDU_CA 93 + +/* cru_softrst_con6 */ +#define SRST_A_IEP_NOC 96 +#define SRST_A_VOP_IEP 97 +#define SRST_A_IEP 98 +#define SRST_H_IEP_NOC 99 +#define SRST_H_IEP 100 +#define SRST_A_RGA_NOC 102 +#define SRST_A_RGA 103 +#define SRST_H_RGA_NOC 104 +#define SRST_H_RGA 105 +#define SRST_RGA_CORE 106 +#define SRST_EMMC_NOC 108 +#define SRST_EMMC 109 +#define SRST_EMMC_GRF 110 + +/* cru_softrst_con7 */ +#define SRST_A_PERIHP_NOC 112 +#define SRST_P_PERIHP_GRF 113 +#define SRST_H_PERIHP_NOC 114 +#define SRST_USBHOST0 115 +#define SRST_HOSTC0_AUX 116 +#define SRST_HOST0_ARB 117 +#define SRST_USBHOST1 118 +#define SRST_HOSTC1_AUX 119 +#define SRST_HOST1_ARB 120 +#define SRST_SDIO0 121 +#define SRST_SDMMC 122 +#define SRST_HSIC 123 +#define SRST_HSIC_AUX 124 +#define SRST_AHB1TOM 125 +#define SRST_P_PERIHP_NOC 126 +#define SRST_HSICPHY 127 + +/* cru_softrst_con8 */ +#define SRST_A_PCIE 128 +#define SRST_P_PCIE 129 +#define SRST_PCIE_CORE 130 +#define SRST_PCIE_MGMT 131 +#define SRST_PCIE_MGMT_STICKY 132 +#define SRST_PCIE_PIPE 133 +#define SRST_PCIE_PM 134 +#define SRST_PCIEPHY 135 +#define SRST_A_GMAC_NOC 136 +#define SRST_A_GMAC 137 +#define SRST_P_GMAC_NOC 138 +#define SRST_P_GMAC_GRF 140 +#define SRST_HSICPHY_POR 142 +#define SRST_HSICPHY_UTMI 143 + +/* cru_softrst_con9 */ +#define SRST_USB2PHY0_POR 144 +#define SRST_USB2PHY0_UTMI_PORT0 145 +#define SRST_USB2PHY0_UTMI_PORT1 146 +#define SRST_USB2PHY0_EHCIPHY 147 +#define SRST_UPHY0_PIPE_L00 148 +#define SRST_UPHY0 149 +#define SRST_UPHY0_TCPDPWRUP 150 +#define SRST_USB2PHY1_POR 152 +#define SRST_USB2PHY1_UTMI_PORT0 153 +#define SRST_USB2PHY1_UTMI_PORT1 154 +#define SRST_USB2PHY1_EHCIPHY 155 +#define SRST_UPHY1_PIPE_L00 156 +#define SRST_UPHY1 157 +#define SRST_UPHY1_TCPDPWRUP 158 + +/* cru_softrst_con10 */ +#define SRST_A_PERILP0_NOC 160 +#define SRST_A_DCF 161 +#define SRST_GIC500 162 +#define SRST_DMAC0_PERILP0 163 +#define SRST_DMAC1_PERILP0 164 +#define SRST_TZMA 165 +#define SRST_INTMEM 166 +#define SRST_ADB400_MST0 167 +#define SRST_ADB400_MST1 168 +#define SRST_ADB400_SLV0 169 +#define SRST_ADB400_SLV1 170 +#define SRST_H_PERILP0 171 +#define SRST_H_PERILP0_NOC 172 +#define SRST_ROM 173 +#define SRST_CRYPTO_S 174 +#define SRST_CRYPTO_M 175 + +/* cru_softrst_con11 */ +#define SRST_P_DCF 176 +#define SRST_CM0S_NOC 177 +#define SRST_CM0S 178 +#define SRST_CM0S_DBG 179 +#define SRST_CM0S_PO 180 +#define SRST_CRYPTO 181 +#define SRST_P_PERILP1_SGRF 182 +#define SRST_P_PERILP1_GRF 183 +#define SRST_CRYPTO1_S 184 +#define SRST_CRYPTO1_M 185 +#define SRST_CRYPTO1 186 +#define SRST_GIC_NOC 188 +#define SRST_SD_NOC 189 +#define SRST_SDIOAUDIO_BRG 190 + +/* cru_softrst_con12 */ +#define SRST_H_PERILP1 192 +#define SRST_H_PERILP1_NOC 193 +#define SRST_H_I2S0_8CH 194 +#define SRST_H_I2S1_8CH 195 +#define SRST_H_I2S2_8CH 196 +#define SRST_H_SPDIF_8CH 197 +#define SRST_P_PERILP1_NOC 198 +#define SRST_P_EFUSE_1024 199 +#define SRST_P_EFUSE_1024S 200 +#define SRST_P_I2C0 201 +#define SRST_P_I2C1 202 +#define SRST_P_I2C2 203 +#define SRST_P_I2C3 204 +#define SRST_P_I2C4 205 +#define SRST_P_I2C5 206 +#define SRST_P_MAILBOX0 207 + +/* cru_softrst_con13 */ +#define SRST_P_UART0 208 +#define SRST_P_UART1 209 +#define SRST_P_UART2 210 +#define SRST_P_UART3 211 +#define SRST_P_SARADC 212 +#define SRST_P_TSADC 213 +#define SRST_P_SPI0 214 +#define SRST_P_SPI1 215 +#define SRST_P_SPI2 216 +#define SRST_P_SPI3 217 +#define SRST_P_SPI4 218 +#define SRST_SPI0 219 +#define SRST_SPI1 220 +#define SRST_SPI2 221 +#define SRST_SPI3 222 +#define SRST_SPI4 223 + +/* cru_softrst_con14 */ +#define SRST_I2S0_8CH 224 +#define SRST_I2S1_8CH 225 +#define SRST_I2S2_8CH 226 +#define SRST_SPDIF_8CH 227 +#define SRST_UART0 228 +#define SRST_UART1 229 +#define SRST_UART2 230 +#define SRST_UART3 231 +#define SRST_TSADC 232 +#define SRST_I2C0 233 +#define SRST_I2C1 234 +#define SRST_I2C2 235 +#define SRST_I2C3 236 +#define SRST_I2C4 237 +#define SRST_I2C5 238 +#define SRST_SDIOAUDIO_NOC 239 + +/* cru_softrst_con15 */ +#define SRST_A_VIO_NOC 240 +#define SRST_A_HDCP_NOC 241 +#define SRST_A_HDCP 242 +#define SRST_H_HDCP_NOC 243 +#define SRST_H_HDCP 244 +#define SRST_P_HDCP_NOC 245 +#define SRST_P_HDCP 246 +#define SRST_P_HDMI_CTRL 247 +#define SRST_P_DP_CTRL 248 +#define SRST_S_DP_CTRL 249 +#define SRST_C_DP_CTRL 250 +#define SRST_P_MIPI_DSI0 251 +#define SRST_P_MIPI_DSI1 252 +#define SRST_DP_CORE 253 +#define SRST_DP_I2S 254 + +/* cru_softrst_con16 */ +#define SRST_GASKET 256 +#define SRST_VIO_GRF 258 +#define SRST_DPTX_SPDIF_REC 259 +#define SRST_HDMI_CTRL 260 +#define SRST_HDCP_CTRL 261 +#define SRST_A_ISP0_NOC 262 +#define SRST_A_ISP1_NOC 263 +#define SRST_H_ISP0_NOC 266 +#define SRST_H_ISP1_NOC 267 +#define SRST_H_ISP0 268 +#define SRST_H_ISP1 269 +#define SRST_ISP0 270 +#define SRST_ISP1 271 + +/* cru_softrst_con17 */ +#define SRST_A_VOP0_NOC 272 +#define SRST_A_VOP1_NOC 273 +#define SRST_A_VOP0 274 +#define SRST_A_VOP1 275 +#define SRST_H_VOP0_NOC 276 +#define SRST_H_VOP1_NOC 277 +#define SRST_H_VOP0 278 +#define SRST_H_VOP1 279 +#define SRST_D_VOP0 280 +#define SRST_D_VOP1 281 +#define SRST_VOP0_PWM 282 +#define SRST_VOP1_PWM 283 +#define SRST_P_EDP_NOC 284 +#define SRST_P_EDP_CTRL 285 + +/* cru_softrst_con18 */ +#define SRST_A_GPU 288 +#define SRST_A_GPU_NOC 289 +#define SRST_A_GPU_GRF 290 +#define SRST_PVTM_GPU 291 +#define SRST_A_USB3_NOC 292 +#define SRST_A_USB3_OTG0 293 +#define SRST_A_USB3_OTG1 294 +#define SRST_A_USB3_GRF 295 +#define SRST_PMU 296 + +/* cru_softrst_con19 */ +#define SRST_P_TIMER0_5 304 +#define SRST_TIMER0 305 +#define SRST_TIMER1 306 +#define SRST_TIMER2 307 +#define SRST_TIMER3 308 +#define SRST_TIMER4 309 +#define SRST_TIMER5 310 +#define SRST_P_TIMER6_11 311 +#define SRST_TIMER6 312 +#define SRST_TIMER7 313 +#define SRST_TIMER8 314 +#define SRST_TIMER9 315 +#define SRST_TIMER10 316 +#define SRST_TIMER11 317 +#define SRST_P_INTR_ARB_PMU 318 +#define SRST_P_ALIVE_SGRF 319 + +/* cru_softrst_con20 */ +#define SRST_P_GPIO2 320 +#define SRST_P_GPIO3 321 +#define SRST_P_GPIO4 322 +#define SRST_P_GRF 323 +#define SRST_P_ALIVE_NOC 324 +#define SRST_P_WDT0 325 +#define SRST_P_WDT1 326 +#define SRST_P_INTR_ARB 327 +#define SRST_P_UPHY0_DPTX 328 +#define SRST_P_UPHY0_APB 330 +#define SRST_P_UPHY0_TCPHY 332 +#define SRST_P_UPHY1_TCPHY 333 +#define SRST_P_UPHY0_TCPDCTRL 334 +#define SRST_P_UPHY1_TCPDCTRL 335 + +/* pmu soft-reset indices */ + +/* pmu_cru_softrst_con0 */ +#define SRST_P_NOC 0 +#define SRST_P_INTMEM 1 +#define SRST_H_CM0S 2 +#define SRST_H_CM0S_NOC 3 +#define SRST_DBG_CM0S 4 +#define SRST_PO_CM0S 5 +#define SRST_P_SPI6 6 +#define SRST_SPI6 7 +#define SRST_P_TIMER_0_1 8 +#define SRST_P_TIMER_0 9 +#define SRST_P_TIMER_1 10 +#define SRST_P_UART4 11 +#define SRST_UART4 12 +#define SRST_P_WDT 13 + +/* pmu_cru_softrst_con1 */ +#define SRST_P_I2C6 16 +#define SRST_P_I2C7 17 +#define SRST_P_I2C8 18 +#define SRST_P_MAILBOX 19 +#define SRST_P_RKPWM 20 +#define SRST_P_PMUGRF 21 +#define SRST_P_SGRF 22 +#define SRST_P_GPIO0 23 +#define SRST_P_GPIO1 24 +#define SRST_P_CRU 25 +#define SRST_P_INTR 26 +#define SRST_PVTM 27 +#define SRST_I2C6 28 +#define SRST_I2C7 29 +#define SRST_I2C8 30 + +#endif diff --git a/include/dt-structs.h b/include/dt-structs.h new file mode 100644 index 0000000..e13afa6 --- /dev/null +++ b/include/dt-structs.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2016 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_STTUCTS +#define __DT_STTUCTS + +/* These structures may only be used in SPL */ +#if CONFIG_IS_ENABLED(OF_PLATDATA) +struct phandle_2_cell { + const void *node; + int id; +}; +#include <generated/dt-structs.h> +#endif + +#endif diff --git a/include/dwmmc.h b/include/dwmmc.h index 335af51..6aebe96 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -224,9 +224,82 @@ static inline u8 dwmci_readb(struct dwmci_host *host, int reg) return readb(host->ioaddr + reg); } +#ifdef CONFIG_BLK +/** + * dwmci_setup_cfg() - Set up the configuration for DWMMC + * + * This is used to set up a DWMMC device when you are using CONFIG_BLK. + * + * This should be called from your MMC driver's probe() method once you have + * the information required. + * + * Generally your driver will have a platform data structure which holds both + * the configuration (struct mmc_config) and the MMC device info (struct mmc). + * For example: + * + * struct rockchip_mmc_plat { + * struct mmc_config cfg; + * struct mmc mmc; + * }; + * + * ... + * + * Inside U_BOOT_DRIVER(): + * .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat), + * + * To access platform data: + * struct rockchip_mmc_plat *plat = dev_get_platdata(dev); + * + * See rockchip_dw_mmc.c for an example. + * + * @cfg: Configuration structure to fill in (generally &plat->mmc) + * @name: Device name (normally dev->name) + * @buswidth: Bus width (in bits, such as 4 or 8) + * @caps: Host capabilities (MMC_MODE_...) + * @max_clk: Maximum supported clock speed in HZ (e.g. 400000) + * @min_clk: Minimum supported clock speed in HZ (e.g. 150000000) + */ void dwmci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth, uint caps, u32 max_clk, u32 min_clk); + +/** + * dwmci_bind() - Set up a new MMC block device + * + * This is used to set up a DWMMC block device when you are using CONFIG_BLK. + * It should be called from your driver's bind() method. + * + * See rockchip_dw_mmc.c for an example. + * + * @dev: Device to set up + * @mmc: Pointer to mmc structure (normally &plat->mmc) + * @cfg: Empty configuration structure (generally &plat->cfg). This is + * normally all zeroes at this point. The only purpose of passing + * this in is to set mmc->cfg to it. + * @return 0 if OK, -ve if the block device could not be created + */ int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg); +#else +/** + * add_dwmci() - Add a new DWMMC interface + * + * This is used when you are not using CONFIG_BLK. Convert your driver over! + * + * @host: DWMMC host structure + * @max_clk: Maximum supported clock speed in HZ (e.g. 400000) + * @min_clk: Minimum supported clock speed in HZ (e.g. 150000000) + * @return 0 if OK, -ve on error + */ int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk); +#endif /* !CONFIG_BLK */ + +#ifdef CONFIG_DM_MMC_OPS +/* Export the operations to drivers */ +int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data); +int dwmci_set_ios(struct udevice *dev); +int dwmci_probe(struct udevice *dev); +extern const struct dm_mmc_ops dm_dwmci_ops; +#endif + #endif /* __DWMMC_HW_H */ diff --git a/include/fdtdec.h b/include/fdtdec.h index 05d70c4..70ea0bf 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -134,13 +134,10 @@ enum fdt_compat_id { COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */ COMPAT_SAMSUNG_EXYNOS5_SOUND, /* Exynos Sound */ COMPAT_WOLFSON_WM8994_CODEC, /* Wolfson WM8994 Sound Codec */ - COMPAT_GOOGLE_CROS_EC_KEYB, /* Google CROS_EC Keyboard */ COMPAT_SAMSUNG_EXYNOS_USB_PHY, /* Exynos phy controller for usb2.0 */ COMPAT_SAMSUNG_EXYNOS5_USB3_PHY,/* Exynos phy controller for usb3.0 */ COMPAT_SAMSUNG_EXYNOS_TMU, /* Exynos TMU */ - COMPAT_SAMSUNG_EXYNOS_FIMD, /* Exynos Display controller */ COMPAT_SAMSUNG_EXYNOS_MIPI_DSI, /* Exynos mipi dsi */ - COMPAT_SAMSUNG_EXYNOS5_DP, /* Exynos Display port controller */ COMPAT_SAMSUNG_EXYNOS_DWMMC, /* Exynos DWMMC controller */ COMPAT_SAMSUNG_EXYNOS_MMC, /* Exynos MMC controller */ COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */ @@ -149,20 +146,16 @@ enum fdt_compat_id { COMPAT_SAMSUNG_EXYNOS5_I2C, /* Exynos5 High Speed I2C Controller */ COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */ COMPAT_INTEL_MICROCODE, /* Intel microcode update */ - COMPAT_INTEL_PANTHERPOINT_AHCI, /* Intel Pantherpoint AHCI */ - COMPAT_INTEL_MODEL_206AX, /* Intel Model 206AX CPU */ - COMPAT_INTEL_GMA, /* Intel Graphics Media Accelerator */ COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */ - COMPAT_INTEL_ICH_SPI, /* Intel ICH7/9 SPI controller */ COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */ COMPAT_SOCIONEXT_XHCI, /* Socionext UniPhier xHCI */ - COMPAT_INTEL_PCH, /* Intel PCH */ COMPAT_ALTERA_SOCFPGA_DWMAC, /* SoCFPGA Ethernet controller */ COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */ COMPAT_ALTERA_SOCFPGA_DWC2USB, /* SoCFPGA DWC2 USB controller */ COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */ COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */ COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */ + COMPAT_SUNXI_NAND, /* SUNXI NAND controller */ COMPAT_COUNT, }; diff --git a/include/fsl_validate.h b/include/fsl_validate.h index a71e1ce..c350938 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -254,4 +254,11 @@ int fsl_secboot_blob_decap(cmd_tbl_t *cmdtp, int flag, int argc, int fsl_check_boot_mode_secure(void); int fsl_setenv_chain_of_trust(void); + +/* + * This function is used to validate the main U-boot binary from + * SPL just before passing control to it using QorIQ Trust + * Architecture header (appended to U-boot image). + */ +void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr); #endif diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index e1b9c64..bb8e144 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -17,7 +17,6 @@ enum { }; int get_fpga_state(unsigned dev); -void print_fpga_state(unsigned dev); int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data); int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data); diff --git a/include/i2c_eeprom.h b/include/i2c_eeprom.h index ea6c962..0452892 100644 --- a/include/i2c_eeprom.h +++ b/include/i2c_eeprom.h @@ -14,6 +14,10 @@ struct i2c_eeprom_ops { }; struct i2c_eeprom { + /* The EEPROM's page size in byte */ + unsigned long pagesize; + /* The EEPROM's page width in bits (pagesize = 2^pagewidth) */ + unsigned pagewidth; }; #endif diff --git a/include/image.h b/include/image.h index d788c26..734def3 100644 --- a/include/image.h +++ b/include/image.h @@ -123,62 +123,86 @@ struct lmb; # define IMAGE_OF_SYSTEM_SETUP 0 #endif +enum ih_category { + IH_ARCH, + IH_COMP, + IH_OS, + IH_TYPE, + + IH_COUNT, +}; + /* * Operating System Codes + * + * The following are exposed to uImage header. + * Do not change values for backward compatibility. */ -#define IH_OS_INVALID 0 /* Invalid OS */ -#define IH_OS_OPENBSD 1 /* OpenBSD */ -#define IH_OS_NETBSD 2 /* NetBSD */ -#define IH_OS_FREEBSD 3 /* FreeBSD */ -#define IH_OS_4_4BSD 4 /* 4.4BSD */ -#define IH_OS_LINUX 5 /* Linux */ -#define IH_OS_SVR4 6 /* SVR4 */ -#define IH_OS_ESIX 7 /* Esix */ -#define IH_OS_SOLARIS 8 /* Solaris */ -#define IH_OS_IRIX 9 /* Irix */ -#define IH_OS_SCO 10 /* SCO */ -#define IH_OS_DELL 11 /* Dell */ -#define IH_OS_NCR 12 /* NCR */ -#define IH_OS_LYNXOS 13 /* LynxOS */ -#define IH_OS_VXWORKS 14 /* VxWorks */ -#define IH_OS_PSOS 15 /* pSOS */ -#define IH_OS_QNX 16 /* QNX */ -#define IH_OS_U_BOOT 17 /* Firmware */ -#define IH_OS_RTEMS 18 /* RTEMS */ -#define IH_OS_ARTOS 19 /* ARTOS */ -#define IH_OS_UNITY 20 /* Unity OS */ -#define IH_OS_INTEGRITY 21 /* INTEGRITY */ -#define IH_OS_OSE 22 /* OSE */ -#define IH_OS_PLAN9 23 /* Plan 9 */ -#define IH_OS_OPENRTOS 24 /* OpenRTOS */ +enum { + IH_OS_INVALID = 0, /* Invalid OS */ + IH_OS_OPENBSD, /* OpenBSD */ + IH_OS_NETBSD, /* NetBSD */ + IH_OS_FREEBSD, /* FreeBSD */ + IH_OS_4_4BSD, /* 4.4BSD */ + IH_OS_LINUX, /* Linux */ + IH_OS_SVR4, /* SVR4 */ + IH_OS_ESIX, /* Esix */ + IH_OS_SOLARIS, /* Solaris */ + IH_OS_IRIX, /* Irix */ + IH_OS_SCO, /* SCO */ + IH_OS_DELL, /* Dell */ + IH_OS_NCR, /* NCR */ + IH_OS_LYNXOS, /* LynxOS */ + IH_OS_VXWORKS, /* VxWorks */ + IH_OS_PSOS, /* pSOS */ + IH_OS_QNX, /* QNX */ + IH_OS_U_BOOT, /* Firmware */ + IH_OS_RTEMS, /* RTEMS */ + IH_OS_ARTOS, /* ARTOS */ + IH_OS_UNITY, /* Unity OS */ + IH_OS_INTEGRITY, /* INTEGRITY */ + IH_OS_OSE, /* OSE */ + IH_OS_PLAN9, /* Plan 9 */ + IH_OS_OPENRTOS, /* OpenRTOS */ + + IH_OS_COUNT, +}; /* * CPU Architecture Codes (supported by Linux) + * + * The following are exposed to uImage header. + * Do not change values for backward compatibility. */ -#define IH_ARCH_INVALID 0 /* Invalid CPU */ -#define IH_ARCH_ALPHA 1 /* Alpha */ -#define IH_ARCH_ARM 2 /* ARM */ -#define IH_ARCH_I386 3 /* Intel x86 */ -#define IH_ARCH_IA64 4 /* IA64 */ -#define IH_ARCH_MIPS 5 /* MIPS */ -#define IH_ARCH_MIPS64 6 /* MIPS 64 Bit */ -#define IH_ARCH_PPC 7 /* PowerPC */ -#define IH_ARCH_S390 8 /* IBM S390 */ -#define IH_ARCH_SH 9 /* SuperH */ -#define IH_ARCH_SPARC 10 /* Sparc */ -#define IH_ARCH_SPARC64 11 /* Sparc 64 Bit */ -#define IH_ARCH_M68K 12 /* M68K */ -#define IH_ARCH_MICROBLAZE 14 /* MicroBlaze */ -#define IH_ARCH_NIOS2 15 /* Nios-II */ -#define IH_ARCH_BLACKFIN 16 /* Blackfin */ -#define IH_ARCH_AVR32 17 /* AVR32 */ -#define IH_ARCH_ST200 18 /* STMicroelectronics ST200 */ -#define IH_ARCH_SANDBOX 19 /* Sandbox architecture (test only) */ -#define IH_ARCH_NDS32 20 /* ANDES Technology - NDS32 */ -#define IH_ARCH_OPENRISC 21 /* OpenRISC 1000 */ -#define IH_ARCH_ARM64 22 /* ARM64 */ -#define IH_ARCH_ARC 23 /* Synopsys DesignWare ARC */ -#define IH_ARCH_X86_64 24 /* AMD x86_64, Intel and Via */ +enum { + IH_ARCH_INVALID = 0, /* Invalid CPU */ + IH_ARCH_ALPHA, /* Alpha */ + IH_ARCH_ARM, /* ARM */ + IH_ARCH_I386, /* Intel x86 */ + IH_ARCH_IA64, /* IA64 */ + IH_ARCH_MIPS, /* MIPS */ + IH_ARCH_MIPS64, /* MIPS 64 Bit */ + IH_ARCH_PPC, /* PowerPC */ + IH_ARCH_S390, /* IBM S390 */ + IH_ARCH_SH, /* SuperH */ + IH_ARCH_SPARC, /* Sparc */ + IH_ARCH_SPARC64, /* Sparc 64 Bit */ + IH_ARCH_M68K, /* M68K */ + IH_ARCH_NIOS, /* Nios-32 */ + IH_ARCH_MICROBLAZE, /* MicroBlaze */ + IH_ARCH_NIOS2, /* Nios-II */ + IH_ARCH_BLACKFIN, /* Blackfin */ + IH_ARCH_AVR32, /* AVR32 */ + IH_ARCH_ST200, /* STMicroelectronics ST200 */ + IH_ARCH_SANDBOX, /* Sandbox architecture (test only) */ + IH_ARCH_NDS32, /* ANDES Technology - NDS32 */ + IH_ARCH_OPENRISC, /* OpenRISC 1000 */ + IH_ARCH_ARM64, /* ARM64 */ + IH_ARCH_ARC, /* Synopsys DesignWare ARC */ + IH_ARCH_X86_64, /* AMD x86_64, Intel and Via */ + + IH_ARCH_COUNT, +}; /* * Image Types @@ -217,49 +241,62 @@ struct lmb; * U-Boot's command interpreter; this feature is especially * useful when you configure U-Boot to use a real shell (hush) * as command interpreter (=> Shell Scripts). + * + * The following are exposed to uImage header. + * Do not change values for backward compatibility. */ -#define IH_TYPE_INVALID 0 /* Invalid Image */ -#define IH_TYPE_STANDALONE 1 /* Standalone Program */ -#define IH_TYPE_KERNEL 2 /* OS Kernel Image */ -#define IH_TYPE_RAMDISK 3 /* RAMDisk Image */ -#define IH_TYPE_MULTI 4 /* Multi-File Image */ -#define IH_TYPE_FIRMWARE 5 /* Firmware Image */ -#define IH_TYPE_SCRIPT 6 /* Script file */ -#define IH_TYPE_FILESYSTEM 7 /* Filesystem Image (any type) */ -#define IH_TYPE_FLATDT 8 /* Binary Flat Device Tree Blob */ -#define IH_TYPE_KWBIMAGE 9 /* Kirkwood Boot Image */ -#define IH_TYPE_IMXIMAGE 10 /* Freescale IMXBoot Image */ -#define IH_TYPE_UBLIMAGE 11 /* Davinci UBL Image */ -#define IH_TYPE_OMAPIMAGE 12 /* TI OMAP Config Header Image */ -#define IH_TYPE_AISIMAGE 13 /* TI Davinci AIS Image */ -#define IH_TYPE_KERNEL_NOLOAD 14 /* OS Kernel Image, can run from any load address */ -#define IH_TYPE_PBLIMAGE 15 /* Freescale PBL Boot Image */ -#define IH_TYPE_MXSIMAGE 16 /* Freescale MXSBoot Image */ -#define IH_TYPE_GPIMAGE 17 /* TI Keystone GPHeader Image */ -#define IH_TYPE_ATMELIMAGE 18 /* ATMEL ROM bootable Image */ -#define IH_TYPE_SOCFPGAIMAGE 19 /* Altera SOCFPGA Preloader */ -#define IH_TYPE_X86_SETUP 20 /* x86 setup.bin Image */ -#define IH_TYPE_LPC32XXIMAGE 21 /* x86 setup.bin Image */ -#define IH_TYPE_LOADABLE 22 /* A list of typeless images */ -#define IH_TYPE_RKIMAGE 23 /* Rockchip Boot Image */ -#define IH_TYPE_RKSD 24 /* Rockchip SD card */ -#define IH_TYPE_RKSPI 25 /* Rockchip SPI image */ -#define IH_TYPE_ZYNQIMAGE 26 /* Xilinx Zynq Boot Image */ -#define IH_TYPE_ZYNQMPIMAGE 27 /* Xilinx ZynqMP Boot Image */ -#define IH_TYPE_FPGA 28 /* FPGA Image */ - -#define IH_TYPE_COUNT 29 /* Number of image types */ +enum { + IH_TYPE_INVALID = 0, /* Invalid Image */ + IH_TYPE_STANDALONE, /* Standalone Program */ + IH_TYPE_KERNEL, /* OS Kernel Image */ + IH_TYPE_RAMDISK, /* RAMDisk Image */ + IH_TYPE_MULTI, /* Multi-File Image */ + IH_TYPE_FIRMWARE, /* Firmware Image */ + IH_TYPE_SCRIPT, /* Script file */ + IH_TYPE_FILESYSTEM, /* Filesystem Image (any type) */ + IH_TYPE_FLATDT, /* Binary Flat Device Tree Blob */ + IH_TYPE_KWBIMAGE, /* Kirkwood Boot Image */ + IH_TYPE_IMXIMAGE, /* Freescale IMXBoot Image */ + IH_TYPE_UBLIMAGE, /* Davinci UBL Image */ + IH_TYPE_OMAPIMAGE, /* TI OMAP Config Header Image */ + IH_TYPE_AISIMAGE, /* TI Davinci AIS Image */ + /* OS Kernel Image, can run from any load address */ + IH_TYPE_KERNEL_NOLOAD, + IH_TYPE_PBLIMAGE, /* Freescale PBL Boot Image */ + IH_TYPE_MXSIMAGE, /* Freescale MXSBoot Image */ + IH_TYPE_GPIMAGE, /* TI Keystone GPHeader Image */ + IH_TYPE_ATMELIMAGE, /* ATMEL ROM bootable Image */ + IH_TYPE_SOCFPGAIMAGE, /* Altera SOCFPGA Preloader */ + IH_TYPE_X86_SETUP, /* x86 setup.bin Image */ + IH_TYPE_LPC32XXIMAGE, /* x86 setup.bin Image */ + IH_TYPE_LOADABLE, /* A list of typeless images */ + IH_TYPE_RKIMAGE, /* Rockchip Boot Image */ + IH_TYPE_RKSD, /* Rockchip SD card */ + IH_TYPE_RKSPI, /* Rockchip SPI image */ + IH_TYPE_ZYNQIMAGE, /* Xilinx Zynq Boot Image */ + IH_TYPE_ZYNQMPIMAGE, /* Xilinx ZynqMP Boot Image */ + IH_TYPE_FPGA, /* FPGA Image */ + + IH_TYPE_COUNT, /* Number of image types */ +}; /* * Compression Types + * + * The following are exposed to uImage header. + * Do not change values for backward compatibility. */ -#define IH_COMP_NONE 0 /* No Compression Used */ -#define IH_COMP_GZIP 1 /* gzip Compression Used */ -#define IH_COMP_BZIP2 2 /* bzip2 Compression Used */ -#define IH_COMP_LZMA 3 /* lzma Compression Used */ -#define IH_COMP_LZO 4 /* lzo Compression Used */ -#define IH_COMP_LZ4 5 /* lz4 Compression Used */ +enum { + IH_COMP_NONE = 0, /* No Compression Used */ + IH_COMP_GZIP, /* gzip Compression Used */ + IH_COMP_BZIP2, /* bzip2 Compression Used */ + IH_COMP_LZMA, /* lzma Compression Used */ + IH_COMP_LZO, /* lzo Compression Used */ + IH_COMP_LZ4, /* lz4 Compression Used */ + + IH_COMP_COUNT, +}; #define IH_MAGIC 0x27051956 /* Image Magic Number */ #define IH_NMLEN 32 /* Image Name Length */ @@ -454,6 +491,40 @@ const char *genimg_get_comp_name(uint8_t comp); */ const char *genimg_get_comp_short_name(uint8_t comp); +/** + * genimg_get_cat_name() - Get the name of an item in a category + * + * @category: Category of item + * @id: Item ID + * @return name of item, or "Unknown ..." if unknown + */ +const char *genimg_get_cat_name(enum ih_category category, uint id); + +/** + * genimg_get_cat_short_name() - Get the short name of an item in a category + * + * @category: Category of item + * @id: Item ID + * @return short name of item, or "Unknown ..." if unknown + */ +const char *genimg_get_cat_short_name(enum ih_category category, uint id); + +/** + * genimg_get_cat_count() - Get the number of items in a category + * + * @category: Category to check + * @return the number of items in the category (IH_xxx_COUNT) + */ +int genimg_get_cat_count(enum ih_category category); + +/** + * genimg_get_cat_desc() - Get the description of a category + * + * @return the description of a category, e.g. "architecture". This + * effectively converts the enum to a string. + */ +const char *genimg_get_cat_desc(enum ih_category category); + int genimg_get_os_id(const char *name); int genimg_get_arch_id(const char *name); int genimg_get_type_id(const char *name); @@ -1173,4 +1244,21 @@ void android_print_contents(const struct andr_img_hdr *hdr); */ int board_fit_config_name_match(const char *name); +#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS +/** + * board_fit_image_post_process() - Do any post-process on FIT binary data + * + * This is used to do any sort of image manipulation, verification, decryption + * etc. in a platform or board specific way. Obviously, anything done here would + * need to be comprehended in how the images were prepared before being injected + * into the FIT creation (i.e. the binary blobs would have been pre-processed + * before being added to the FIT image). + * + * @image: pointer to the image start pointer + * @size: pointer to the image size + * @return no return value (failure should be handled internally) + */ +void board_fit_image_post_process(void **p_image, size_t *p_size); +#endif /* CONFIG_SPL_FIT_IMAGE_POST_PROCESS */ + #endif /* __IMAGE_H__ */ diff --git a/include/linux/io.h b/include/linux/io.h index 1b36a22..a104b7e 100644 --- a/include/linux/io.h +++ b/include/linux/io.h @@ -5,6 +5,22 @@ #ifndef _LINUX_IO_H #define _LINUX_IO_H +#include <linux/compiler.h> +#include <linux/types.h> #include <asm/io.h> +#ifndef CONFIG_HAVE_ARCH_IOREMAP +static inline void __iomem *ioremap(resource_size_t offset, + resource_size_t size) +{ + return (void __iomem *)(unsigned long)offset; +} + +static inline void iounmap(void __iomem *addr) +{ +} + +#define devm_ioremap(dev, offset, size) ioremap(offset, size) +#endif + #endif /* _LINUX_IO_H */ diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index cf20674..779eea0 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -500,5 +500,10 @@ int mtd_arg_off(const char *arg, int *idx, loff_t *off, loff_t *size, int mtd_arg_off_size(int argc, char *const argv[], int *idx, loff_t *off, loff_t *size, loff_t *maxsize, int devtype, uint64_t chipsize); + +/* drivers/mtd/mtdcore.c */ +void mtd_get_len_incl_bad(struct mtd_info *mtd, uint64_t offset, + const uint64_t length, uint64_t *len_incl_bad, + int *truncated); #endif #endif /* __MTD_MTD_H__ */ diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index b5a02c3..87d72db 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -48,7 +48,7 @@ extern void nand_wait_ready(struct mtd_info *mtd); * is supported now. If you add a chip with bigger oobsize/page * adjust this accordingly. */ -#define NAND_MAX_OOBSIZE 1216 +#define NAND_MAX_OOBSIZE 1664 #define NAND_MAX_PAGESIZE 16384 /* @@ -590,6 +590,7 @@ struct nand_buffers { * flash device * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the * flash device. + * @flash_node: [BOARDSPECIFIC] device node describing this instance * @read_byte: [REPLACEABLE] read one byte from the chip * @read_word: [REPLACEABLE] read one word from the chip * @write_byte: [REPLACEABLE] write a single byte to the chip on the @@ -689,6 +690,8 @@ struct nand_chip { void __iomem *IO_ADDR_R; void __iomem *IO_ADDR_W; + int flash_node; + uint8_t (*read_byte)(struct mtd_info *mtd); u16 (*read_word)(struct mtd_info *mtd); void (*write_byte)(struct mtd_info *mtd, uint8_t byte); diff --git a/include/linux/mtd/omap_gpmc.h b/include/linux/mtd/omap_gpmc.h index 3a75674..be3ce9d 100644 --- a/include/linux/mtd/omap_gpmc.h +++ b/include/linux/mtd/omap_gpmc.h @@ -92,6 +92,7 @@ struct gpmc { }; /* Used for board specific gpmc initialization */ -extern struct gpmc *gpmc_cfg; +extern const struct gpmc *gpmc_cfg; +extern char gpmc_cs0_flash; #endif /* __ASM_OMAP_GPMC_H */ diff --git a/include/linux/types.h b/include/linux/types.h index 6f75be4..416fa66 100644 --- a/include/linux/types.h +++ b/include/linux/types.h @@ -124,6 +124,10 @@ typedef __UINT64_TYPE__ u_int64_t; typedef __INT64_TYPE__ int64_t; #endif +#ifdef __KERNEL__ +typedef phys_addr_t resource_size_t; +#endif + /* * Below are truly Linux-specific types that should never collide with * any application/library that wants linux/types.h. diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h index 253eddf..199f366 100644 --- a/include/linux/usb/xhci-fsl.h +++ b/include/linux/usb/xhci-fsl.h @@ -51,22 +51,18 @@ struct fsl_xhci { struct dwc3 *dwc3_reg; }; -#if defined(CONFIG_LS102XA) -#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR +#if defined(CONFIG_LS102XA) || defined(CONFIG_LS1012A) +#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 #elif defined(CONFIG_LS2080A) -#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR -#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR -#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 -#elif defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A) -#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR -#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR -#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR -#elif defined(CONFIG_LS1012A) -#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR -#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0 +#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR +#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 +#elif defined(CONFIG_LS1043A) +#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR +#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR +#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_XHCI_USB3_ADDR #endif #define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \ diff --git a/include/mmc.h b/include/mmc.h index f383925..8f309f1 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -323,6 +323,58 @@ struct mmc_data { /* forward decl. */ struct mmc; +#ifdef CONFIG_DM_MMC_OPS +struct dm_mmc_ops { + /** + * send_cmd() - Send a command to the MMC device + * + * @dev: Device to receive the command + * @cmd: Command to send + * @data: Additional data to send/receive + * @return 0 if OK, -ve on error + */ + int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data); + + /** + * set_ios() - Set the I/O speed/width for an MMC device + * + * @dev: Device to update + * @return 0 if OK, -ve on error + */ + int (*set_ios)(struct udevice *dev); + + /** + * get_cd() - See whether a card is present + * + * @dev: Device to check + * @return 0 if not present, 1 if present, -ve on error + */ + int (*get_cd)(struct udevice *dev); + + /** + * get_wp() - See whether a card has write-protect enabled + * + * @dev: Device to check + * @return 0 if write-enabled, 1 if write-protected, -ve on error + */ + int (*get_wp)(struct udevice *dev); +}; + +#define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops) + +int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data); +int dm_mmc_set_ios(struct udevice *dev); +int dm_mmc_get_cd(struct udevice *dev); +int dm_mmc_get_wp(struct udevice *dev); + +/* Transition functions for compatibility */ +int mmc_set_ios(struct mmc *mmc); +int mmc_getcd(struct mmc *mmc); +int mmc_getwp(struct mmc *mmc); + +#else struct mmc_ops { int (*send_cmd)(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data); @@ -331,10 +383,13 @@ struct mmc_ops { int (*getcd)(struct mmc *mmc); int (*getwp)(struct mmc *mmc); }; +#endif struct mmc_config { const char *name; +#ifndef CONFIG_DM_MMC_OPS const struct mmc_ops *ops; +#endif uint host_caps; uint voltages; uint f_min; @@ -343,7 +398,12 @@ struct mmc_config { unsigned char part_type; }; -/* TODO struct mmc should be in mmc_private but it's hard to fix right now */ +/* + * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device + * with mmc_get_mmc_dev(). + * + * TODO struct mmc should be in mmc_private but it's hard to fix right now + */ struct mmc { #ifndef CONFIG_BLK struct list_head link; @@ -446,10 +506,14 @@ void print_mmc_devices(char separator); int get_mmc_num(void); int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf, enum mmc_hwpart_conf_mode mode); + +#ifndef CONFIG_DM_MMC_OPS int mmc_getcd(struct mmc *mmc); int board_mmc_getcd(struct mmc *mmc); int mmc_getwp(struct mmc *mmc); int board_mmc_getwp(struct mmc *mmc); +#endif + int mmc_set_dsr(struct mmc *mmc, u16 val); /* Function to change the size of boot partition and rpmb partitions */ int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, diff --git a/include/nand.h b/include/nand.h index a4f0f92..b6eb223 100644 --- a/include/nand.h +++ b/include/nand.h @@ -122,6 +122,7 @@ int nand_unlock(struct mtd_info *mtd, loff_t start, size_t length, int nand_get_lock_status(struct mtd_info *mtd, loff_t offset); int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst); +int nand_spl_read_block(int block, int offset, int len, void *dst); void nand_deselect(void); #ifdef CONFIG_SYS_NAND_SELECT_DEVICE @@ -141,3 +142,6 @@ __attribute__((noreturn)) void nand_boot(void); int get_nand_env_oob(struct mtd_info *mtd, unsigned long *result); #endif int spl_nand_erase_one(int block, int page); + +/* platform specific init functions */ +void sunxi_nand_init(void); diff --git a/include/net.h b/include/net.h index 5ee5929..06320c6 100644 --- a/include/net.h +++ b/include/net.h @@ -238,7 +238,7 @@ int eth_getenv_enetaddr(const char *name, uchar *enetaddr); int eth_setenv_enetaddr(const char *name, const uchar *enetaddr); /** - * eth_setenv_enetaddr_by_index() - set the MAC address envrionment variable + * eth_setenv_enetaddr_by_index() - set the MAC address environment variable * * This sets up an environment variable with the given MAC address (@enetaddr). * The environment variable to be set is defined by <@base_name><@index>addr. diff --git a/include/onenand_uboot.h b/include/onenand_uboot.h index fd01040..995f0aa 100644 --- a/include/onenand_uboot.h +++ b/include/onenand_uboot.h @@ -26,7 +26,7 @@ extern struct mtd_info onenand_mtd; extern struct onenand_chip onenand_chip; /* board */ -extern void onenand_board_init(struct mtd_info *); +extern int onenand_board_init(struct mtd_info *); /* Functions */ extern void onenand_init(void); @@ -49,6 +49,7 @@ extern int flexonenand_set_boundary(struct mtd_info *mtd, int die, int boundary, int lock); /* SPL */ +int onenand_spl_read_block(int block, int offset, int len, void *dst); void onenand_spl_load_image(uint32_t offs, uint32_t size, void *dst); #endif /* __UBOOT_ONENAND_H */ diff --git a/include/os.h b/include/os.h index 954a48c..1782e50 100644 --- a/include/os.h +++ b/include/os.h @@ -287,6 +287,31 @@ int os_read_ram_buf(const char *fname); int os_jump_to_image(const void *dest, int size); /** + * os_find_u_boot() - Determine the path to U-Boot proper + * + * This function is intended to be called from within sandbox SPL. It uses + * a few heuristics to find U-Boot proper. Normally it is either in the same + * directory, or the directory above (since u-boot-spl is normally in an + * spl/ subdirectory when built). + * + * @fname: Place to put full path to U-Boot + * @maxlen: Maximum size of @fname + * @return 0 if OK, -NOSPC if the filename is too large, -ENOENT if not found + */ +int os_find_u_boot(char *fname, int maxlen); + +/** + * os_spl_to_uboot() - Run U-Boot proper + * + * When called from SPL, this runs U-Boot proper. The filename is obtained by + * calling os_find_u_boot(). + * + * @fname: Full pathname to U-Boot executable + * @return 0 if OK, -ve on error + */ +int os_spl_to_uboot(const char *fname); + +/** * Read the current system time * * This reads the current Local Time and places it into the provided diff --git a/include/regmap.h b/include/regmap.h index eccf770..1eed94e 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -57,6 +57,22 @@ int regmap_read(struct regmap *map, uint offset, uint *valp); int regmap_init_mem(struct udevice *dev, struct regmap **mapp); /** + * regmap_init_mem_platdata() - Set up a new memory register map for of-platdata + * + * This creates a new regmap with a list of regions passed in, rather than + * using the device tree. It only supports 32-bit machines. + * + * Use regmap_uninit() to free it. + * + * @dev: Device that uses this map + * @reg: List of address, size pairs + * @count: Number of pairs (e.g. 1 if the regmap has a single entry) + * @mapp: Returns allocated map + */ +int regmap_init_mem_platdata(struct udevice *dev, u32 *reg, int count, + struct regmap **mapp); + +/** * regmap_get_range() - Obtain the base memory address of a regmap range * * @map: Regmap to query diff --git a/include/sdhci.h b/include/sdhci.h index e0f6667..c4d3b55 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -338,5 +338,85 @@ static inline u8 sdhci_readb(struct sdhci_host *host, int reg) } #endif +#ifdef CONFIG_BLK +/** + * sdhci_setup_cfg() - Set up the configuration for DWMMC + * + * This is used to set up an SDHCI device when you are using CONFIG_BLK. + * + * This should be called from your MMC driver's probe() method once you have + * the information required. + * + * Generally your driver will have a platform data structure which holds both + * the configuration (struct mmc_config) and the MMC device info (struct mmc). + * For example: + * + * struct msm_sdhc_plat { + * struct mmc_config cfg; + * struct mmc mmc; + * }; + * + * ... + * + * Inside U_BOOT_DRIVER(): + * .platdata_auto_alloc_size = sizeof(struct msm_sdhc_plat), + * + * To access platform data: + * struct msm_sdhc_plat *plat = dev_get_platdata(dev); + * + * See msm_sdhci.c for an example. + * + * @cfg: Configuration structure to fill in (generally &plat->mmc) + * @name: Device name (normally dev->name) + * @buswidth: Bus width (in bits, such as 4 or 8) + * @caps: Host capabilities (MMC_MODE_...) + * @max_clk: Maximum supported clock speed in HZ (0 for default) + * @min_clk: Minimum supported clock speed in HZ (0 for default) + * @version: Host controller version (generally read from the + * SDHCI_HOST_VERSION register) + * @quirks: Quick flags (SDHCI_QUIRK_...) + * @host_caps: Additional host capabilities (0 if none) + */ +int sdhci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth, + uint caps, u32 max_clk, u32 min_clk, uint version, + uint quirks, uint host_caps); + +/** + * sdhci_bind() - Set up a new MMC block device + * + * This is used to set up an SDHCI block device when you are using CONFIG_BLK. + * It should be called from your driver's bind() method. + * + * See msm_sdhci.c for an example. + * + * @dev: Device to set up + * @mmc: Pointer to mmc structure (normally &plat->mmc) + * @cfg: Empty configuration structure (generally &plat->cfg). This is + * normally all zeroes at this point. The only purpose of passing + * this in is to set mmc->cfg to it. + * @return 0 if OK, -ve if the block device could not be created + */ +int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg); +#else + +/** + * add_sdhci() - Add a new SDHCI interface + * + * This is used when you are not using CONFIG_BLK. Convert your driver over! + * + * @host: SDHCI host structure + * @max_clk: Maximum supported clock speed in HZ (0 for default) + * @min_clk: Minimum supported clock speed in HZ (0 for default) + * @return 0 if OK, -ve on error + */ int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk); +#endif /* !CONFIG_BLK */ + +#ifdef CONFIG_DM_MMC_OPS +/* Export the operations to drivers */ +int sdhci_probe(struct udevice *dev); +extern const struct dm_mmc_ops sdhci_ops; +#else +#endif + #endif /* __SDHCI_HW_H */ diff --git a/include/spl.h b/include/spl.h index 2360466..8afa085 100644 --- a/include/spl.h +++ b/include/spl.h @@ -71,6 +71,7 @@ void spl_set_header_raw_uboot(void); int spl_parse_image_header(const struct image_header *header); void spl_board_prepare_for_linux(void); void spl_board_prepare_for_boot(void); +int spl_board_ubi_load_image(u32 boot_device); void __noreturn jump_to_image_linux(void *arg); int spl_start_uboot(void); void spl_display_print(void); @@ -84,6 +85,9 @@ int spl_onenand_load_image(void); /* NOR SPL functions */ int spl_nor_load_image(void); +/* UBI SPL functions */ +int spl_ubi_load_image(u32 boot_device); + /* MMC SPL functions */ int spl_mmc_load_image(u32 boot_device); diff --git a/include/syscon.h b/include/syscon.h index 4593b6e..34842aa 100644 --- a/include/syscon.h +++ b/include/syscon.h @@ -23,6 +23,17 @@ struct syscon_ops { #define syscon_get_ops(dev) ((struct syscon_ops *)(dev)->driver->ops) +#if CONFIG_IS_ENABLED(OF_PLATDATA) +/* + * We don't support 64-bit machines. If they are so resource-contrained that + * they need to use OF_PLATDATA, something is horribly wrong with the + * education of our hardware engineers. + */ +struct syscon_base_platdata { + u32 reg[2]; +}; +#endif + /** * syscon_get_regmap() - Get access to a register map * diff --git a/include/ubispl.h b/include/ubispl.h new file mode 100644 index 0000000..944653e --- /dev/null +++ b/include/ubispl.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) Thomas Gleixner <tglx@linutronix.de> + * + * SPDX-License-Identifier: GPL 2.0+ BSD-3-Clause + */ +#ifndef __UBOOT_UBISPL_H +#define __UBOOT_UBISPL_H + +/* + * The following CONFIG options are relevant for UBISPL + * + * #define CONFIG_SPL_UBI_MAX_VOL_LEBS 256 + * + * Defines the maximum number of logical erase blocks per loadable + * (static) volume to size the ubispl internal arrays. + * + * #define CONFIG_SPL_UBI_MAX_PEB_SIZE (256*1024) + * + * Defines the maximum physical erase block size to size the fastmap + * buffer for ubispl. + * + * #define CONFIG_SPL_UBI_MAX_PEBS 4096 + * + * Define the maximum number of physical erase blocks to size the + * ubispl internal arrays. + * + * #define CONFIG_SPL_UBI_VOL_IDS 8 + * + * Defines the maximum number of volumes in which UBISPL is + * interested. Limits the amount of memory for the scan data and + * speeds up the scan process as we simply ignore stuff which we dont + * want to load from the SPL anyway. So the volumes which can be + * loaded in the above example are ids 0 - 7 + */ + +/* + * The struct definition is in drivers/mtd/ubispl/ubispl.h. It does + * not fit into the BSS due to the large buffer requirement of the + * upstream fastmap code. So the caller of ubispl_load_volumes needs + * to hand in a pointer to a free memory area where ubispl will place + * its data. The area is not required to be initialized. + */ +struct ubi_scan_info; + +typedef int (*ubispl_read_flash)(int pnum, int offset, int len, void *dst); + +/** + * struct ubispl_info - description structure for fast ubi scan + * @ubi: Pointer to memory space for ubi scan info structure + * @peb_size: Physical erase block size + * @vid_offset: Offset of the VID header + * @leb_start: Start of the logical erase block, i.e. offset of data + * @peb_count: Number of physical erase blocks in the UBI FLASH area + * aka MTD partition. + * @peb_offset: Offset of PEB0 in the UBI FLASH area (aka MTD partition) + * to the real start of the FLASH in erase blocks. + * @fastmap: Enable fastmap attachment + * @read: Read function to access the flash + */ +struct ubispl_info { + struct ubi_scan_info *ubi; + u32 peb_size; + u32 vid_offset; + u32 leb_start; + u32 peb_count; + u32 peb_offset; + int fastmap; + ubispl_read_flash read; +}; + +/** + * struct ubispl_load - structure to describe a volume to load + * @vol_id: Volume id + * @load_addr: Load address of the volume + */ +struct ubispl_load { + int vol_id; + void *load_addr; +}; + +/** + * ubispl_load_volumes - Scan flash and load volumes + * @info: Pointer to the ubi scan info structure + * @lovls: Pointer to array of volumes to load + * @nrvols: Array size of @lovls + */ +int ubispl_load_volumes(struct ubispl_info *info, + struct ubispl_load *lvols, int nrvols); + +#endif diff --git a/include/usb/dwc2_udc.h b/include/usb/dwc2_udc.h index 302e9a3..7324d8a 100644 --- a/include/usb/dwc2_udc.h +++ b/include/usb/dwc2_udc.h @@ -12,12 +12,17 @@ #define PHY0_SLEEP (1 << 5) struct dwc2_plat_otg_data { + void *priv; + int phy_of_node; int (*phy_control)(int on); unsigned int regs_phy; unsigned int regs_otg; unsigned int usb_phy_ctrl; unsigned int usb_flags; unsigned int usb_gusbcfg; + unsigned int rx_fifo_sz; + unsigned int np_tx_fifo_sz; + unsigned int tx_fifo_sz; }; int dwc2_udc_probe(struct dwc2_plat_otg_data *pdata); diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h index 586d32a..882aed4 100644 --- a/include/usb/ehci-ci.h +++ b/include/usb/ehci-ci.h @@ -160,7 +160,7 @@ #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR #define CONFIG_SYS_FSL_USB2_ADDR 0 #elif defined(CONFIG_LS102XA) -#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_LS102XA_USB1_ADDR +#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR #define CONFIG_SYS_FSL_USB2_ADDR 0 #endif |