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In case high region memory doesn't have enough space for Management
Complex (MC), the return value should indicate a failure so the
caller can handle it accordingly.
Signed-off-by: York Sun <york.sun@nxp.com>
Reported-by: Ebony Zhu <ebony.zhu@nxp.com>
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Suplements for patch 2e3dbee02915aaf75834747ff8753282118075dc
to cover LS1088A: USB3PHY Observing Intjermittent Failure in Rx
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
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Recently logic to enable RGMII tx delay was changed by
below patch.
"net: phy: realtek: fix enabling of the TX-delay for RTL8211F"
Based on the patch, here we are enabling the tx delay again.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
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Since TX delay is now enabled only in PHY_INTERFACE_MODE_RGMII_ID
PHY_INTERFACE_MODE_RGMII_TXID.
These change where introduced in phy driver in commit titled
"net: phy: realtek: fix enabling of the TX-delay for RTL8211F"
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
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On ls1012a soc, core clock source frequency is 100Mhz.
Generic timer frequency is derived from core clock source divided
by 4, which is 25Mhz. So assign timer frequency to 25Mhz here.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
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Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
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Enable non-secure access for PFE block.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
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Define init_pfe_scfg_dcfg_regs to configure scfg and dcfg
registers of pfe.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
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SoC specific PFE macros are defined and structure ccsr_scfg
is updated with members defined for PFE.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
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Call gemac_initialize to initialize both gemacs of pfe.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
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Ethernet support on all three LS1012A platforms(FRDM, QDS and RDB) is
enabled with this patch.
eth.c files for all 3 platforms contain board ethernet initialization
function and also function to reset phy.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
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Contains all the pfe header files.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
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pfe_command provides command line support for several features that
support pfe like starting or stopping the pfe, checking the health
of the processor engines and checking status of different unit inside
pfe.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
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This patch adds PFE driver into U-Boot.
Following are the main driver files:-
pfe.c: provides low level helper functions to initialize PFE internal
processor engines and other hardware blocks.
pfe_driver.c: provides probe functions, initialization functions
and packet send and receive functions.
pfe_eth.c: provides high level gemac, phy and mdio initialization
functions.
pfe_firmware.c: provides functions to load firmware into PFE
internal processor engines.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
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Layerscape Gen2 SoC supports GPIO registers to control GPIO
signals. Adding support of GPIO structure to access GPIO
registers.
Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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Memory allocated via malloc is not guaranteed to be zeroized.
So explicitly use calloc instead of malloc.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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The MC boot sequence is contained in mc_env_boot. Update LS1088A boards
to use this function, and hook it to reset_phy so that it's called late
enough, after the ports have been initialized, for proper DPC / DPL
fixup.
Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
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Signed-off-by: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com>
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QE_IRAM_READY should be set only after successfully uploading the
firmware.
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
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Fix a bug of 'commit 8104deb2d6b7 ("armv8: layerscape: Adjust memory
mapping for Flash/SD card on LS1046A")' as NAND block size is
256KB on LS1046AQDS.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
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Add a variable $kernelheader_addr_r used in
distroboot to validate kernel image as its absence
caused kernel validation failure
Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com>
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PPA loading during SPL stage is not required for nornal
SD boot scenario.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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PPA loading during SPL stage is not required for nornal
SD boot scenario.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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This file has some coding style problems. Fix these to make the future
updates easier.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
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IFC-NOR and QSPI-NOR signals are muxed on SoC to save pins
Add fsl_fdt_fixup_flash()
-To disable IFC-NOR node in dts if QSPI is enabled and vice-versa
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
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Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
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CCN-504 HPF registers were believed to be accessible only from EL3.
However, recent tests proved otherwise. Remove checking for exception
level to re-enable L3 cache flushing for all levels.
Signed-off-by: York Sun <york.sun@nxp.com>
Tested-by: Zhao Qiang <qiang.zhao@nxp.com>
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The implementation of function set_pcie_ns_access() uses a wrong
argument. The structure array ns_dev has a member 'ind' which is
initialized by CSU_CSLX_*. It should use the 'ind' directly to
address the PCIe's CSL register (CSL_base + CSU_CSLX_PCIE*).
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[YS: Revise commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
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Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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Enable validation of boot.scr script prior to its execution dependent
on "secureboot" flag in environment. Enable fall back option to
qspi boot in case of secure boot.
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com>
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Include common config_distro_defaults.h and config_distro_bootcmd.h
for u-boot enviroments to support automatical distro boot which
scan boot.scr from external storage devices(e.g. SD and USB)
and execute autoboot script.
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
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Include common config_distro_defaults.h and config_distro_bootcmd.h
for u-boot enviroments to support automatical distro boot which
scan boot.scr from external storage devices(e.g. SD and USB)
and execute autoboot script.
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
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Moves IR chip (IR36021) specific code in flag to resolve
compilation issue where it is not present. For example,
LS1088A is having a new LTC3882 voltage chip.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
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For most of ls2080ardb use-cases, mc private DRAM block is required
to be of 1.75GB.
Hence set mcmemsize=0x70000000 in default env
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
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This patch adds changes necessary to move functionality present in
PowerPC folders with ARM architectures that have DPAA1 QBMan hardware
- Created new board/freescale/common/portals.c to house shared device
tree fixups for DPAA1 devices with ARM and PowerPC cores
- Added new header file to top includes directory to allow files in
both architectures to grab the function prototypes
- Port inhibit_portals() from PowerPC to ARM. This function is used in
setup to disable interrupts on all QMan and BMan portals. It is
needed because the interrupts are enabled by default for all portals
including unused/uninitialised portals. When the kernel attempts to
go to deep sleep the unused portals prevent it from doing so
Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com>
Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
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Enable validation of boot.scr script prior to its execution dependent
on "secureboot" flag in environment.
Signed-off-by: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
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Enable validation of boot.scr script prior to its execution dependent
on "secureboot" flag in environment. Also enable "secureboot=y"
flag in environment for ARM based platforms instead of bootcmd.
Signed-off-by: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com>
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Corrects the channel number passed in i2c write operation for
LTC3882 voltage regulator.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
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"pci: layerscape: Fixup device tree node for ls2088a" added
support for LS208xA devices but fixing iommu-map property
is missing. This patch adds support for fixing iommu-map.
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
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This patch adjusts memory map for images on LS1012A
as per below memory map:
Image Flash Offset
RCW+PBI 0x00000000
Boot firmware (U-Boot) 0x00100000
Boot firmware Environment 0x00300000
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
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Enabled PCIe support and PCI command feature.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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LS1088A has the same PCIe controller as LS2088A, and the LS1088A
used LS2088A PCIe compatible under Linux.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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The pcie config space of ls1088a is different from ls2080a.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
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Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
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Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
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Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
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Enable support for loadables in SEC firmware FIT image. Currently support
is added for single loadable image.
Brief description of implementation:
- Add two more address pointers (loadable_h, loadable_l) as arguments to
sec_firmware_init() api.
- Create new api: sec_firmware_checks_copy_loadable() to check if loadables
node is present in SEC firmware FIT image. If present, verify loadable
image and copies it to secure DDR memory.
- Populate address pointers with secure DDR memory addresses where loadable
is copied.
Example use-case could be trusted OS (tee.bin) as loadables node in SEC
firmware FIT image.
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
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Change DDR allocated for secure memory from 2 MB to 66 MB. This additional
64 MB secure memory is required for trusted OS running in Trusted Execution
Environment using ARMv8 TrustZone.
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
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