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2015-10-27spi: designware_spi: Use BIT macroJagan Teki
Replace numerical bit shift with BIT macro in designware_spi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27spi: cadence_qspi_apb: Use BIT macroJagan Teki
Replace numerical bit shift with BIT macro in cadence_qspi_apb :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Acked-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27spi: bfin_spi6xx: Use BIT macroJagan Teki
Replace numerical bit shift with BIT macro in bfin_spi6xx :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27spi: atmel_spi: Use BIT macroJagan Teki
Replace numerical bit shift with BIT macro in atmel_spi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Bo Shen <voice.shen@atmel.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27spi: zynq_[q]spi: Use GENMASK macroJagan Teki
GENMASK macro used on zynq_spi.c and zynq_qspi.c GENMASK is used to create a contiguous bitmask([hi:lo]). Ex: (0x7 << 3) => GENMASK(5, 3) Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-27spi: zynq_[q]spi: Use BIT macroJagan Teki
Used BIT macro on zynq_spi.c and zynq_qspi.c :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25spi: zynq_qspi: Minor cleanupsJagan Teki
- Use __func__ on debug - Removed unnecessary comment - Fix function name in debug as zynq_qspi_xfer instead of spi_xfer Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25sf: Add FSR support to spi_flash_cmd_wait_readyJagan Teki
This patch adds flag status register reading support to spi_flash_cmd_wait_ready. Cc: Simon Glass <sjg@chromium.org> Cc: Marek Vasut <marex@denx.de> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Stefan Roese <sr@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Tom Rini <trini@konsulko.com> Cc: Hou Zhiqiang <B48286@freescale.com> Tested-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25sf: Update status reg check in spi_flash_cmd_wait_readyJagan Teki
Current flash wait_ready logic is not modular to add new register status check, hence updated the status check for adding few more register checks in future. Below are the sf speed runs with 'sf update' on whole flash, 16MiB. => sf update 0x100 0x0 0x1000000 device 0 whole chip 16777216 bytes written, 0 bytes skipped in 59.564s, speed 289262 B/s => sf update 0x100 0x0 0x1000000 device 0 whole chip 16777216 bytes written, 0 bytes skipped in 62.549s, speed 275036 B/s => sf update 0x100 0x0 0x1000000 device 0 whole chip 16777216 bytes written, 0 bytes skipped in 61.276s, speed 284359 B/s Cc: Simon Glass <sjg@chromium.org> Cc: Marek Vasut <marex@denx.de> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Stefan Roese <sr@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Tom Rini <trini@konsulko.com> Tested-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-25sf: Make flash->flags use for generic usageJagan Teki
Use the flash->flags for generic usage, not only for dm-spi-flash, this will be used for future flag additions. [Correct the spi flash flags detect logic] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25sf: Optimize BAR write codeJagan Teki
Optimized spi-flash bar writing code and also removed unnecessary bank_sel in read_ops. Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25sf: Add spi_flash_read_barJagan Teki
Add spi_flash_read_bar function for reading bar and discovering bar commands at probe time. Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25sf: Return bank_sel, if flash->bank_curr == bank_selJagan Teki
If computed bank_sel is same as flash->bank_curr which is computed at probe time, then return the bank_sel instead of zero. Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25spi: zynq_spi: Remove unneeded headersJagan Teki
- Removed unneeded inclusion of header files - Add "Xilinx" on license text Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25zynq-common: Add SPL SPI offset, size configsSiva Durga Prasad Paladugu
Define CONFIG_SYS_SPI_ARGS_OFFS, CONFIG_SYS_SPI_ARGS_SIZE and CONFIG_SYS_SPI_KERNEL_OFFS which will be used in SPL spi mode. These macros defines the device tree offset, size and the kernel image offset in flash respectively. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-10-25spi: zynq_qspi: Fix to configure CPOL, CPHA maskJagan Teki
priv->mode is initialized when .set_speed triggers with mode value, so checking mode for configuring CPOL, CPHA using priv->mode is invalid hence use mode from .set_speed argument, and at the end priv->mode will initialized with mode. This patch also replaces formatting string to use speed instead of mode in .set_speed ops. Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25zynq-common: Enable ISSI SPI-NOR flash supportJagan Teki
This patch enabled CONFIG_SPI_FLASH_ISSI for qspi on zynq boards. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com>
2015-10-25sf: params: Add IS25LP128 part supportJagan Teki
Added support for IS25LP128 flash part. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com>
2015-10-25sf: params: Add IS25LP064 part supportJagan Teki
Added support for IS25LP064 flash part. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com>
2015-10-25sf: params: Add IS25LP032 part supportJagan Teki
Added support for IS25LP032 flash part. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com>
2015-10-25spi: zynq_spi: Store cs value into private dataJagan Teki
Store cs value into private data and use it while activating chipselect instead of passing through function. Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25spi: zynq_spi: Rename baudrate divisor mask nameJagan Teki
Rename ZYNQ_SPI_CR_BRD_MASK to ZYNQ_SPI_CR_BAUD_MASK for more readable. Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25spi: zynq_spi: Add config reg shift named macrosJagan Teki
Update the numerical values for baudrate and chipselect with config reg shift named macro's Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25spi: Kconfig: Add Zynq QSPI controller entryJagan Teki
Add Zynq QSPI controller Kconfig entry. Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
2015-10-25configs: zynq: Enable zynq qspi controllerJagan Teki
Enable zynq qspi controller driver on respective zynq boards. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
2015-10-25zynq-common: Enable Bank/Extended address register supportJagan Teki
Enabled SPI flash Bank/Extended address register support. Bank/Extended address registers are used to access the flash which has size > 16MiB in 3-byte addressing. Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25zynq-common: Enable zynq qspi controller supportJagan Teki
This patch adds support for zynq qspi controller driver on zynq-common.h Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
2015-10-25configs: Enable legacy SPI flash interface supportJagan Teki
Enable legacy spi-flash interface support for boards which supports qspi controller with connected spi-nor flash. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
2015-10-25dts: zed: Enable zynq qspi controller nodeJagan Teki
Enabled zynq qspi controller node for zed board. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2015-10-25dts: zc770-xm010: Enable zynq qspi controller nodeJagan Teki
Enabled zynq qspi controller node for zc770-xm010 board. => sf probe 0 -- bus1 for selecting qspi controller => sf probe 1 -- bus0 for selecting spi controller Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2015-10-25dts: zc706: Enable zynq qspi controller nodeJagan Teki
Enabled zynq qspi controller node for zc706 board. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2015-10-25dts: zc702: Enable zynq qspi controller nodeJagan Teki
Enabled zynq qspi controller node for zc702 board. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2015-10-25dts: microzed: Enable zynq qspi controller nodeJagan Teki
Enabled zynq qspi controller node for microzed board, verified the same on spansion spi-nor flash. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
2015-10-25doc: device-tree-bindings: spi: Add zynq qspi infoJagan Teki
Added device-tree-binding information for zynq qspi controller driver. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
2015-10-25dts: zynq: Add zynq qspi controller nodesJagan Teki
This patch adds zynq qspi controller nodes in zynq-7000.dtsi. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
2015-10-25spi: Add zynq qspi controller driverJagan Teki
Added zynq qspi controller driver for Xilinx Zynq APSOC, this driver is driver-model driven with devicetree support. => sf probe SF: Detected S25FL128S_64K with page size 256 Bytes, erase size 64 KiB, total 16 MiB => mw.b 0x100 0xCC 0x1000000 => sf update 0x100 0x0 0x1000000 device 0 whole chip 16777216 bytes written, 0 bytes skipped in 59.842s, speed 289262 B/s => sf read 0x3000000 0x0 0x1000000 device 0 whole chip SF: 16777216 bytes @ 0x0 Read: OK => cmp.b 0x3000000 0x100 0x1000000 Total of 16777216 byte(s) were the same Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
2015-10-24common/board_f.c: modify the macro to use get_clocks() more commonGong Qianyu
get_clocks() should not be limited by ESDHC. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
2015-10-24arm, powerpc: select SYS_GENERIC_BOARDMasahiro Yamada
We have finished Generic Board conversion for ARM and PowerPC, i.e. all the boards have been converted except OpenRISC, SuperH, SPARC, which have not supported Generic Board framework yet. Select SYS_GENERIC_BOARD in arch/Kconfig and delete all the macro defines in include/configs/*.h. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-10-24Revert "ARM: zynq: disable CONFIG_SYS_MALLOC_F to fix MMC boot"Simon Glass
This reverts commit 321f86e18d6aae9f7b7ba3ef1eb0cec769481874. The original bug has been fixed. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-on: Zedboard and ZC706 board Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-on: zc702 Tested-by: Michal Simek <michal.simek@xilinx.com>
2015-10-24zynq: Move SPL console init out of board_init_f()Simon Glass
We should not init the console this early since it precludes using driver model for the UART, since it is not set up at the start of board_init_f(). See the README for more information. The debug UART does not have this restriction. If we want to do early init with the console on it can be done in spl_board_init(). Move the preloader_console_init() call from board_init_f() to board_init_r(). Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Michal Simek <michal.simek@xilinx.com>
2015-10-24microblaze: Add a TODO to call board_init_f_mem()Simon Glass
This C function should be used to do the early memory layout and init. This is beyond my powers, so just add a TODO for the maintainer. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Michal Simek <michal.simek@xilinx.com>
2015-10-24arm: Switch 32-bit ARM to using generic global_data setupSimon Glass
There is quite a bit of assembler code that can be removed if we use the generic global_data setup. Less arch-specific code makes it easier to add new features and maintain the start-up code. Drop the unneeded code and adjust the hooks in board_f.c to cope. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-10-24arm: Switch aarch64 to using generic global_data setupSimon Glass
There is quite a bit of assembler code that can be removed if we use the generic global_data setup. Less arch-specific code makes it easier to add new features and maintain the start-up code. Drop the unneeded code and adjust the hooks in board_f.c to cope. Tested on LS2085ARDB and LS2085AQDS (armv8 SoC). Tested-by: York Sun <yorksun@freescale.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2015-10-24board_init_f_mem(): Don't create an unused early malloc() areaSimon Glass
Change the #ifdef so that the early malloc() area is not set up in SPL if CONFIG_SYS_SPL_MALLOC_START is defined. In that case it would never actually be used, and just chews up stack space. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-10-24board_init_f_mem(): Don't require memset()Simon Glass
Unfortunately memset() is not always available, so provide a substitute when needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-10-24Move board_init_f_mem() into a common locationSimon Glass
This function will be used by both SPL and U-Boot proper. So move it into a common place. Also change the #ifdef so that the early malloc() area is not set up in SPL if CONFIG_SYS_SPL_MALLOC_START is defined. In that case it would never actually be used, and just chews up stack space. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-10-24fs-test.sh: fix pre-requisite detectionStephen Warren
In the following snippet: if [ ! -x `which $prereq` ]; then When $prereq does not exist, `which $prereq` evaluates to the empty string, which results in *no* argument being passed to the -x operator, which then evaluates to true, which is the equivalent of the prereq having been found. In order for this to fail as expected, we must pass an empty argument, which then causes -x to fail. Do this by wrapping the `` in quotes so there's always an argument to -x, even if the value of the argument is zero-length. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2015-10-24test: fat: add test of non-contiguous file readsStephen Warren
In my patch series to replace fs/fat with "ff.c", I enhanced ff.c to optimize file reading, so that reads of contiguous clusters are submitted to the IO device as a single read. This test attempts to torture-test edge-cases of that enhancement. BTW, the only way I found to validate that this script actually does create non-contiguous files was to manually inspect the FAT bitmap in a hex dump of the FAT image. hdparm --fibmap doesn't work on loop-mounted filesystems. filefrag -v -e seems to lie about files being contiguous when they aren't. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2015-10-24itest: make memory access work under sandboxStephen Warren
itest accesses memory, and hence must map/unmap it. Without doing so, it accesses invalid addresses and crashes. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-10-24distro_bootcmd: Add support for booting from ubifsRoy Spliet
Under the assumptions of having a UBI volume called boot, containing a ubifs filesystem. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Stephen Warren <swarren@nvidia.com>
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