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2014-08-20imx: ventana: add iomux for PCISKT_WDIS# gpioTim Harvey
The PCISKT_WDIS# gpio allows for asserting WDIS# going to the various PCIe sockets on the Ventana board. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-08-20imx: ventana: enable SION bit on gpio outputsTim Harvey
Enable the SION bit on gpio outputs that we wish to be able to read the value of. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-08-20imx: ventana: configure i2c_dis# pin properly for gw53xxTim Harvey
The i2c_dis# pinmux/padconf was missing for the GW53xx (this feature was added to the GW53xx on revB PCB's). Additionally, remove the duplicate config for GW54xx. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-08-20imx: ventana: add missing crlf to printTim Harvey
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-08-20imx: ventana: add video enable gpio pinmux for GW54xxTim Harvey
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-08-20imx: ventana: add appropriate delay following GSC i2c writeTim Harvey
The Gateworks System Controller EEPROM config is flash based. Add a delay following writes to avoid errors on back-to-back writes. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-08-20imx: ventana: remove caam disable per eeprom bitTim Harvey
During manufacturing this bit is not getting enabled when it should be, so we will ignore it. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-08-20imx: ventana: set dynamic env var for flash layoutTim Harvey
NAND devices have differing layouts with respect to page size and pages per block. These parameters affect the parameters that need to be passed to mkfs.ubifs and ubinize used to create UBI images. The various NAND chips supported by Gateworks Ventana fall into two different layouts which we refer to as 'normal' and 'large'. This layout is useful when referencing ubi files to download and flash so we create a dynamic env variable for it. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-08-20mx6sxsabresd: Update DDR initializationFabio Estevam
Use the latest DDR initialization values suggested by the FSL hardware team. While at it, add some comments for clarification. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-20pci: mx6: fix occasional link failuresTim Harvey
According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable for SS function) must remain deasserted until the reference clock is running at the appropriate frequency. Without this patch we find a high link failure rate (>5%) on certain IMX6 boards at various temperatures. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-20ARM: mx6: Enable Thumb build for SPLMarek Vasut
Building the SPL in Thumb mode saves roughly 30% in size of the resulting SPL binary. As the size of SPL it limited on the MX6, this helps a lot. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Tim Harvey <tharvey@gateworks.com>
2014-08-20ARM: mx6: Handle the MMDCx_MDCTL COL field capricesMarek Vasut
The COL field value cannot be easily calculated from the desired column number. Instead, there are special cases for that, see the datasheet, MMDCx_MDCTL field description, field COL . Cater for those special cases. Signed-off-by: Marek Vasut <marex@denx.de>
2014-08-20ARM: mx6: Prevent overflow in DRAM size detectionMarek Vasut
The MX6 DRAM controller can be configured to handle 4GiB of DRAM, but only 3840 MiB of that can be really used. In case the controller is configured to operate a 4GiB module, the imx_ddr_size() function will correctly compute that there is 4GiB of DRAM in the system. Firstly, the return value is 32-bit, so the function will effectively return zero. Secondly, the MX6 cannot address the full 4GiB, but only 3840MiB of all that. Thus, clamp the returned size to 3840MiB in such case. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Tim Harvey <tharvey@gateworks.com>
2014-08-20ARM: mx5: Fix CHSCCDR nameMarek Vasut
Fix the name of the CCM CHSCCDR register. Signed-off-by: Marek Vasut <marex@denx.de>
2014-08-20mx31pdk: Change maintainerFabio Estevam
Currently I don't have access to a mx31pdk board. Magnus was the original maintainer of the board and accepted to take back this role. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Magnus Lilja <lilja.magnus@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
2014-08-20mx6: add support of multi-processor commandGabriel Huau
This allows u-boot to load different OS or Bare Metal application on different cores of the i.MX6 SoC. For example: running Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1. Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Acked-by: Stefano Babic <sbabic@denx.de>
2014-08-13embest/mx6boards: only toggle eMMC usdhc3 RST line on MarSboardIain Paton
On MarS usdhc3 is eMMC, on RIoT usdhc3 is uSD and eMMC is usdhc4. Don't run the MarS specific eMMC reset code on usdhc3 when board_type == BOARD_IS_RIOTBOARD Signed-off-by: Iain Paton <ipaton0@gmail.com>
2014-08-13Update aristainetos board to KconfigStefano Babic
aristainetos board was merged in u-boot-imx before Kconfig was integrated, but it is not yet mainline. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
2014-08-11Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic
Conflicts: boards.cfg Signed-off-by: Stefano Babic <sbabic@denx.de>
2014-08-09Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master'Albert ARIBAUD
2014-08-08i.MX31 PDK: Enable generic board for i.MX31 PDKMagnus Lilja
Enable CONFIG_SYS_GENERIC_BOARD for the i.MX31 PDK board. Tested on actual hardware. Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-08pmic: pmic_pfuze100: Use a shorter name for PMIC nameFabio Estevam
It is redundant to use 'PFUZE100_PMIC' as the PMIC name because we already know it is a PMIC. Call it simply 'PFUZE100' instead. Cc: Tim Harvey <tharvey@gateworks.com> Cc: Markus Niebel <Markus.Niebel@tq-group.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-08mx6: crm_regs: Fix MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADEDFabio Estevam
According to the Reference Manual the 'mask_periph2_clk_sel_loaded' field of register CCM_CIMR corresponds to bit 19 so fix its definition accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-08mx6: crm_regs: Fix MXC_CCM_CLPCR_WB_PER_AT_LPM definitionFabio Estevam
According to the Reference Manual the 'wb_per_at_lpm' field of register CCM_CLPCR corresponds to bit 16 so fix its definition accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-08mx6: crm_regs: Fix CDCDR_SPDIF0_CLK_PODF mask and offsetFabio Estevam
According to the Reference Manual the 'spdif0_clk_podf' field of register CCM_CDCDR corresponds to bits 22, 23 and 24, so fix the mask and offset definitions accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-08mx6: imx-regs: Remove unused 'omux' field from iomux structFabio Estevam
'omux' field is not used anywhere and such layout is not valid for mx6solox. Instead of adding more ifdef's into the structure, let's simply remove this unused 'omux' field. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
2014-08-08arm: m53evk: Fix RTC bus numberMarek Vasut
A previous update to the I2C stack introduced a typo in the configuration option. Fix the typo and therefore allow the RTC to work correctly with the 'date' command again. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
2014-08-08Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic
2014-08-06Prepare v2014.10-rc1Tom Rini
Signed-off-by: Tom Rini <trini@ti.com>
2014-08-06Change Andy Fleming's email addressAndy Fleming
Messages to afleming@freescale.com now bounce, and should be directed to my personal address at afleming@gmail.com Signed-off-by: Andy Fleming <afleming@gmail.com>
2014-08-06The _config target is not present anymore, mention _defconfig insteadHolger Freyther
The _config part is gone for sure, the _defconfig target could at least work. I have not verified this for all targets though.
2014-08-06git-mailrc: add a kconfig aliasStephen Warren
It's easier to Cc Masahiro on Kconfig-related changes with a git-mailrc alias. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-06doc: README.SPL: adjust for Kbuild and KconfigMasahiro Yamada
Reflect the latest build system to doc/README.SPL. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-06doc: delete README.ARM-SoCMasahiro Yamada
This document is too old and useless. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-06Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini
2014-08-06Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini
2014-08-05spi, spi_mxc: do not hang in spi_xchg_singleHeiko Schocher
if status register do never set MXC_CSPICTRL_TC, spi_xchg_single endless loops. Add a timeout here to prevent endless hang. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Dirk Behme <dirk.behme@gmail.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-08-05spi: Support half-duplex mode in FDT decodeSimon Glass
This parameter should also be supported. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-08-05exynos: spi: Fix calculation of SPI transaction start timeSimon Glass
The SPI transaction delay is supposed to be measured from the end of one transaction to the start of the next. The code does not work that way, so fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-08-05cros_ec: Fix two bugs in the SPI implementationSimon Glass
An incorrect message version is passed to the EC in some cases and the parameters of one function are switched. Fix these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-08-05sf: sf_ops: Stop leaking memoryMarek Vasut
It's usually a common pattern to free() the memory that we allocated. Implement this here to stop leaking memory. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-08-04Merge http://git.denx.de/u-boot-dmTom Rini
2014-08-04arm: Support pre-relocation malloc()Simon Glass
Add support for re-relocation malloc() in arm's start-up code. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-04arm: Set up global data before board_init_f()Simon Glass
At present arm defines CONFIG_SYS_GENERIC_GLOBAL_DATA, meaning that the global_data pointer is set up in board_init_f(). However it is actually set up before this, it just isn't zeroed. If we zero the global data before calling board_init_f() then we don't need to define CONFIG_SYS_GENERIC_GLOBAL_DATA. Make this change (on arm32 only) to simplify the init process. I don't have the ability to test aarch64 yet. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Tom Rini <trini@ti.com>
2014-08-01kmp204x: prepare to use CPU watchdogBoschung, Rainer
This patch configures the qrio to trigger a core reset on a CPU reset request. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-01kmp204x/qrio: support for setting the CPU reset request modeBoschung, Rainer
To acheive this, the qrio_uprstreq() function that sets the UPRSTREQN flag in the qrio RESCNF reg is added. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-01kmp204x: set CPU watchdog reset reason flagBoschung, Rainer
Check the core timer status register (TSR) for watchdog reset, and and set the QRIO's reset reason flag REASON1[0] accordingly. This allows the appliction SW to identify the cpu watchdog as a reset reason, by setting the REASON1[0] flag in the QRIO. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-01kmp204x/qrio: prepare support for the CPU watchdog reset reasonBoschung, Rainer
To achieve this, the qrio_cpuwd_flag() function that sets the CPU watchdog flag in the REASON1 reg is added. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-01kmp204x: CPU watchdog enabledBoschung, Rainer
The booting of the board is now protected by the CPU watchdog. A failure during the boot phase will end up in board reset. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-01powerpc: mpc85xx watchdog init added to init_funcBoschung, Rainer
When CONFIG_WATCHDOG is defined the board initialization just performs a WATCHDOG_RESET, an initialization of the watchdog is not done. This has been modified fot the MPC85xx, the board initialization calls its watchdog initialitzation allowing for full watchdog configuration very early in the boot phase. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
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