summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2012-07-19net: link_local: fix buildbenoit.thebaudeau@advans
Fix comment within comment build error. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Joe Hershberger <joe.hershberger@gmail.com>
2012-07-19net: bootp: fix buildbenoit.thebaudeau@advans
Fix NetSetState function name used with CONFIG_BOOTP_MAY_FAIL. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Joe Hershberger <joe.hershberger@gmail.com>
2012-07-19net: fec_mxc: Fix MDC for xMIIbenoit.thebaudeau@advans
The MDC signal is available on all xMII (i.e. 'not 7-wire') interfaces, so mii_speed has to be set for all these interfaces, and not only for MII. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
2012-07-19net: fec_mxc: Fix setting of RCR for xMIIbenoit.thebaudeau@advans
At least on i.MX25, the RMII mode did not work, which is fixed by this patch. The MII_MODE bit of the FEC RCR register means xMII, i.e. 'not 7-wire', so set it accordingly. According to the xMII and 7-wire (aka GPSI) standards, full duplex should be available on xMII, but not on 7-wire, so set FCE accordingly. The FEC may support full duplex for 7-wire too, but the reference manual does not say that, so avoid an invalid assumption. Actually, the choice between half and full duplex also depends on the endpoint/switch/repeater configuration, so a config option could be added for that, but there has been no need for it so far. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
2012-07-19Blackfin: bfin_mac: drop volatile markings on packet buffersMike Frysinger
Now that common code doesn't declare these as volatile, we don't need to either anymore. This fixes the build warning: bfin_mac.c: In function 'bfin_EMAC_recv': bfin_mac.c:193:23: warning: assignment discards qualifiers from pointer target type Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-07-18usb_storage: fix ehci driver max transfer sizeStefan Herbrechtsmeier
The commit 5dd95cf93dfffa1d19a1928990852aac9f55b9d9 'usb_storage: Fix EHCI "out of buffer pointers" with CD-ROM' introduce a bug in usb_storage as it wrongly assumes that every transfer can use 4096 bytes per qt_buffer. This is wrong if the start address of the data is not page aligned to 4096 bytes and leads to 'EHCI timed out on TD' messages because of 'out of buffer pointers' in ehci_td_buffer function. The bug appears during load of a fragmented file and read from or write to an unaligned memory address. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
2012-07-18smsc95xx: align buffers to cache line sizeIlya Yanok
Align buffers passed to the USB code to cache line size so they can be DMAed safely. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-07-18ehci-hcd: change debug() to printf() in case of errorsIlya Yanok
Printing message could be useful if something goes really wrong. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-07-18usb: check return value of submit_{control, bulk}_msgIlya Yanok
Return values of submit_{control,bulk}_msg() functions should be checked to detect possible error. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-07-18usb: pass cache-aligned buffer to usb_get_descriptor()Ilya Yanok
usb_get_descriptor passes it's buffer argument directly to usb_control_msg() so it has to be properly aligned/padded. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-07-18ehci-hcd: fix external buffer cache handlingIlya Yanok
Buffer coming from upper layers should be cacheline aligned/padded to perform safe cache operations. For now we don't do bounce buffering so getting unaligned buffer is an upper layer error. We can't check if the buffer is properly padded with current interface so just assume it is (consider changing with in the future). The following changes are done: 1. Remove useless length alignment check. We get actual transfer length not the size of the underlying buffer so it's perfectly valid for it to be unaligned. 2. Move flush_dcache_range() out of while loop or it will flush too much. 3. Don't try to fix buffer address before calling invalidate: if it's unaligned it's an error anyway so let cache subsystem cry about that. 4. Fix end buffer address to be cacheline aligned assuming upper layer reserved enough space. This is potentially dangerous operation so upper layers should be careful about that. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-07-18ehci-hcd.c, musb_core, usb.h: Add USB_DMA_MINALIGN define for cache alignmentTom Rini
The USB spec says that 32 bytes is the minimum required alignment. However on some platforms we have a larger minimum requirement for cache coherency. In those cases, use that value rather than the USB spec minimum. We add a cpp check to <usb.h> to define USB_DMA_MINALIGN and make use of it in ehci-hcd.c and musb_core.h. We cannot use MAX() here as we are not allowed to have tests inside of align(...). Signed-off-by: Tom Rini <trini@ti.com> [marek.vasut]: introduce some crazy macro voodoo Signed-off-by: Marek Vasut <marex@denx.de> [ilya.yanok]: moved external buffer fixes to separate patch, we use {ALLOC,DEFINE}_ALIGN_BUFFER macros with alignment of USB_DMA_MINALIGN for qh_list, qh and qtd structures to make sure they are proper aligned for both controller and cache operations. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-07-18ehci-hcd: program asynclistaddr before every transferIlya Yanok
Move or_asynclistaddr programming to ehci_submit_async() function to make sure queue head is properly programmed before every transfer. This solves the problem with changing qh address. Also remove unneeded qh_list->qh_link reprogramming at the end of transfer. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-07-18common.h: Introduce DEFINE_CACHE_ALIGN_BUFFERMarek Vasut
This is the out-of-function-scope counterpart of ALLOC_CACHE_ALIGN_BUFFER. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> [ilya.yanok]: added missing <linux/compiler.h> include and {DEFINE,ALLOC}_ALIGN_BUFFER macros allowing explicit alignment specification. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-07-18ehci-omap: Do not call dcache_off from omap_ehci_hcd_initTom Rini
This has never been completely sufficient and now happens too late to paper over the cache coherency problems with the current USB stack. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-07-18Merge branch 'next' of git://git.denx.de/u-boot-videoWolfgang Denk
* 'next' of git://git.denx.de/u-boot-video: ipu_common: Add ldb_clk for use in parenting the pixel clock ipu_common: Do not hardcode the ipu_clk frequency ipu_common: Rename MXC_CCM_BASE ipu_common: Let clk_ipu_enable/disable only run on MX51 and MX53 ipu_common: Only apply the erratum to MX51 video: Rename CONFIG_VIDEO_MX5 mx6: Allow mx6 to access the IPUv3 registers common lcd: minor coding style changes Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-18Merge branch 'master' of git://git.denx.de/u-boot-niosWolfgang Denk
* 'master' of git://git.denx.de/u-boot-nios: nios2: move gd and bd into BSS Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-16nios2: move gd and bd into BSSThomas Chou
As suggested by Graeme Russ, move gd and bd data structrures to BSS instead of calculating the locations around the stack and heap. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-07-13FSL/eSDHC: enable the clock to detect the SD cardJerry Huang
For FSL low-end processors (VVN2.2), in order to detect the SD card, we should enable PEREN, HCKEN and IPGEN to enable the clock. Otherwise, after booting the u-boot, and then inserting the SD card, the SD card can't be detected. For SDHC VVN2.3 IP, these bits are reserved, and SDCLKEN is used. And when accessing to these reserved bit, no any impact happened. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> CC: Andy Fleming <afleming@gmail.com> CC: Marek Vasut <marex@denx.de> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-07-13SD/MMC: check the card status during erase operationJerry Huang
Use the function 'mmc_send_status' to check the card status. only when the card is ready, driver can send the next erase command to the card, otherwise, the erase will failed: => mmc erase 0 1 MMC erase: dev # 0, block # 0, count 1 ... 1 blocks erase: OK => mmc erase 0 2 MMC erase: dev # 0, block # 0, count 2 ... mmc erase failed 1 blocks erase: ERROR => mmc erase 0 4 MMC erase: dev # 0, block # 0, count 4 ... mmc erase failed 1 blocks erase: ERROR Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> CC: Andy Fleming <afleming@gmail.com> CC: Marek Vasut <marex@denx.de> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-07-13mmc:fix Call mmc_init() when executing mmc_get_dev()Łukasz Majewski
This code adds call to mmc_init(), for partition related commands (e.g. fatls, fatinfo etc.). It is safe to call mmc_init() multiple times since mmc->has_init flag prevents from multiple initialization. The FAT related code calls get_dev high level method and then uses elements from mmc->block_dev, which is uninitialized until the mmc_init (and thereof mmc_startup) is called. This problem appears on boards, which don't use mmc as the default place for envs Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-07-13mmc: remove the hard setting for tran_speedJaehoon Chung
mmc_set_clock is set to the hard-coding. But i think good that use the tran_speed value. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-07-13i.MX: fsl_esdhc: allow use with cache enabled.Eric Nelson
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-07-12net: nfs: make NFS_TIMEOUT configurableTetsuyuki Kobayashi
NFS_TIMEOUT is constant value defined in net/nfs.c. But sometimes it needs to adjust. This patch enables to override NFS_TIMEOUT by defining CONFIG_NFS_TIMEOUT in a board specific config file. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
2012-07-12Merge branch 'next' of git://git.denx.de/u-boot-net into nextWolfgang Denk
* 'next' of git://git.denx.de/u-boot-net: net: Inline the new eth_setenv_enetaddr_by_index function net: allow setting env enetaddr from net device setting net/designware: Consecutive writes to the same register to be avoided CACHE: net: asix: Fix asix driver to work with data cache on net: phy: micrel: make ksz9021 phy accessible net: abort network initialization if the PHY driver fails phylib: phy_startup() should return an error code on failure net: tftp: fix type of block arg to store_block Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-12Merge branch 'master' of git://git.denx.de/u-boot-i2cWolfgang Denk
* 'master' of git://git.denx.de/u-boot-i2c: mx28evk: Add I2C support mxs-i2c: Fix internal address byte order mxc_i2c: remove setting speed at each start mx6qsabrelite: add i2c support mxc_i2c: specify i2c base address in config file Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-11net: Inline the new eth_setenv_enetaddr_by_index functionJoe Hershberger
This function is currently only used in one case. Inline for now. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-07-11net: allow setting env enetaddr from net device settingRob Herring
If the net driver has setup a valid ethernet address and an ethernet address is not set in the environment already, then set the environment variables from the net driver setting. This enables pxe booting on boards which don't set ethaddr env variable. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2012-07-11net/designware: Consecutive writes to the same register to be avoidedDinh Nguyen
This commit is an add-on to f6c4191f. There are a few registers where consecutive writes to the same location should be avoided or have a delay. According to Synopsys, here is a list of the registers and bit(s) where consecutive writes should be avoided or a delay is required: DMA Registers: Register 0 Bit 7 Register 6 All bits except for 24, 16-13, 2-1. GMAC Registers: Registers 0-3 All bits Registers 6-7 All bits Register 10 All bits Register 11 All bits except for 5-6. Registers 16-47 All bits Register 48 All bits except for 18-16, 14. Register 448 Bit 4. Register 459 Bits 0-3. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Matthew Gerlach <mgerlach@altera.com> Acked-by: Amit Virdi <amit.virdi@st.com>
2012-07-11CACHE: net: asix: Fix asix driver to work with data cache onMarek Vasut
The asix driver did not align buffers, therefore it didn't work with data cache enabled. Fix this. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@gmail.com>
2012-07-11net: phy: micrel: make ksz9021 phy accessibleTroy Kisky
Micrel accidentally used the same part number for the KS8721 and KSZ9021. So, both cannot be in the same build of u-boot. Add a config option to handle this. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Vladimir Zapolskiy <vz@mleia.com>
2012-07-11net: abort network initialization if the PHY driver failsTimur Tabi
Now that phy_startup() can return an actual error code, check for that error code and abort network initialization if the PHY fails. Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Nobuhiro Iwamamatsu <nobuhiro.iwamatsu.yj@renesas.com> (sh_eth part) Acked-by: Stephan Linz <linz@li-pro.net> (Xilinx part, xilinx_axi_emac and xilinx_ll_temac) Reviewed-by: Marek Vasut <marex@denx.de> (FEC part)
2012-07-11phylib: phy_startup() should return an error code on failureTimur Tabi
phy_startup() calls the PHY driver's startup function, but it ignores the return code from that function, and so it never returns any failures. Signed-off-by: Timur Tabi <timur@freescale.com>
2012-07-11net: tftp: fix type of block arg to store_blockJayachandran Chandrasekharan Nair
The block argument for store_block can be -1 when the tftp sequence number rolls over (i.e TftpBlock == 0), so the first argument to store_block has to be of type 'int' instead of 'unsigned'. In our environment (gcc 4.4.5 mips toolchain), this causes incorrect 'offset' to be generated for storing the block, and the tftp block with number 0 will be written elsewhere, resulting in a bad block in the downloaded file and a memory corruption. Signed-off-by: Jayachandran Chandrasekharan Nair <jayachandranc@netlogicmicro.com>
2012-07-11mx28evk: Add I2C supportFabio Estevam
Add I2C support. Tested by placing a 24LC16 EEPROM into the U50 slot which comes empty from factory. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
2012-07-11mxs-i2c: Fix internal address byte orderTorsten Fleischer
Large EEPROMs, e.g. 24lc32, need 2 byte to address the internal memory. These devices require that the high byte of the internal address has to be written first. The mxs_i2c driver currently writes the address' low byte first. The following patch fixes the byte order of the internal address that should be written to the I2C device. Signed-off-by: Torsten Fleischer <to-fleischer@t-online.de> CC: Marek Vasut <marex@denx.de> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
2012-07-11mxc_i2c: remove setting speed at each startTroy Kisky
Other then being very weird, this code was also wrong. For example, say I set speed to 100K. I'll read back the speed as 85937. But the speed is really 85937.5, so we I reset the speed to 85937, I'll get 73660.7. After a couple of transactions my speed is now exactly 68750 so it will remain there. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
2012-07-11mx6qsabrelite: add i2c supportTroy Kisky
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
2012-07-11mxc_i2c: specify i2c base address in config fileTroy Kisky
The following platforms had their config files changed flea3, imx31_phycore, mx35pdk, mx53ard, mx53evk, mx53smd and mx53loco. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
2012-07-10net: fix typo in arp clean upMike Frysinger
The clean up patch missed an &, so we end up passing an int rather than a pointer to the sprintf function. arp.c: In function 'ArpReceive': arp.c:197: warning: format '%p' expects type 'void *', but argument 3 has type 'int' Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-07-10net/sh-ether: Fix build by removing ECSIPR_BRCRXIP and otherNobuhiro Iwamatsu
When support sh7734 of sh-ether, ECSIPR_BRCRXIP and other were removed. Therefore SH7757 and SH7724 can not build. This revise this probelem. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
2012-07-10ipu_common: Add ldb_clk for use in parenting the pixel clockEric Nelson
Add ldb_clk for use in parenting the pixel clock. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-10ipu_common: Do not hardcode the ipu_clk frequencyFabio Estevam
Do not hardcode the ipu_clk frequency and let the board file pass this value. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-10ipu_common: Rename MXC_CCM_BASEFabio Estevam
Rename MXC_CCM_BASE to CCM_BASE_ADDR as this is already defined for MX6. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-10ipu_common: Let clk_ipu_enable/disable only run on MX51 and MX53Fabio Estevam
The registers accessed inside clk_ipu_enable/disable are not present on MX6, so make sure they only run on MX51 and MX53. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-10ipu_common: Only apply the erratum to MX51Fabio Estevam
The following erratum : "ENGcm08316 IPU: Clarification regarding the bypass mode registers setup for display and camera interfaces" only applies to mx51, so restrict its usage for this SoC only. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-10video: Rename CONFIG_VIDEO_MX5Fabio Estevam
Rename CONFIG_VIDEO_MX5 as this driver can also be used on mx6. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-10mx6: Allow mx6 to access the IPUv3 registersFabio Estevam
Adjust the IPUv3 registers, so that the IPUv3 driver can be extended for mx6 as well. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-10common lcd: minor coding style changesNikita Kiryanov
No functional changes Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
2012-07-10Prepare v2012.07-rc1Wolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
generated by cgit v0.10.2 at 2024-08-17 23:59:08 (GMT)