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2016-12-01arm: mvebu: move SYS_MVEBU_PLL_CLOCK to KconfigChris Packham
The main PLL frequency is 2GHz for Armada-XP and 1GHZ for Armada 375, 38x and 39x. [ Linux commit ae142bd9976532aa5232ab0b00e621690d8bfe6a ] Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2016-12-01mvebu: db-88f6820-amc: Enable FIT supportChris Packham
Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2016-12-01ts4600: Disable CONFIG_DISPLAY_CPUINFOTom Rini
Without this change we see: ../arch/arm/cpu/arm926ejs/mxs/mxs.c: In function ‘print_cpuinfo’: ../arch/arm/cpu/arm926ejs/mxs/mxs.c:181:23: warning: unused variable ‘data’ [-Wunused-variable] ../arch/arm/cpu/arm926ejs/mxs/mxs.c:180:6: warning: variable ‘cpurev’ set but not used [-Wunused-but-set-variable] So the easy solution is to disable CONFIG_DISPLAY_CPUINFO Reviewed-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2016-12-01Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini
2016-12-01travis.yml: Split Freescale ARM job up moreTom Rini
In order to avoid running into the time limit, split the 32bit and 64bit Freescale boards into separate jobs. We could either pass "freescale & armv8" to buildman or exclude all of the 32bit CPUs. While the former is shorter I fear the amount of possible escaping required would make things less readable. Signed-off-by: Tom Rini <trini@konsulko.com>
2016-11-30MIPS: Fix map_physmem for cached mappingsPaul Burton
map_physmem should return a pointer that can be used by the CPU to access the given memory - on MIPS simply returning the physical address as it does prior to this patch doesn't achieve that. Instead return a pointer to the memory within (c)kseg0, which matches up consistently with the (c)kseg1 pointer that uncached mappings return via ioremap. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-11-30MIPS: Use ram_top, not bi_memsize, in arch_lmb_reservePaul Burton
When calculating the region to reserve for the stack in arch_lmb_reserve, make use of ram_top instead of adding bi_memsize to CONFIG_SYS_SDRAM_BASE. This avoids overflow if the system has enough memory to reach the end of the address space. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-11-30mips: Let cache.h be included from assembly sourceMarek Vasut
Add ifdef __ASSEMBLY__ around the function prototype to let cache.h be included from assembly code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com>
2016-11-30common/board_f: enable initr_trap for MIPSDaniel Schwierzeck
Enable initr_trap hook also for MIPS to install and enable U-Boot's specific MIPS exception handlers. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-11-30MIPS: add handling for generic and EJTAG exceptionsDaniel Schwierzeck
Add exception handlers for generic and EJTAG exceptions. Most of the assembly code is imported from Linux kernel and adapted to U-Boot. The exception vector table will be reserved above the stack before U-Boot is relocated. The exception handlers will be installed and activated after relocation in the initr_traps hook function. Generic exceptions are handled by showing a CPU register dump similar to Linux kernel. For example: malta # md 1 00000001: Ooops: $ 0 : 00000000 00000000 00000009 00000004 $ 4 : 8ff7e108 00000000 0000003a 00000000 $ 8 : 00000008 00000001 8ff7cd18 00000004 $12 : 00000002 00000000 00000005 0000003a $16 : 00000004 00000040 00000001 00000001 $20 : 00000000 8fff53c0 00000008 00000004 $24 : ffffffff 8ffdea44 $28 : 90001650 8ff7cd00 00000004 8ffe6818 Hi : 00000000 Lo : 00000004 epc : 8ffe6848 (text bfc28848) ra : 8ffe6818 (text bfc28818) Status: 00000006 Cause : 00000410 (ExcCode 04) BadVA : 8ff9e928 PrId : 00019300 ### ERROR ### Please RESET the board ### EJTAG exceptions are checked for SDBBP and delegated to the SDBBP handler if necessary. Otherwise the debug mode will simply be exited. The SDBBP handler currently prints the contents of registers c0_depc and c0_debug. This could be extended in the future to handle semi-hosting according to the MIPS UHI specification. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Tested-by: Paul Burton <paul.burton@imgtec.com>
2016-11-30MIPS: reserve space for exception vectorsDaniel Schwierzeck
In order to set own exception handlers, a table with the exception vectors must be built in DRAM and the CPU EBase register must be set to the base address of this table. Reserve the space above the stack and use gd->irq_sp as storage for the exception base address. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-11-30MIPS: add asm-offsets for struct pt_regsDaniel Schwierzeck
Import asm-offsets.c from kernel to generate offset for struct pt_regs needed by exception handlers. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-11-30MIPS: add possibility to setup initial stack and global data in SRAMDaniel Schwierzeck
This adds a new Kconfig option CONFIG_MIPS_INIT_STACK_IN_SRAM which a SoC can select if it supports some kind of SRAM. Together with CONFIG_SYS_INIT_SP_ADDR the initial stack and global data can be set up in that SRAM. This can be used to provide a C environment also for lowlevel_init(). Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-11-30MIPS: factor out code for initial stack and global dataDaniel Schwierzeck
Move the code for setting up the initial stack and global data to a macro to be able to use it more than once. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-11-30MIPS: fix iand optimize setup of CP0 registersDaniel Schwierzeck
Clear cp0 status while preserving implementation specific bits. Set bits BEV and ERL as the arch specification requires after a reset or soft-reset exception. Extend and fix initialization of watch registers. Check if additional watch register sets are implemented and initialize them too. Initialize cp0 count as early as possible to get the most accurate boot timing. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-11-30MIPS: fix ROM exception vectorsDaniel Schwierzeck
When booting from ROM, early exceptions can't be handled properly. Instead of busy-looping give the developer the possibilty to examine the situation. Invoke an UHI exception operation which can be read as unhandled exception by a hardware debugger if one is attached. If the debugger doesn't support UHI, the exception is read as unexpected breakpoint. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-11-30MIPS: make inclusion of ROM exception vectors configurableDaniel Schwierzeck
This adds a compile time option to include code for static exception vectors. Static exception vectors are only needed, when the U-Boot entry point is equal to the CPU reset exception vector address. For instance this is the case when U-Boot is used as ROM in Qemu or booted from parallel NOR flash. When U-Boot is booted from RAM (e.g. loaded there by SPL), the exception vectors need to be setup dynamically, which is done in follow-up commits. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-11-30Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini
2016-11-30imx6: clock: Enable External Memory Interface [EIM] clock (eim_slow_clock)Lukasz Majewski
This patch extends the imx6 clock code to enable or disable the EIM slow clock, which in necessary when one wants to use EIM interface t o read/write from external memory (e.g. NOR). Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
2016-11-30mx6sx: Add initial support for Samtec VIN|ING 2000 boardChristoph Fritz
This patch adds initial support for Samtec VIN|ING 2000 board. Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Acked-by: Marek Vasut <marex@denx.de>
2016-11-30Merge git://git.denx.de/u-boot-mpc85xxTom Rini
2016-11-29travis.yml: Add samsung and rockchip buildsTom Rini
The catch-all job is failing due to time limits depending on factors out of our control, so move Samsung and Rockchip boards into their own jobs and then exclude them from the general ARM and AArch64 jobs. Signed-off-by: Tom Rini <trini@konsulko.com>
2016-11-29imx7: SPI: add suport for SPI flash in mikroBUS slotAngus Ainslie
Enable the escpi3 nets attached to the mikroBUS slot on the i.MX7 Sabre evalution board. Also enble the SPI flash commands to work with the "flash click" board. This is V2 of this patch with changes recommended by the maintainer CC: Jagan Teki <jteki@openedev.com>
2016-11-29arm: mx6: specify SPL paddingStefan Agner
Specify standard padding for payload to 68KB. This is derived from the maximum header size plus maximum SPL size. It matches the already defined offset for SD/eMMC devices (69KB) too. This allows to use the u-boot-with-spl.imx build target to generate a directly flashable image which can be flashed using: dd if=u-boot-with-spl.imx of=/dev/mmcblk0 bs=512 skip=2 While the patch has been created with SD/eMMC in mind, this also works with other boot media. The board file needs to configure the media specific (absolute) payload offset accordingly. Especially the IVT offset is boot media specific and can be retrieved from the reference manual (Table 8-25. Image Vector Table Offset and Initial Load Region Size). For NAND boot a define like this should do the job: #define CONFIG_SYS_NAND_U_BOOT_OFFS (SPL_PAD_TO + 0x400) Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2016-11-29mx6sx: Add initial support for UDOO Neo BoardBreno Lima
UDOO Neo Board is a development board from Seco that has three models: - UDOO Neo Basic - UDOO Neo Basic Kick Starter - UDOO Neo Extended - UDOO Neo Full All versions are based on the i.MX6 SoloX processor. For more details about the UDOO Neo board, please refer to: http://www.udoo.org/udoo-neo/ This work is based on a previous commit of Francesco Montefoschi <francesco.monte@gmail.com>: https://github.com/fmntf/u-boot/commit/877b71184a5105e708024f232d36aed574961844 Only tested on the UDOO Neo Full board. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-11-29colibri_vf: Read kernel and device tree from static UBI volumesSanchayan Maity
Our update scripts write the kernel and device tree in seperate UBI volumes. This allows to use a lot less UBI/UBIFS support in U-Boot, which should lower the risk of hitting bugs in this area. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
2016-11-29ARM: ts4600: add basic board supportSebastien Bourdelin
This commit adds basic support including: MMC, Serial console Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-11-29board: ge: bx50v3: add the PMIC configuration supportKen Lin
Change the PMIC bulk configuration from auto mode to sync mode to avoid voltage dropout issue seen in auto mode. Signed-off-by: Ken Lin <ken.lin@advantech.com.tw> Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
2016-11-29ARM: mx6: ddr: use Kconfig for inclusion of DDR calibration routinesEric Nelson
The DDR calibration routines are gated by conditionals for the i.MX6DQ SOCs, but with the use of the sysinfo parameter, these are usable on at least i.MX6SDL and i.MX6SL variants with DDR3. Also, since only the Novena board currently uses the dynamic DDR calibration routines, these routines waste space on other boards using SPL. Add a KConfig entry to allow boards to selectively include the DDR calibration routines. Signed-off-by: Eric Nelson <eric@nelint.com>
2016-11-29mx6: ddr: add routine to return DDR calibration dataEric Nelson
Add routine mmdc_read_calibration() to return the output of DDR calibration. This can be used for debugging or to aid in construction of static memory configuration. This routine will be used in a subsequent patch set adding a virtual "mx6memcal" board, but could also be useful when gathering statistics during an initial production run. Signed-off-by: Eric Nelson <eric@nelint.com>
2016-11-29mx6: ddr: pass mx6_ddr_sysinfo to calibration routinesEric Nelson
The DDR calibration routines have scattered support for bus widths other than 64-bits: -- The mmdc_do_write_level_calibration() routine assumes the presence of PHY1, and -- The mmdc_do_dqs_calibration() routine tries to determine whether one or two DDR PHYs are active by reading MDCTL. Since a caller of these routines must have a valid struct mx6_ddr_sysinfo for use in calling mx6_dram_cfg(), and the bus width is available in the "dsize" field, use this structure to inform the calibration routines which PHYs are active. This allows the use of the DDR calibration routines on CPU variants like i.MX6SL that only have a single MMDC port. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Marek Vasut <marex@denx.de>
2016-11-29mx6: ddr: allow 32 cycles for DQS gating calibrationEric Nelson
The DDR calibration code is only setting flag DG_CMP_CYC (DQS gating sample cycle) for the first PHY. Set the 32-cycle flag for both PHYs and clear when done so the MPDGCTRL0 output value isn't polluted with calibration artifacts. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Marek Vasut <marex@denx.de>
2016-11-29imx: mx6: ddr: add register MPZQLP2CTL for LPDDR2Eric Nelson
Add constants for the MPZQLP2CTL DDR register for both banks to allow setting the LPDDR2 timing values in .cfg files using a named constant instead of hex addresses as is currently done in mx6slevk and other board files. Signed-off-by: Eric Nelson <eric@nelint.com>
2016-11-29tools: imximage: display DCD block offset, lengthEric Nelson
These values can be used to sign a U-Boot image for use when loading an image through the Serial Download Protocol (SDP). Note that the address of 0x910000 is usable with the stock configuration of imx_usb_loader on i.MX6 and i.MX7 SOCs: https://github.com/boundarydevices/imx_usb_loader/blob/master/mx6_usb_work.conf#L3 Refer to the section on imx_usb_loader in this post for more details: https://boundarydevices.com/high-assurance-boot-hab-dummies/ Signed-off-by: Eric Nelson <eric@nelint.com>
2016-11-29arm: imx: wandboard: fix compile error if CONFIG_VIDEO is deactivatedSven Ebenfeld
When I tried to deactivate VIDEO support for the Wandboard, it still tried to initialize the Framebuffer and so on. That is the reason for the added ifdefs. CONFIG_VIDEO is enabled in the configuration as default and therefore nothing changes for the default user. The structs mx6dl_i2c2_pad_info and mx6q_i2c2_pad_info are only available when CONFIG_IPUV3 are set and should not be tried to access, when that define is not defined. Signed-off-by: Sven Ebenfeld <sven.ebenfeld@gmail.com>
2016-11-29pwm: imx: increase support up to PWM8 for i.MX6SXChristoph Fritz
This patch increases supported PWMs from previously PWM4 now up to PWM8 if i.MX6SX is in use. Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
2016-11-29tbs2910: Make Ethernet functional againSoeren Moch
Configure the PHY to output a 125MHz clk from CLK_25M and set tx clock delay. This patch is similar to commit 4b6035da482cccda06aeb419634f99937c9fc783 ("mx6sabresd: Make Ethernet functional again"). Signed-off-by: Soeren Moch <smoch@web.de>
2016-11-29imx: make ipu's di configurableMax Krummenacher
The ipu has two display interfaces. Make the used one a parameter in struct display_info_t instead of using unconditionally DI0. DI0 is the default setting. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Reviewed-by: Eric Nelson <eric@nelint.com>
2016-11-29spl: mmc: fix switch statementMax Krummenacher
If CONFIG_SPL_LIBCOMMON_SUPPORT is not defined there is a lone case statement at the end of the switch leading to a compile error. Remove the offending case statement. | common/spl/spl_mmc.c:339:7: error: label at end of compound statement Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Vasut <marex@denx.de>
2016-11-29ARM: mx6: add MMC2 boot device detection support in SPLMarcin Niestroj
Check BOOT_CFG2[3:4] to determine which SD/MMC port is selected to boot from. If MMC2 is selected return BOOT_DEVICE_MMC2. In all other cases return BOOT_DEVICE_MMC1, as we do not have corresponding macro for MMC3 and MMC4. Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
2016-11-29Merge branch 'master' of git://git.denx.de/u-bootStefano Babic
Signed-off-by: Stefano Babic <sbabic@denx.de>
2016-11-29armv7: psci: cpu_off: flush D-Cache before disable D-CachePeng Fan
Before disable cache, need to first flush cache. There maybe dirty data in D-Cache before disable D-Cache. After disable D-Cache, the first store instructions in psci_v7_flush_dcache_all will directly store registers {r4-r5, r7, r9-r11, lr} to memory. If there is dirty data before disable D-Cache, psci_v7_flush_dcache_all will flush data to memory, and may overwrite the memory that hold the registers {r4-r5, r7, r9-r11, lr}. So before disable cache, first flush D-Cache. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Hongbo Zhang <hongbo.zhang@nxp.com> Cc: York Sun <york.sun@nxp.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Tom Rini <trini@konsulko.com>
2016-11-29vexpress64: Juno: Change PCI buss addresses for IO to start from zero.Liviu Dudau
Juno uses a 1:1 mapping between CPU and PCI addresses for IO. First, that will trip devices that cannot use more than 16 bits of addresses for IO, second it is un-necessary as the system can handle zero-based PCI addresses just fine. Change the mapping to start IO bus addresses from zero. Signed-off-by: Liviu Dudau <Liviu.Dudau@foss.arm.com>
2016-11-29bcm2835: Reserve the spin table in efi memory mapAlexander Graf
Firmware provides a spin table on the raspberry pi. This table shouldn't get overwritten by payloads, so we need to mark it as reserved. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2016-11-29bcm2835 video: Map frame buffer as 32bppAlexander Graf
To enable working efifb support, let's map the frame buffer as 32bpp instead of 16bpp. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2016-11-29ARM: bcm283x: Implement EFI RTS reset_systemAlexander Graf
The rpi has a pretty simple way of resetting the whole system. All it takes is to poke a few registers at a well defined location in MMIO space. This patch adds support for the EFI loader implementation to allow an OS to reset and power off the system when we're outside of boot time. Signed-off-by: Alexander Graf <agraf@suse.de>
2016-11-29drivers: net: keystone_net: add rgmii link type support when parsing dtMugunthan V N
Add support to detect RGMII link interface from link-interface device tree entry. Also rename the existing link type enums so that it provides meaningful interface like SGMII. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reported-by: Sekhar Nori <nsekhar@ti.com> Tested-by: Sekhar Nori <nsekhar@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-11-29ARM: bcm283x: use OF_CONTROL for bcm283xFabian Vogt
This patch removes use of U_BOOT_DEVICE in board/raspberrypi/rpi/rpi.c, enables OF_CONTROL in the config and adjusts the rpi_*defconfig configs. Signed-off-by: Fabian Vogt <fvogt@suse.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-11-29board: rpi: move uart deactivation to board_initFabian Vogt
When using OF_CONTROL, the disabled value of the mini UART platdata gets reset after board_early_init_f. So move detection and disabling to board_init and remove board_early_init_f. This uses the first device using the mini uart driver, as this method works reliably with different device trees or even no device tree at all. Signed-off-by: Fabian Vogt <fvogt@suse.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-11-29serial: bcm283x_mu: support disabling after initializationFabian Vogt
For the Raspberry Pi 3 it needs to be possible to disable the serial device after initialization happens, as only after the GPIO device is available it is known whether the mini uart is usable. Signed-off-by: Fabian Vogt <fvogt@suse.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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