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2016-03-21arm: ls102xa: fdt: Update FSL_QSPI_COMPAT and FSL_DSPI_COMPATAlison Wang
As the compatible property values for QSPI and DSPI dts nodes are changed in kernel, FSL_QSPI_COMPAT and FSL_DSPI_COMPAT need to be updated too. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21drivers/crypto/fsl: define structures for PDBAneesh Bansal
Structures are defined for PDB (Protocol Data Blcks) for various operations. These structure will be used to add PDB data while creating the PDB descriptors. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> CC: Ulises Cardenas <raul.casas@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21drivers/crypto/fsl: add constructs for protocol descriptorsAneesh Bansal
Construct APIs are added to create Protocol Descriptors for CAAM block. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> CC: Ulises Cardenas <raul.casas@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21drivers/crypto/fsl: correct error checking in run_descriptorAneesh Bansal
When CAAM runs a descriptor and an error occurs, a non-zero value is set in Output Status Register. The if condition should check the status for a non-zero value. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21armv8: ls2080ardb: invert irq pins polarity for AQR405 PHYShaohui Xie
To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins polarity by setting IRQCR register, because AQR405 interrupt is low active but GIC accepts high active. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21armv8: lsch3: Enable WUO config for RNI-20 nodePrabhakar Kushwaha
Enable wuo config to accelerate coherent ordered writes for LS2080A and LS2085A. WRIOP IP is connected to RNI-20 Node. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21arm64: Fix layerscape mmu setupAlexander Graf
With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-17cmd_dhry.c: Use lldiv for vax_mips calculation as wellTom Rini
Since dhry_per_sec is a u64 we must also use lldiv here when working with it. Otherwise: ../lib/dhry/cmd_dhry.c:(.text.do_dhry+0xd8): undefined reference to `__udivdi3' On some platforms. Signed-off-by: Tom Rini <trini@konsulko.com>
2016-03-17x86: Add congatec conga-QA3/E3845-4G (Bay Trail) supportStefan Roese
This patch adds support for the congatec conga-QA3/E3845-4G eMMC8 SoM, installed on the congatec Qseven 2.0 evaluation carrier board (conga-QEVAL). Its port is very similar to the MinnowboardMAX port and also uses the Intel FSP as described in doc/README.x86. Currently supported are the following interfaces / devices: - UART (via Winbond legacy SuperIO chip on carrier board) - Ethernet (PCIe Intel I210 / E1000) - SPI including SPI NOR as boot-device - USB 2.0 - SATA via U-Boot SCSI IF - eMMC - Video (HDMI output @ 800x600) - PCIe Not supported yet is: - I2C - USB 3.0 Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Add support for the samus chromebookSimon Glass
This adds basic support for chromebook_samus. This is the 2015 Pixel and is based on an Intel broadwell platform. Supported so far are: - Serial - SPI flash - SDRAM init (with MRC cache) - SATA - Video (on the internal LCD panel) - Keyboard Various less-visible drivers are provided to make the above work (e.g. PCH, power control and LPC). The platform requires various binary blobs which are documented in the README. The major missing feature is USB3 since the existing U-Boot support does not work correctly with Intel XHCI controllers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Support a chained-boot development flowSimon Glass
Sometimes it is useful to jump into U-Boot directly from coreboot or UEFI without any 16-bit init. This can help during development by allowing U-Boot to avoid doing all the init required by the platform. U-Boot expects its GDT to be set up correctly by its 16-bit code. If coreboot doesn't do this (because it hasn't run the payload setup code yet) then this won't happen. In this case we cannot rely on the GDT settings. U-Boot will hang or crash if these are wrong. Provide a development-only option to set up the GDT correctly. This is just a hack so you can jump to U-Boot from any stage of coreboot, not just at the end. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: dts: Drop memory SPD compatible stringSimon Glass
This is not needed now that the memory controller driver has the SPD data in its own node. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: ivybridge: Convert to use the common SDRAM codeSimon Glass
Adjust the existing implementation to use the new common SDRAM init code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Add common SDRAM-init codeSimon Glass
The code to call the memory reference code is common to several Intel CPUs. Add common code for performing this init. Intel calls this 'Pre-EFI-Init' (PEI), where EFI stands for Extensible Firmware Interface. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Move common PCH code into a common placeSimon Glass
The SATA indexed register write functions are common to several Intel PCHs. Move this into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17dhry: Correct dhrystone calculation for fast machinesSimon Glass
At present samus reports about 5600 DMIPS. With the default iteration count this is OK, but if 10 million runs are performed it overflows. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-03-17arm: Add a 64-bit division routine to the private librarySimon Glass
This is missing, with causes lldiv() to fail on boards with use the private libgcc. Add the missing routine. Code is available for using the CLZ instruction but it is not enabled at present. This comes from coreboot version 4.0. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-03-17x86: Fix a header nit in x86-chromebook.hSimon Glass
There is an extra line in the comment in the header. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Add a function to set the IOAPIC IDSimon Glass
Add a function to set the ID in the IOAPIC. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Update README for new developmentsSimon Glass
Update a few points which have become out-of-date. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Use white on black for the console on chromebooksSimon Glass
This is a little easier on the eyes, particularly when the backlight is set to maximum. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Add a default address for reference codeSimon Glass
Add an address which can be used for loading and running the reference code when needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: broadwell: Add video supportSimon Glass
Add a video driver for Intel's broadwell integrated graphics controller. This uses a binary blob for most init, with the driver just performing a few basic tasks. This driver supports VESA as the mode-setting mechanism. Since most boards don't support driver model yet with VESA, a special case is added to the Kconfig for broadwell. Eventually all boards will use driver model and this can be removed. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: broadwell: Add support for high-speed I/O lane with MESimon Glass
Provide a way to determine the HSIO (high-speed I/O) version supported by the Intel Management Engine (ME) implementation on the platform. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: broadwell: Add a GPIO driverSimon Glass
Add a GPIO driver for the GPIO peripheral found on broadwell devices. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: broadwell: Add support for SDRAM setupSimon Glass
Broadwell uses a binary blob called the memory reference code (MRC) to start up its SDRAM. This is similar to ivybridge so we can mostly use common code for running this blob. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: broadwell: Add power-control supportSimon Glass
Broadwell requires quite a bit of power-management setup. Add code to set this up correctly. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com> [squashed in http://patchwork.ozlabs.org/patch/598373/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: broadwell: Add reference code supportSimon Glass
Broadwell needs a special binary blob to set up the PCH. Add code to run this on start-up. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: broadwell: Add an LPC driverSimon Glass
Add a driver for the broadwell LPC (low-pin-count peripheral). This mostly uses common code. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: broadwell: Add a northbridge driverSimon Glass
Add a driver for the broadwell northbridge. This sets up the location of several blocks of registers. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: broadwell: Add a SATA driverSimon Glass
Add a SATA driver for broadwell. This supports connecting an SSD and the usual U-Boot commands to read and write data. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: broadwell: Add a pinctrl driverSimon Glass
GPIO pins need to be set up on start-up. Add a driver to provide this, configured from the device tree. The binding is slightly different from the existing ICH6 binding, since that is quite verbose. The new binding should be just as extensible. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: broadwell: Add a PCH driverSimon Glass
Add a driver for the broadwell low-power platform controller hub. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Add basic support for broadwellSimon Glass
This adds the broadwell architecture, with the CPU driver and some useful header files. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: dts: Update the pinctrl binding a littleSimon Glass
Make a few minor updates to make the meaning clearer. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Add support for running Intel reference codeSimon Glass
Intel has invented yet another binary blob which firmware is required to run. This is run after SDRAM is ready. It is linked to load at a particular address, typically 0, but is a relocatable ELF so can be moved if required. Add support for this in the build system. The file should be placed in the board directory, and called refcode.elf. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Drop all the old pin configuration codeSimon Glass
We don't need this anymore - we can use device tree and the new pinconfig driver instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: gpio: Allow the pinctrl driver to set up the pin configSimon Glass
Rather than setting up the pin configuration in the GPIO driver, use the new pinctrl driver to do it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Add an ICH6 pin configuration driverSimon Glass
Add a driver which sets up the pin configuration on x86 devices with an ICH6 (or later) Platform Controller Hub. The driver is not in the pinctrl uclass due to some oddities of the way x86 devices work: - The GPIO controller is not present in I/O space until it is set up - This is done by writing a register in the PCH - The PCH has a driver which itself uses PCI, another driver - The pinctrl uclass requires that a pinctrl device be available before any other device can be probed It would be possible to work around the limitations by: - Hard-coding the GPIO address rather than reading it from the PCH - Using special x86 PCI access to set the GPIO address in the PCH However it is not clear that this is better, since the pin configuration driver does not actually provide normal pin configuration services - it simply sets up all the pins statically when probed. While this remains the case, it seems better to use a syscon uclass instead. This can be probed whenever it is needed, without any limitations. Also add an 'invert' property to support inverting the input. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: link: Add pin configuration to the device treeSimon Glass
At present pin configuration on link does not use the standard mechanism, but some rather ugly custom code. As a first step to resolving this, add the pin configuration to the device tree. Four of the GPIOs must be available before relocation (for SDRAM pin strapping). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Update microcode for secondary CPUsSimon Glass
Each CPU needs to have its microcode loaded. Add support for this so that all CPUs will have the same version. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: ivybridge: Show microcode version for each coreSimon Glass
Enable the microcode feature so that the microcode version is shown with the 'cpu detail' command. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Record the CPU details when starting each coreSimon Glass
As each core starts up, record its microcode version and CPU ID so these can be presented with the 'cpu detail' command. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Move common MRC Kconfig options to the common fileSimon Glass
At present the MRC options are private to ivybridge. Other Intel CPUs also use these settings. Move them to a common place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Allow I/O functions to use pointersSimon Glass
It is common with memory-mapped I/O to use the address of a structure member to access memory, as in: struct some_regs { u32 ctrl; u32 data; } struct some_regs *regs = (struct some_regs *)BASE_ADDRESS; writel(1, &reg->ctrl); writel(2, &reg->data); This does not currently work with inl(), outl(), etc. Add a cast to permit this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Add macros to clear and set I/O bitsSimon Glass
The clrsetbits_...() macros are useful for working with memory mapped I/O. But they do not work with I/O space, as used on x86 machines. Add some macros to provide similar features for I/O. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: ivybridge: Drop sandybridge_early_init()Simon Glass
This function was removed in the previous clean-up. Drop it from the header file also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Move Intel Management Engine code to a common placeSimon Glass
Some of the Intel ME code is common to several Intel CPUs. Move it into a common location. Add a header file for report_platform.c also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [squashed in http://patchwork.ozlabs.org/patch/598372/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Rename PORT_RESET to IO_PORT_RESETSimon Glass
This same name is used in USB. Add a prefix to distinguish it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Move common CPU code to its own placeSimon Glass
Some of the Intel CPU code is common to several Intel CPUs. Move it into a common location along with required declarations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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