summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2016-07-02sunxi: Add defconfig and DTS file for Allwinner R16 EVB (Parrot)Quentin Schulz
The Parrot Board is an evaluation board with an Allwinner R16 (assumed to be close to an Allwinner A33), 4GB of eMMC, 512MB of RAM, USB host and OTG, a WiFi/Bluetooth combo chip, a micro SD Card reader, 2 controllable buttons, an LVDS port with separated backlight and capacitive touch panel ports, an audio/microphone jack, a camera CSI port, 2 sets of 22 GPIOs and an accelerometer. The DTS file is identical to the one submitted to the upstream kernel. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-07-02sunxi: Add missing boot_media fields in the SPL headerOlliver Schinagl
Commit b19236fd1 ("sunxi: Increase SPL header size to 64 bytes to avoid code corruption") Added defines for MMC0 and SPI as boot identification. After verifying on an OLinuXino Lime2 with NAND and eMMC, the expected values have been confirmed and added to spl.h Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-07-02sunxi: spl: Fix DRAM info printingHans de Goede
The switch to simple_printf was causing the SPL dram info to show as: DRAM: u MiB This fixes this by switching from %lu to %d for printing the DRAM size. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-07-01Prepare v2016.07-rc3Tom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-07-01Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini
2016-07-01mmc: increase MMC SDHCI read status timeoutSteve Rae
Otherwise, ocassionally see errors like this: Flashing sparse image at offset 2078720 Flashing Sparse Image sdhci_send_command: Timeout for status update! mmc fail to send stop cmd write_sparse_image: Write failed, block #2181088 [0] This does not affect the actual writing speed, which is controlled by the default value: CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT It only increases the retries when reading: SDHCI_INT_STATUS to avoid the timeout error. Signed-off-by: Steve Rae <steve.rae@raedomain.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
2016-07-01ti_omap5_common: Find right dtb file for DRA72-RevC EvmLokesh Vutla
DRA72-Evm revC uses dra72-evm-revc.dtb. Update the same in env vatiables. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-07-01autoboot: move bootdelay >= 0 check to abortboot()Masahiro Yamada
Move the bootdelay >= 0 check to the caller, which simplifies the callees. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2016-07-01autoboot: move CONFIG_SILENT_CONSOLE handlingMasahiro Yamada
Factor out the same code from the callees to the caller. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2016-07-01autoboot: rename abortboot_{keyed, normal} to __abortbootMasahiro Yamada
Because abortboot_keyed() and abortboot_normal() are not compiled at the same time, we can rename both of them to __abortboot(). This allows to drop #ifdef from the caller. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2016-07-01autoboot: remove CONFIG_ZERO_BOOTDELAY_CHECKMasahiro Yamada
As the help message of CONFIG_BOOTDELAY says, CONFIG_BOOTDELAY=-2 means the autoboot with no delay, with no abort check even if CONFIG_ZERO_BOOTDELAY_CHECK is defined. To sum up, the autoboot behaves as follows: [1] CONFIG_BOOTDELAY=0 && CONFIG_ZERO_BOOTDELAY_CHECK=y autoboot with no delay, but you can abort it by key input [2] CONFIG_BOOTDELAY=0 && CONFIG_ZERO_BOOTDELAY_CHECK=n autoboot with no delay, with no check for abort [3] CONFIG_BOOTDELAY=-1 disable autoboot [4] CONFIG_BOOTDELAY=-2 autoboot with no delay, with no check for abort As you notice, [2] and [4] come to the same result, which means we do not need CONFIG_ZERO_BOOTDELAY_CHECK. We can control all the cases only by CONFIG_BOOTDELAY, like this: [1] CONFIG_BOOTDELAY=0 autoboot with no delay, but you can abort it by key input [2] CONFIG_BOOTDELAY=-1 disable autoboot [3] CONFIG_BOOTDELAY=-2 autoboot with no delay, with no check for abort This commit converts the logic as follow: CONFIG_BOOTDELAY=0 && CONFIG_ZERO_BOOTDELAY_CHECK=n --> CONFIG_BOOTDELAY=-2 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Heiko Schocher <hs@denx.de> Acked-by: Christian Riesch <christian.riesch@omicronenergy.com> Acked-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
2016-07-01doc: bootdelay: drop explanation about CONFIG_BOOTDELAY from READMEMasahiro Yamada
The same information now exists in common/Kconfig. Do not duplicate documentation from the point of view of maintainability. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2016-07-01ARM: socfpga: move CONFIG_BOOTDELAY to Kconfig for IS1 boardMasahiro Yamada
This recently added board missed the tree-wide migration of CONFIG_BOOTDELAY. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
2016-07-01ARM: AM437x: Align HS device variant defconfig filenameAndreas Dannenberg
Align the name of the defconfig file for high-security (HS) device variants from the AM43xx family of SoCs with the corresponding name used for the general purpose devices. This allows for easier cross-association of those files and also provides room to grow from an HS device part number perspective. Furthermore, update and cleanup associated MAINTAINERS file. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Madan Srinivas <madans@ti.com>
2016-07-01driver: qspi: correct QSPI disable CS reset valuePraneeth Bajjuri
Correcting QSPI disable/unselect CS reset value. CTRL_CORE_CONTROL_IO_2: QSPI_MEMMAPPED_CS[10:8] This is not causing any issue, but its better to untouch the reserved bits. Praneeth Bajjuri <praneeth@ti.com> Signed-off-by: Ravi Babu <ravibabu@ti.com>
2016-07-01ARM: uniphier: add external IRQ setup codeMasahiro Yamada
I will carry this work-around until it is cared in the kernel. This looks up the AIDET node and sets up a register to handle active low interrupt signals. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-07-01ARM: dts: uniphier: add AIDET nodesMasahiro Yamada
The AIDET (ARM Interrupt Detector Add-on Circuit) is a kind of syscon block related with the interrupt controller. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-07-01pinctrl: uniphier: add Ethernet pin-mux settingsMasahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-07-01pinctrl: uniphier: avoid building unneeded pin-mux tables for SPLMasahiro Yamada
SPL does not use all of the devices, so we can save some memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-07-01pinctrl: uniphier: support pin configuration for dedicated pinsMasahiro Yamada
PH1-LD4 and PH1-sLD8 SoCs have pins that support pin configuration (pin biasing, drive strength control), but not pin-muxing. Allow to fill the mux value table with -1 for those pins; pins with mux value -1 will be skipped in the pin-mux set function. The mux value type should be changed from "unsigned" to "int" in order to accommodate -1 as a special case. [ Linux commit: 363c90e743b50a432a91a211dd8b078d9df446e9 ] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-07-01pinctrl: uniphier: split pinctrl driver for PH1-LD11 and PH1-LD20Masahiro Yamada
PH1-LD11 and PH1-LD20 have much pin controlling in common, so I added a single driver shared between them in the initial commit. However, the Ethernet pin-mux settings I am going to add are different with each other, and they may diverge more as the progress of development. Split it into two dedicated drivers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-07-01pinctrl: uniphier: allow to have pinctrl node under syscon nodeMasahiro Yamada
Currently, the UniPhier pinctrl driver itself is a syscon, but it turned out much more reasonable to make it a child node of a syscon because our syscon node consists of a bunch of system configuration registers, not only pinctrl, but also phy, and misc registers. It is difficult to split the node. This commit allows to migrate to the new DT structure. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-07-01ARM: dts: uniphier: sync Device Trees with upstream LinuxMasahiro Yamada
I periodically sync Device Trees for better maintainability. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-06-30pinctrl: uniphier: remove unneeded pin group nand_cs1Masahiro Yamada
This SoC does not support NAND CS1. This place-holder is no longer necessary. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-06-30pinctrl: uniphier: fix NAND pin-mux setting for PH1-LD11/LD20Masahiro Yamada
My mistake in the initial support patch. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-06-30pinctrl: uniphier: remove wrong pin-mux functions for ProXstream2Masahiro Yamada
These are pin group names, not function names. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-06-30ARM: uniphier: fix typo "talbe"Masahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-06-29x86: coreboot: Remove the dummy pch driverBin Meng
There is a dummy pch driver in the coreboot directory. This causes drivers of its children fail to function due to empty ops. Remove the whole file since it is no longer needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-06-28Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
2016-06-28configs: Re-sync after boot menu changesTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-06-28armv8: dts: fsl: Remove cpu nodes from Layerscape DTSIsAbhimanyu Saini
Currently layescape SoCs are not using cpu nodes. So removing them in favour of compatibly with similar SoCs that have different cores like LS2080A and LS2088A. This has been tested on LS2080AQDS, LS1043ARDB, LS1012ARDB. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-28armv8: fsl-layerscape: Append "A" in SoC name for ARM based SoCsPrabhakar Kushwaha
Freescale ARMv8 SoC name ends with "A" to represent ARM SoCs. like LS2080A, LS1043A, LS1012A. So append "A" to SoC names. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-28mmc: fsl: introduce wp_enablePeng Fan
Introudce wp_enable. To check WPSPL, wp_enable needs to be set to 1 in board code. Take i.MX6UL for example, for some boards, they do not use WP singal, so they does not configure USDHC1_WP_SELECT_INPUT, and its default value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and SION bit set. So USDHC controller can always get wp signal and WPSPL shows write protect and blocks driver continuing. This is not what we want to see, so add wp_enable, and if set to 0, just omit the WPSPL checking and this does not effect normal working of usdhc controller. If wp-gpios is provided in dts, wp_enable is set to 1, otherwise 0. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: York Sun <york.sun@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-28fsl_esdhc: Update clock enable bits for USDHCYe Li
The USDHC moves the 4 clock bits CARD_CLK_SOFT_EN, IPG_PERCLK_SOFT_EN, HCLK_SOFT_EN, and IPG_CLK_SOFT_EN from sysctl register to vendorspec register. The driver uses RSTA to replace the clock gate off operation. But this is not a good solution because: 1. when using RSTA, we should wait this bit to clear by itself. This is not implemeneted in the code. 2. After RSTA is set, it is recommended that the Host Driver reset the external card and reinitialize it. So in this patch, we change to use the vendorspec registers for these bits operation. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: York Sun <york.sun@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-28mmc: fsl: reset to normal boot mode when eMMC fast bootPeng Fan
When booting in eMMC fast boot, MMC host does not exit from boot mode after bootrom loading image. So the first command 'CMD0' sent in uboot will pull down the CMD line to low and cause errors. This patch cleans the MMC boot register in "mmc_init" to put the MMC host back to normal mode. Also clear DLL_CTRL delay line settings at USDHC initialization to eliminate the pre-settings from boot rom. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: York Sun <york.sun@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-28armv8: ls1043aqds: print FPGA info early for QSPI bootQianyu Gong
Now I2C is initialized early enough to access FPGA so it supports to show board info as early as other boot methods. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-28armv8: ls1043aqds: use configurable clockQianyu Gong
Get the clocks from FPGA through I2C, if IFC is disabled. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-28common: add new boot media kconfig entryPeng Fan
Add CONFIG_{SD|NAND|ONENAND|SPI|QSPI|SATA}_BOOT kconfig entries. SoCs supports loading U-Boot from different medias to DRAM, such as i.MX6/7 supports loading U-Boot to DRAM from sd/emmc/nand/qspi/spi/sata and etc. For i.MX, imximage will generate different IVT headers according to boot medias. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Heiko Schocher <hs@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Christophe Ricard <christophe-h.ricard@st.com> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Francois Retief <fgretief@spaceteq.co.za> Cc: Tom Rini <trini@konsulko.com>
2016-06-28Kconfig: make NOR_BOOT a common optionPeng Fan
Not only am335x supports booting from NOR, i.MX6 SoCs also supports booting from NOR. Make NOR_BOOT a common option to let different SoCs share it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Heiko Schocher <hs@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Christophe Ricard <christophe-h.ricard@st.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Francois Retief <fgretief@spaceteq.co.za> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-06-28maintainers: new email addressSteve Rae
Update the email address for the boards that I maintain. Signed-off-by: Steve Rae <steve.rae@raedomain.com>
2016-06-27fastboot: sparse: improve CHUNK_TYPE_FILL write performanceSteve Rae
- increase the size of the fill buffer - testing has shown a 10x improvement when the sparse image has large CHUNK_TYPE_FILL chunks Signed-off-by: Steve Rae <srae@broadcom.com>
2016-06-27fastboot: sparse: implement reserve()Steve Rae
In order to process the CHUNK_TYPE_DONT_CARE properly, there is a requirement to be able to 'reserve' a specified number of blocks in the storage media. Because of the special handling of "bad blocks" in NAND devices, this is implemented in a storage abstraction function. Signed-off-by: Steve Rae <srae@broadcom.com> Reviewed-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-06-27fastboot: sparse: resync common/image-sparse.c (part 2)Steve Rae
- update fastboot_okay() and fastboot_fail() This file originally came from upstream code. While retaining the storage abstraction feature, this is the second set of the changes required to resync with the cmd_flash_mmc_sparse_img() in the file aboot.c from https://us.codeaurora.org/cgit/quic/la/kernel/lk/plain/app/aboot/aboot.c?h=LE.BR.1.2.1 Signed-off-by: Steve Rae <srae@broadcom.com>
2016-06-27fastboot: sparse: resync common/image-sparse.c (part 1)Steve Rae
This file originally came from upstream code. While retaining the storage abstraction feature, this is the first set of the changes required to resync with the cmd_flash_mmc_sparse_img() in the file aboot.c from https://us.codeaurora.org/cgit/quic/la/kernel/lk/plain/app/aboot/aboot.c?h=LE.BR.1.2.1 Signed-off-by: Steve Rae <srae@broadcom.com>
2016-06-27fastboot: sparse: remove session-id logicSteve Rae
This "session-id" alogrithm is not required, and currently corrupts the stored image whenever more the one "session" is required. Signed-off-by: Steve Rae <srae@broadcom.com>
2016-06-27Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini
2016-06-27mmc: dw_mmc: fix the wrong AND operationJaehoon Chung
These condition checking are wrong. Original Author's intention might be "&" instead of "&&". It can know whether receive or transmit data request with BIT[4]/BIT[5] of RINTSTS register. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2016-06-26arm: at91: taurus/axm: add DM and DTS supportHeiko Schocher
add DM and DTS support for the at91 based siemens boards. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> [rebased on current ToT] Signed-off-by: Andreas Bießmann <andreas@biessmann.org>
2016-06-26arm: at91: smartweb: add DM and DTS supportHeiko Schocher
Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> [rebased on current ToT] Signed-off-by: Andreas Bießmann <andreas@biessmann.org>
2016-06-26arm: at91: dts: Bring in dts files for AT91SAM9G20 and SAM9260Heiko Schocher
Add this files from Linux v4.6-rc5 66b8a424d: [workqueue: fix ghost PENDING flag while doing MQ IO] Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Andreas Bießmann <andreas@biessmann.org>
generated by cgit v0.10.2 at 2024-11-09 14:15:54 (GMT)