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2018-10-09Force default env in rescue flash configuration for Grapeboardscalys-lsdk-1803Joris van Vossen
2018-09-26MT25QU512A flash driver flags update for GrapeboardJoris van Vossen
2018-08-28MT25QU512 Flash support for GrapeboardJoris van Vossen
2018-05-17ubifs update and yocto build supportJoris van Vossen
2018-05-17Initial secure boot support for grapeboardJoris van Vossen
2018-05-17Grapeboard rescue flash compatibility updateJoris van Vossen
2018-04-24Grapeboard Eth PHY LED configuration updatedJoris van Vossen
2018-04-18UBIFS and distroboot support and rescue target build merged with default targetJoris van Vossen
2018-04-09LSDK-18.03 Grapeboard initial supportJoris van Vossen
2018-03-10driver: net: fsl-mc: remove usage of CONFIG_FSL_MC_ENETYogesh Gaur
remove usage of CONFIG_FSL_MC_ENET config option for file drivers/net/fsl-mc/mc.c. As per driver/net/Makefile drivers/net/Makefile:72:obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/ Thus, file mc.c would going to compile only when CONFIG_FSL_MC_ENET is enabled. Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
2018-03-09powerpc: configs: Set initrd_high environment variblePrabhakar Kushwaha
In commit 20e072f, it force to check "bootm_low" and "bootm_size" if "initrd_high" is missing. It will cause Linux can't boot up with ramdisk size > 100MB on PPC. On PPC the initrd does not need to be loaded within the boot mapping. This assumption of what the absence of initrd_high means in commit 20e072f is not universally appropriate. As the discussion is continuing in the community, this patch is just a workaround to fix the issue. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2018-03-09armv8: ls1043ardb_sdcard: delete CONFIG_SPL_FSL_LS_PPAZhang Ying-22455
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
2018-03-07mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabledYangbo Lu
u-boot is trying to make CONFIG_BLK as a hard requirement for DM_MMC. But now it's still not. config BLK bool "Support block devices" depends on DM default y if DM_MMC When fsl_esdhc driver was reworked for DM_MMC support, DM_MMC without CONFIG_BLK enabled wasn't considered. This patch is to fix probe issue without CONFIG_BLK enabled. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2018-02-13armv8: sec_firmware: Remove JR3 from device tree node in all casesRuchika Gupta
JR3 was getting removed from device tree only if random number generation was successful. However, if SEC firmware is present,JR3 should be removed from device tree node irrespective of the random seed generation as SEC firmware reserves it for it's use. Not removing it in case of random number generation failure causes the kernel to crash. Random number generation was being called twice. This is not required. If SEC firmware is running, SIP call can be made to the SEC firmware to get the random number. This call itself would return failure if function is not supported. Duplicate calling of random number generation function has been removed Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
2018-02-12ls1088a: qspi: Enable XIP mode above 16 MB addressesRajat Srivastava
Currently in LS1088A, XIP mode in QSPI works up to 16 MB addresses. This patch enables QSPI support in XIP mode for addresses above 16 MB as well. Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
2018-02-08PowerPC: phy: enable all phylib drivers when use phylib and tsec enetZhao Qiang
<config_phylib_all_drivers.h> should be included when CONFIG_PHYLIB and CONFIG_TSEC_ENET are defined. Fixes: 3146f0c017 ("Move PHYLIB to Kconfig") Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
2018-02-08ls2081a: qspi: Enable config to write aligned data to TxFIFORajat Srivastava
Enable config in LS2081A boards to send only 16 bytes aligned data to TxFIFO while writing to flash. Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
2018-02-08ls2088a: qspi: Enable config to write aligned data to TxFIFORajat Srivastava
Enable config in LS2088A boards to send only 16 bytes aligned data to TxFIFO while writing to flash. Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
2018-02-08ls2080a: qspi: Enable config to write aligned data to TxFIFORajat Srivastava
Enable config in LS2080A boards to send only 16 bytes aligned data to TxFIFO while writing to flash. Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
2018-02-08ls1088a: qspi: Enable config to write aligned data to TxFIFORajat Srivastava
Enable config in LS1088A boards to send only 16 bytes aligned data to TxFIFO while writing to flash. Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
2018-02-08Kconfig: qspi: Add SPI_ALIGNED_TXFIFO config detailsRajat Srivastava
This config makes driver send only 16 bytes aligned data to TxFIFO while writing on flash. Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
2018-02-08qspi: Add code to send only aligned data to TxFIFORajat Srivastava
Some Freescale QSPI controllers require driver to send only 16 bytes aligned data to TxFIFO while performing flash write operation. The extra data is not actually written on flash. The patch enables driver to send 16 bytes aligned data to TxFIFO, provided the config is enabled. The reason behind this behaviour of controller is still not clear and discussion with hardware team is ongoing. The patch will be updated before sending it to upstream. Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
2018-02-08ls1088a: Moving CONFIG_FSL_QSPI to defconfigRajat Srivastava
Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
2018-02-08EHCI: Fix endian access issue on EHCI intinalizationyinbo.zhu
This issue is exposed after commit 9000eddbase0d ("drivers/usb/ehci: Use platform-specific accessors"), the wrong endian way of EHCI controller programing will cause USB function down. Configs Affected: P2041-40-R2.0, P3041-R2.0, P4080-40-R3.0, P5040-21-R2.1, T1024-R1.0, T1040-42-20-22-R1.1, T2080-R1.1, T4240-4160-R2.0 Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
2018-02-06ARMv8: ls1046a: Enable PCIe and E1000 in lpuart defconfigHou Zhiqiang
Enable PCIe and E1000 in ls1046aqds lpuart defconfig. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2018-01-29armv8: ls1088: Add CONFIG_SPI_FLASH_SPANSION to sdcard defconfigsAshish Kumar
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
2018-01-29armv8: ls1088a: Move CONFIG_BOOTARGS and CONFIG_CMD_GREPENV to defconfigAshish Kumar
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
2018-01-29armv8: ls1088: Add qixis offsets for lbmap and rcw_srcAshish Kumar
This patch add value for rcw_src and lbmap if the seconday boot targets are ifc and emmc. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
2018-01-29fsl: common :qixis: Add ifc and emmc switch support in qixisAshish Kumar
Previously only SD, NAND etc were secondary boot source and had IFC-NOR as primary booting target. But for SoC like LS1088 IFC-NOR can be secondary boot source, while QSPI-NOR is primary booting target, So add options in qixis to switch to other targets using new commands. E.g. '=> qixis_reset ifc' : switch to ifc '=> qixis_reset emmc' : switch to emmc Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
2018-01-19board:ls1012a2g5rdb: define PFE firmware address in kconfigBhaskar Upadhaya
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
2018-01-19board: ls1012a: update mdio, phy parameters based on serdes protocolBhaskar Upadhaya
mdio bus and phy-id needs to be configured based on serdes protocol 3508, 2208 selected via RCW. Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
2018-01-19board: ls1012a2g5rdb: avoid phy resetBhaskar Upadhaya
ls1012a2g5rdb does not have requirement of phy reset, so placing reset_phy code for ls1012ardb only. Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
2018-01-18dm: pci: change bus number register setting compliant with LinuxMinghuan Lian
This patch is to change U-Boot PCI bus assignement compliant with Linux. It means each PCIe controller's bus number is 0, not the current maximum PCI bus number, when start to scan this controller. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-01-18armv8: ls1088ardb: secure boot: Use tiny printf to save spl sizePankit Garg
Using tiny printf remove format specifier debug capabilities for secure boot defconfig Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
2018-01-18armv8: ls1088a: vid: Add some function in SPL for VIDPankit Garg
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
2018-01-18ls1088a: Add VID support for QDS and RDB platformsRajesh Bhagat
This patch adds the support for VID on LS1088AQDS and LS1088ARDB systems. It reads the fusesr register and changes the VDD accordingly by adjusting the voltage via LTC3882 regulator. This patch also takes care of the special case of 0.9V VDD is present in fusesr register. In that case,it also changes the SERDES voltage by disabling the SERDES, changing the SVDD and then re-enabling SERDES. Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
2018-01-18common: board_f: vid: Add VID specific API to adjust core voltageRajesh Bhagat
Adds a VID specific API in init_sequence_f and spl code flow namely init_func_vid which is required to adjust core voltage. VID specific code is required in spl, hence moving flag CONFIG_VID out of spl flags. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
2018-01-18ls1088a: ddr: configure DDR for 0.9v for VID supportRajesh Bhagat
When VID feature is supported, check the contents of fuse register and configure DDR operate at 0.9v. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
2018-01-18ddr: fsl: set cdr1 first in case 0.9v VDD is enabled for some SoCsRajesh Bhagat
Sets DDR configuration parameter cdr1 before all other settings to support case 0.9v VDD is enabled for some SoCs Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
2018-01-18board: common: vid: Add support for LTC3882 voltage regulator chipRajesh Bhagat
Restructures common driver to support LTC3882 voltage regulator chip. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
2018-01-18Kconfig: Add LTC3882 voltage regulator configRajesh Bhagat
Adds below LTC3882 voltage regulator config: CONFIG_VOL_MONITOR_LTC3882_READ CONFIG_VOL_MONITOR_LTC3882_SET Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
2018-01-18board: common: vid: Move IR chip specific code in flagRajesh Bhagat
Moves IR chip (IR36021) specific code in flag to resolve compilation issue where it is not present. For example, LS1088A is having a new LTC3882 voltage chip. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
2018-01-18board: common: vid: Add board specific vdd adjust APIRajesh Bhagat
Adds a board specific API namely board_adjust_vdd which is required to define the board VDD adjust settings. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
2018-01-18board: common:vid: Add LS1088A VID Supported voltage valuesRajesh Bhagat
Adds below voltage values supported by LS1088A Soc: 1.025 V(default), 0.9875V, 0.9750 V, 0.9V, 1.0 V, 1.0125 V, 1.0250 V Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
2018-01-18armv8: lsch3: Add serdes and DDR voltage setupRajesh Bhagat
Adds SERDES voltage and reset SERDES lanes API and makes enable/disable DDR controller support 0.9V API common. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
2018-01-17configs: ls1012a: add pfe configuration for LS1012ACalvin Johnson
Add configurations for PFE. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Changes in v2: -Moved SYS_LS_PFE_FW_ADDR from pfe Kconfig to board Kconfigs -Add "pfe stop" to ls1012a rdb, frdm and 2g5rdb config files
2018-01-17armv8: layerscape: csu: enable ns access to PFE registersCalvin Johnson
Enable all types of non-secure access to PFE block registers. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Changes in v2: -Improved commit message to provide more description
2018-01-17armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECCCalvin Johnson
1. Set AWCACHE0 attribute of PFE DDR and HDBUS master interfaces to bufferable. 2. Set RD/WR QoS for PFE DDR and HDBUS AXI master interfaces. 3. Disable ECC detection for PFE. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Changes in v2: -Improved commit message to provide more description -Replaced magic numbers with proper definitions
2018-01-17armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structureCalvin Johnson
SoC specific PFE macros are defined and structure ccsr_scfg is updated with members defined for PFE. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Changes in v2: None
2018-01-17armv8: fsl-lsch2: initialize pfe gemacCalvin Johnson
Call gemac_initialize to initialize both gemacs of pfe. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Changes in v2: None
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