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path: root/arch/arm/cpu/armv7/ls102xa/fdt.c
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2017-05-01fdt: Move fdt_fixup_ethernet to a common placeTom Rini
With 3f66149d9fb4 we no longer have a common call fdt_fixup_ethernet. This was fine to do on PowerPC as they largely had calls already in ft_cpu_fixup. On ARM however we largely relied on this call. Rather than introduce a large number of changes to ft_cpu_fixup / ft_board_fixup we recognize that this is a common enough call that we should be doing it in a central location. Do it early enough that we can do any further updates in ft_cpu_fixup / ft_board_fixup. Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Thomas Chou <thomas@wytron.com.tw> (maintainer:NIOS) Cc: York Sun <york.sun@nxp.com> (maintainer:POWERPC MPC85XX) Cc: Stefan Roese <sr@denx.de> (maintainer:POWERPC PPC4XX) Cc: Simon Glass <sjg@chromium.org> Cc: Joakim Tjernlund <Joakim.Tjernlund@infinera.com> Fixes: 3f66149d9fb4 ("Remove extra fdt_fixup_ethernet() call") Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-28arm: ls102xa: Rewrite the logic of ft_fixup_enet_phy_connect_type()Bin Meng
eth_get_dev_by_index() is an API which is not available in driver model. Use eth_get_dev_by_name() instead, which can also simplifly the code logic a little bit. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-10-29ls102xa: fdt: Disable IFC in SD boot for QSPIAlison Wang
As QSPI/DSPI and IFC are pin multiplexed, IFC is disabled in SD boot for QSPI. This patch will add fdt support for this rule. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20arm: ls1021a: Remove the inappropriate use of the function 'sprintf'Alison Wang
As the function 'sprintf' does not check buffer boundaries but outputs to the buffer 'enet' of fixed size (16), this patch removes the function 'sprintf', and uses 'strcpy' instead. It will assign the character arrays 'enet' and 'phy' the corresponding character strings. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-24fsl/ls1021qds: Add deep sleep supporttang yuantian
Add deep sleep support on Freescale LS1021QDS platform. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> [York Sun: Fix conflict in fdt.c] Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-24ls102xa: fdt: Disable QSPI and DSPI in NOR/NAND/SD bootAlison Wang
As QSPI/DSPI and IFC are pin multiplexed, QSPI and DSPI are only enabled in QSPI boot, and disabled in other boot modes. IFC is enabled in NOR/NAND/SD boot, and disabled in QSPI boot. This patch will add fdt support for the above rules. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-24crypto/fsl: Add fixup for crypto nodeRuchika Gupta
Era property is added in the crypto node in device tree. Move the code to do so from arch/powerpc/mpc8xxx/fdt.c to drivers/sec/sec.c so that it can be used across arm and powerpc platforms having crypto node. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> [York Sun: Fix commit message indentation] Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11arm: ls102xa: fixed a bus frequency setting errorTang Yuantian
The bus frequency in SOC node should be clock frequency of platform. That is not true if it is devided by 2. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-09-08arm: ls102xa: Add Freescale LS102xA SoC supportWang Huan
The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>