| Age | Commit message (Expand) | Author |
|---|---|---|
| 2016-08-12 | ARM: non-sec: flush code cacheline aligned | Stefan Agner |
| 2015-05-13 | tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0 | Ian Campbell |
| 2015-05-13 | ARM: Add board-specific initialization hook for PSCI | Jan Kiszka |
| 2015-03-01 | ARM: HYP/non-sec: relocation before enable secondary cores | Peng Fan |
| 2015-01-24 | ARM: HYP/non-sec: Make variable gic_dist_addr as a local one | tang yuantian |
| 2014-07-28 | ARM: HYP/non-sec: remove MIDR check to validate CBAR | Marc Zyngier |
| 2014-07-28 | ARM: HYP/non-sec: allow relocation to secure RAM | Marc Zyngier |
| 2013-10-07 | ARM: virtualization: replace verbose license with SPDX identifier | Andre Przywara |
| 2013-10-03 | ARM: extend non-secure switch to also go into HYP mode | Andre Przywara |
| 2013-10-03 | ARM: add SMP support for non-secure switch | Andre Przywara |
| 2013-10-03 | ARM: add C function to switch to non-secure state | Andre Przywara |
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index : u-boot | |
| NXP/Freescale LSDK U-boot tree with Scalys patches | www-data |
| summaryrefslogtreecommitdiff |