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path: root/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
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2017-10-17armv8: Workaround for USB erratum A-009007 on LS1088ARan Wang
Suplements for patch 2e3dbee02915aaf75834747ff8753282118075dc to cover LS1088A: USB3PHY Observing Intjermittent Failure in Rx Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
2017-09-11armv8/fsl-lsch2: correct QMAN clockHou Zhiqiang
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-09-04armv8: ls1088a: correct pcie fixup compatible stringHou Zhiqiang
LS1088A has the same PCIe controller as LS2088A, and the LS1088A used LS2088A PCIe compatible under Linux. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-08-29 LS1088A_QSPI: SECURE_BOOT: Images validationPrabhakar Kushwaha
Validates PPA, MC, DPC, Bootscript, DPL and Kernel images in ESBC phase using esbc_validate command. Add images validation in default environment under mcinitcmd prior to MC initialization. Add header address for PPA to be validated during ESBC phase for LS1088A platform based on LAyerscape Chasis 3. Moves sec_init prior to ppa_init as for validation of PPA sec must be initialised before the PPA is initialised. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
2017-08-23armv8: fsl-layerscape: Support to add RGMII for ls1088aqdsAshish Kumar
This patch adds support RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
2017-08-23armv8: ls1088ardb: Add support for LS1088ARDB platformAshish Kumar
LS1088A is an ARMv8 implementation. The LS1088ARDB is an evaluatoin platform that supports the LS1088A family SoCs. This patch add basic support of the platform. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
2017-08-23armv8: ls1088a: Add NXP LS1088A SoC supportAshish Kumar
The QorIQ LS1088A processor is built on the Layerscape architecture combining eight ARM A53 processor cores with advanced, high-performance datapath acceleration and networks, peripheral interfaces required for networking, wireless infrastructure, and general-purpose embedded applications. LS1088A is compliant with the Layerscape Chassis Generation 3. Features summary: - Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs - Cores are in 2 cluster of 4-cores each - Cache coherent interconnect (CCI-400) - One 64-bit DDR4 SDRAM memory controller with ECC - Data path acceleration architecture 2.0 (DPAA2) - Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs - QSPI, IFC, 3 PCIe, 1 SATA, 2 USB, 1 SDXC, 2 DUARTs etc Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
2017-08-23armv8: fsl-lsch3: Make CCN-504 related code conditionalAshish Kumar
LS2080 family has CCN-504 cache coherent interconnet. Other SoCs from LSCH3 may have differnt interconnect like LS1088. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2017-08-23armv8:fsl-layerscape: Consolidate registers space defination for CCI-400 busAshish Kumar
CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new CONFIG defination "SYS_FSL_HAS_CCI400" and moves existing register space definaton of CCI-400 bus from immap_lsch2 to fsl_immap, so that it can be used for both chasis 2 and chasis 3. "CONFIG_SYS_CCI400_ADDR" is depricated and new SYS_CCI400_OFFSET is introduced in Kconfig Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2017-08-17arm: Fix USB errata reilated patches issue.Ran Wang
1.Miss definition in Kconfig. 2.Compile switch should be CONFIG_ARCH_LSxxx. 3.Miss some register define. Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
2017-08-17armv8: Add workaround for USB erratum A-009008Suresh Gupta
USB High Speed (HS) EYE Height Adjustment This patch is adding the erratum for LS1043 and LS2080 SoCs. But miss LS1088A due to code base not support LS1088A yet, need to be added in arch/arm/cpu/armv8/fsl-layerscape/Kconfig in the future. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com> Signed-off-by: ran.wang <ran.wang_1@nxp.com>
2017-08-17armv8: Add workaround for USB erratum A-009007Suresh Gupta
USB3PHY Observing Intermittent Failure in Rx This patch is adding the erratum for LS1043 and LS2080 SoCs. But miss LS1088A due to code base not support LS1088A yet, need to be added in arch/arm/cpu/armv8/fsl-layerscape/Kconfig in the future. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com> Signed-off-by: ran.wang <ran.wang_1@nxp.com>
2017-08-17armv8: Add workaround for USB erratum A-008997Suresh Gupta
USB3 LFPS Peak-Peak Differential Output Voltage Adjustment This patch is adding the erratum for LS1043 and LS2080 SoCs. But miss LS1088A due to code base not support LS1088A yet, need to be added in arch/arm/cpu/armv8/fsl-layerscape/Kconfig in the future. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com> Signed-off-by: ran.wang <ran.wang_1@nxp.com>
2017-08-17armv8: Add workaround for USB erratum A-009798Ran Wang
USB High Speed Squelch Threshold Adjustment This patch is adding the erratum for LS1043 and LS2080 SoCs. But miss LS1088A due to code base not support LS1088A yet, need to be added in arch/arm/cpu/armv8/fsl-layerscape/Kconfig in the future. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com> Signed-off-by: ran.wang <ran.wang_1@nxp.com>
2017-08-09armv8: errata: Implement workaround for Cortex-A53 Erratum 855873Alison Wang
855873: An eviction might overtake a cache clean operation Workaround: The erratum can be avoided by upgrading cache clean by address operations to cache clean and invalidate operations. For Cortex-A53 r0p3 and later release, this can be achieved by setting CPUACTLR.ENDCCASCI to 1. This patch is to implement the workaround for this erratum. Signed-off-by: Alison Wang <alison.wang@nxp.com>
2017-08-09LS2080ARDB: QSPI boot: Secure Boot image validationVinitha Pillai-B57223
Validates the images in the ESBC phase for LS2088ARDB platform and QSPI boot using esbc_validate command. Add images validation in default environment under mcinitcmd prior to MC initialization. Adds header address for PPA to be validated during ESBC phase for ARCH_LS2088 and QSPI_BOOT. Moves sec_init prior to ppa_init as for validation of PPA sec must be initialised before the PPA is initialised. Signed-off-by: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
2017-08-09SECURE_BOOT: Unify memory map for Layerscape basedVinitha Pillai-B57223
Unify memory map for Layerscape based platforms as per DASH SDK memory map. This patch includes changes in bootscript, bootscript header and PPA header addresses change as per unified memory map. Signed-off-by: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
2017-06-02armv8: layerscape: Enabling loading PPA during SPL stageYork Sun
Loading PPA in SPL puts the rest of U-Boot (including RAM version loaded later) in EL2 with MMU and cache enabled. Once PPA is loaded, PSCI is available. Signed-off-by: York Sun <york.sun@nxp.com>
2017-05-23armv8: ls2080ardb, ls2080aqds: Adjust memory map for NOR-bootSantan Kumar
This patch adjusts memory map for images on LS2080ARDB and LS2080AQDS NOR flash as below Image Flash Offset RCW+PBI 0x00000000 Boot firmware (U-Boot) 0x00100000 Boot firmware Environment 0x00300000 PPA firmware 0x00400000 PHY firmware 0x00980000 DPAA2 MC 0x00A00000 DPAA2 DPL 0x00D00000 DPAA2 DPC 0x00E00000 Kernel.itb 0x01000000 Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-23armv8: layerscape: Adjust memory mapping for Flash/SD card on LS1043AAlison Wang
This patch is to adjust the memory mapping for FLash/SD card on LS1043AQDS and LS1043ARDB, such as PPA firmware load address, FMAN firmware load address, QE firmware load address, U-Boot start address on serial flash and environment address. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-23armv8: ls2080ardb: Add QSPI-boot supportPriyanka Jain
QSPI-boot is supported on LS2088ARDB RevF board with LS2088A SoC. LS2088ARDB RevF Board has limitation that QIXIS can not be accessed. CONFIG_FSL_QIXIS is not enabled. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-24armv8: fsl-layerscape: Support loading PPA header from eMMC/SD and NAND FlashSumit Garg
Add Kconfig option to support loading PPA header from eMMC/SD and NAND Flash. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17armv8: fsl-lsch3: Instantiate TZASC configuration in 2 groupsAshish kumar
Number of TZASC instances may vary across NXP SoCs. So put TZASC configuration under instance specific defines. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17arm64/ls1046a: Enable ERRATUM_A008850 for ls1046a SoCShengzhou Liu
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17armv8: SECURE_BOOT: Enable chain of trust on LS1012A platformVinitha Pillai-B57223
Define bootscript and its header addresses for QSPI target Also add PPA header address in Kconfig Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17armv8: SECURE_BOOT: Enable chain of trust on LS1046A platformVinitha Pillai-B57223
Define bootscript and its header addresses for QSPI target. Also define PPA header address to enable PPA validation. Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
2017-04-17armv8: fsl-layerscape: SECURE BOOT: Add header address of PPA in kconfigVinitha Pillai-B57223
The header address of PPA defined in Kconfig. Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: Kconfig: fsl-ppa: support load PPA from eMMC/SD and NAND FlashHou Zhiqiang
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28board: freescale: ls2080a/ls2088a: Enable PPASantan Kumar
Enable PPA on LS2080A, LS2088A boards: -LS2080ARDB, LS2080AQDS -LS2088ARDB, LS2088AQDS Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: fsl-lsch3: Conditionally apply workaround for erratum a0009203Ashish kumar
This i2c errata only applies to LS2080A and its variants, namely LS2080A, LS2085A and LS2088A. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-14armv8: ls2080a: Move CONFIG_SYS_MC_RSV_MEM_ALIGN to KconfigYork Sun
Use Kconfig option instead of config macro in header file. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-14armv8: ls2080a: Move CONFIG_FSL_MC_ENET to KconfigYork Sun
Use Kconfig option instead of config macro in header file. Clean up existing usage. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-14armv8: Add global variable resv_ramYork Sun
Use gd->arch.resv_ram to track reserved memory allocation. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-10ARM: Migrate errata to KconfigTom Rini
This moves all of the current ARM errata from various header files and in to Kconfig. This allows for a minor amount of cleanup as we had some instances where both a general common header file was enabling errata as well as the board config. We now just select these once at the higher level in Kconfig Signed-off-by: Tom Rini <trini@konsulko.com>
2017-01-31armv8: ls1046a: Enable workaround for erratum A-008336York Sun
Erratum A-008336 applies to LS1046A per latest SoC document. Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
2017-01-25Convert CONFIG_BOARD_EARLY_INIT_F to KconfigSimon Glass
This converts the following to Kconfig: CONFIG_BOARD_EARLY_INIT_F Signed-off-by: Simon Glass <sjg@chromium.org>
2017-01-25Convert CONFIG_ARCH_EARLY_INIT_R to KconfigSimon Glass
This converts the following to Kconfig: CONFIG_ARCH_EARLY_INIT_R Signed-off-by: Simon Glass <sjg@chromium.org>
2017-01-18kconfig: fsl PPA: move CONFIG_* to KconfigHou Zhiqiang
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCIHou Zhiqiang
Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18armv8/fsl-layerscape: fdt: fixup LS1043A rev1 MSI nodeWenbin Song
The default MSI node in kernel tree is for LS1043A rev1.0 silicon, if rev1.1 silicon used, need to fixup the MSI node to match it. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18armv8/ls1043a: fixup GIC offset for ls1043a rev1Wenbin Song
The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose which offset will be used. The LS1043A rev1.0 silicon only supports the CIG offset with 4K alignment. If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment is used. 64K alignment is the default setting. Overriding the weak smp_kick_all_cpus, the new impletment is able to detect GIC offset. The default GIC offset in kernel device tree is using 4K alignment, it need to be fixed if 64K alignment is detected. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18armv8: fsl-layerscape: Fix SECURE_BOOT configYork Sun
Without a prompt in Kconfig, SECURE_BOOT cannot be selected by defconfig. The option was dropped unintentionally when defconfig files were cleaned up. Three targets were impacted ls1043ardb_SECURE_BOOT, ls2080ardb_SECURE_BOOT, ls2080aqds_SECURE_BOOT. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18armv8/fsl-lsch2: refactor the clock system initializationHou Zhiqiang
Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18ARMv8/fsl-layerscape: Enable data coherency between cores in clusterHou Zhiqiang
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18kconfig: move FSL_PCIE_COMPAT to platform KconfigHou Zhiqiang
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-05ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS to KconfigYork Sun
Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing usage in ls102xa and fsl-layerscape. Remove all powerpc macros in config header and board header files. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-05arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to KconfigYork Sun
Use Kconfig to select errata workaround. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-05fsl_ddr: Move DDR config options to driver KconfigYork Sun
Create driver/ddr/fsl/Kconfig and move existing options. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> [trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-01-05crypto: Move CONFIG_SYS_FSL_SEC_LE and _BE to KconfigYork Sun
Use Kconfig option to set little- or big-endian access to secure boot and trust architecture. Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-05crypto: Move SYS_FSL_SEC_COMPAT into driver KconfigYork Sun
Instead of define CONFIG_SYS_FSL_SEC_COMPAT in header files for PowerPC and ARM SoCs, move it to Kconfig under the driver. Signed-off-by: York Sun <york.sun@nxp.com>
generated by cgit v0.10.2 at 2024-06-16 07:12:26 (GMT)