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H3's CCU includes some switches which disable non-secure access to some
of the more critical clock controls, such as MBUS, PLLs, and main
platform busses.
Configure them to enable non-secure access.
For now the only SoC that has this feature is the H3. For other
platforms just use a default (weak) empty function so things do
not break.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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Secure Memory Touch Arbiter is the same thing as the TrustZone
Protection Controller found on A31/A31s.
Access to many peripherals on the H3 can be controlled by the SMTA,
and the settings default to secure access only.
This patch supports the new settings, and sets them to allow non-secure
access.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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The management data input/output (MDIO) requires open-drain,
i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
this feature. So to TO1.1, need to enable open drain by setting
bits GPR0[8:7] for TO1.1.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
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Check "Figure 19-5. BUS clock generation" of i.MX 6SoloX Applications
Processor Reference Manual and "Figure 18-5. BUS clock generation" of
i.MX 6UltraLite Applications Processor Reference Manual. If mmdc clk
sources from pll4_main_clk(pll_audio), the calculation is wrong.
Fix mmdc_ch0 clk calculation. Also add PLL_AUDIO/VIDEO support
for decode_pll.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
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Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
[hdegoede@redhat.com: Minor cleanups]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
applied with fixing 2 checkpatch warnings:
WARNING: please, no space before tabs
Signed-off-by: Heiko Schocher <hs@denx.de>
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To prepare timer driver to DM/DT conversion do not build the
exiting timer driver when CONFIG_TIMER is defined. But since
omap's SPL doesn't support DM yet so built timer driver only for
SPL build when CONFIG_TIMER is defined.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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This patch moves stm32 sources at one place, with this armv7m now contains
only generic stuff.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
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Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Acked-by: Enric Balletbo Serra <enric.balletbo@collabora.com>
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This commit adds functions issuing calls to secure monitor or
hypervisore. This allows using services such as Power State
Coordination Interface (PSCI) provided by firmware, e.g. ARM
Trusted Firmware (ATF)
The SMC call can destroy all registers declared temporary by the
calling conventions. The clobber list is "x0..x17" because of
this
Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Corey Minyard <cminyard@mvista.com>
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
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This patch adds code which sets up 2-level page tables on ARM64 thus
extending available VA space. CPUs implementing 64k translation
granule are able to use direct PA-VA mapping of the whole 48 bit
address space.
It also adds the ability to reset the SCTRL register at the very beginning
of execution to avoid interference from stale mappings set up by early
firmware/loaders/etc.
Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
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For NXP LPC32xx boards the change enables SPL_DM option, this allows
to use any driver model UART driver in SPL images, hence a restriction
on HSUART in SPL image is removed and well as definitions for non-DM
NS16550 driver, its DM version is used instead.
Because SPL_DM requires malloc(), enable CONFIG_SPL_SYS_MALLOC_SIMPLE
for LPC32xx boards.
The change adds about 5KB to the resulting SPL image (for devkit3250
board SPL image is increased from 10672 to 15608 bytes).
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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On NXP LPC32xx platform for non-SPL builds the change adds
standard (NS16550) and high-speed UARTs to driver model.
Due to specific of DM NS16550 device description UART clock can not be
got in runtime and by default it is set to 13MHz, if board PERIPH_CLK
is different, this should be specified in board configuration file.
For SPL builds HSUARTs are disabled and non-DM NS16550 driver is
compiled, if needed.
The change also updates default configs of devkit3250 and work_92105
boards to reflect updates in platform files.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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On these platforms we have many cases of boards that enable device model
and GPIO support but do not enable OF_CONTROL and pass in a device tree
with the binary. We need to bring in the platform data here as well.
Tested on Beaglebone Black.
Reported-by: Robert Nelson <robertcnelson@gmail.com>
Reported-by: Francisco Aguerre <franciscoaguerre@gmail.com>
Reported-by: Jason Kridner <jkridner@beagleboard.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
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For some board designs, it might be useful to switch the DC-DC
clock source to something else rather the default 24 MHz, e.g.
for EMI reasons.
For this, override the mxs_power_setup_dcdc_clocksource function
in your board support files.
Example:
void mxs_power_setup_dcdc_clocksource(void)
{
mxs_power_switch_dcdc_clocksource(POWER_MISC_FREQSEL_20MHZ);
}
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
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Drop duplicated debug info for tcl.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
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Consecutive write transactions from core to PCI express outbound
path hangs after 25 to 30 transactions depending on core freq.
This erratum enable the mbist clock through COP register setting.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Freescale ARM-based Layerscape contains a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls2080aqds, ls2080ardb and
ls1043aqds boards.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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For LS1043, SEC read/writes are made snoopable by setting
the corresponding bits in SCFG to avoid coherency issues.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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usec2ticks() function has been defined for ARMv8 which will
be used by SEC Driver.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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MC and debug server are not board-specific. Move reserving memory to SoC
file, using the new board_reserve_ram_top function. Reduce debug server
memory by 2MB to make room for secure memory.
In the system with MC and debug server, the top of u-boot memory
is not the end of memory. PRAM is not used for this reservation.
Signed-off-by: York Sun <yorksun@freescale.com>
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DDR has been set as secure in MMU tables. Non-secure master such
as SDHC DMA cannot access data correctly. Mixing secure and non-
secure MMU entries requirs the MMU tables themselves in secure
memory. This patch moves MMU tables into a secure DDR area.
Early MMU tables are changed to set DDR as non-secure. A new
table is added into final MMU tables so secure memory can have
2MB granuality.
gd->secure_ram tracks the location of this secure memory. For
ARMv8 SoCs, the RAM base is not zero and RAM is divided into several
banks. gd->secure_ram needs to be maintained before using. This
maintenance is board-specific, depending on the SoC and memory
bank of the secure memory falls into.
Signed-off-by: York Sun <yorksun@freescale.com>
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As the errata A008336 and A008514 do not apply to all LS series SoCs
(such as LS1021A, LS1043A) we move them to an soc specific file
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the
memory controller performance.
The value: 63b2_0042h comes from the hardware team.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Enable snoop and DVM message on all CCI-400 slave ports. Setting
on disabled feature (snoop or DVM) is ignored by CCI-400.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
[York Sun: Add commit message]
Reviewed-by: York Sun <yorksun@freescale.com>
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Since the changes in a1e56cf the way that we had board_mmc_init()
structured for OMAP parts (so that we always report device 0) are no
longer functional. For now, make the case of booting from the second
device initialize both devices (we have no devices that only have the
second device as MMC). A further rework and consolidation of the
functions should be done at a later date.
Tested on Beaglebone Black (SD and eMMC boot).
Reported-by: Vagrant Cascadian <vagrant@debian.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
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Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.
SNPCNFGCR contains the bits to drive snoop signal
for various masters.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Create a soc.c file to put the code for soc special settings.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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GCC 5.x does not like sizeof(array_variable) and errors out. Change these
calls to be instead sizeof(u8) (as that's what serdes_prtcl_map is) *
SERDES_PRCTL_COUNT (the number of array elements).
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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This patch fixes the DDR3 initialization procedure in
order to comply with DDR3 standard. A 500 us delay is specified
between the DDR3 reset and clock enable signal. Until now,
this delay was not respected. Some DDR3 chips don't bother
but the bigger the RAM becomes the more likely it seems that
this delay is needed. We observed that DRAM > 256 MB from
the manufacturer Samsung have an issue when the specification
is not respected.
Changes:
1) Add a 1 ms wait for L3 timeout error trigger
2) Don't delay DDR3 initialization
Bit 31 of emif_sdram_ref_ctrl shouldn't be set because his
suppresses the initialization of DDR3
Signed-off-by: Samuel Egli <samuel.egli@siemens.com>
Reviewed-by: James Doublesin <doublesin@ti.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Felipe Balbi <balbi@ti.com>
Cc: Roger Meier <r.meier@siemens.com>
Cc: Heiko Schocher <hs@denx.de>
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The read delays were set incorrectly, leading to reliability
issues at higher DRAM clock speeds. This commit adjusts this
to match the vendor boot0 behaviour.
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Tested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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Add some spaces around operators.
Signed-off-by: Olliver Schinagl <o.schinagl@ultimaker.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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Commit 6c739c5d added code to enable i2c bus 4 and 5 on the sun7i SoC
but forgot to extend the range check in clock_twi_onoff, resulting in
the clock not getting enabled.
The range-check is not needed at all, since clock_twi_onoff only gets
called with such high indexes when CONFIG_I2C3_ENABLE / CONFIG_I2C4_ENABLE
is set and Kconfig already only allows these on sun6i / sun7i.
This commit removes the range-check all together fixing i2c bus 4 and 5
not working on sun7i.
Signed-off-by: Olliver Schinagl <o.schinagl@ultimaker.com>
[hdegoede@redhat.com] Remove range check instead of extending it
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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Add support for A83T dram. Register are different from sun8i A33.
init code is similar to A33 dram init.
hope we'll shift duplicate code in dram_sun8i_*
to dram helper in future.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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Add basic clocks pll1, pll5, and some default values from allwinner u-boot.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
[hdegoede@redhat.com] Fix PLL6 init to run at 600 MHz instead of 288 MHz,
fixing the mmc support not working
[hdegoede@redhat.com] Fix PLL init code to properly wait for the PLL-s to
stabilize, fixing cold-booting directly from sdcard not working
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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Enabled support for AXP818 in SPL and u-boot.
DCDC1, DCDC2, DCDC3 and DCSC5 are enabled.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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On A83T, PB9,PB10 are UART0 pins.
On allwinner A83T Dev board(h8homlet), this uart0 serial connector
is exposed.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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Allwinner A83T is octa-core cortex-a7 SOC.
This enables support for A83T.
SMP is not yet supported.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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cc: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
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We now want to make sure that we have the platform data for NS16550 when
we do not have OF_CONTROL set.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Kamil Lulko <kamil.lulko@gmail.com>
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With gcc-5.x we get warning about inline non-static functions referring to
static elements.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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At the moment, the desired brownout is at 1.0V. However,
this setting cannot be realized by hardware since we have
only 3 bits to represent the voltage difference from the
target value.
Target value is 1500 mV, brownout target is 1000 mV,
voltage steps are 25 mV.
Register content calculation:
(1500 [mV] - 1000 [mV]) / 25 [mV] = 20 (decimal) = 0x14
Register takes only 3 bits, that is 0x4.
But 0x4 * 25 [mV] = 100 [mV], that means that actual
brownout level is 1500 [mV] - 100 [mV] = 1.4 V.
Minimum possible BO level is
1500 [mV] - 0x7 * 25 [mV] = 1315 [mV].
So lets use this value as desired BO value (which is
also the same as FSL bootlets use).
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
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If the core runs at higher than x3 speed of the platform, there is
possiblity about sev instruction to getting missed by other cores.
This is because of SoC Run Control block may not able to sample
the EVENTI(Sev) signals.
Configure Run Control and EPU to periodically send out EVENTI signals to
wake up A57 cores.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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When one core is released, other cores may not have valid entry
address. Those cores are trapped by "wfe" and wait for further
instruction. When their address is set, they need to be kicked
off by "sev".
Signed-off-by: York Sun <yorksun@freescale.com>
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