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2015-07-28ARM: zynq: DT: Add missing interrupt for L2 pl310Michal Simek
Add pl310 interrupt to the Zynq devicetree. Signed-off-by: Alex Wilson <alex.david.wilson@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Get rid of ps-clk-frequencyMichal Simek
ps-clk-frequency is platform specific setting and shouldn't be the part of DTSI. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Update years in copyrightMichal Simek
Trivial. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Add reference to bus nodeMichal Simek
For adding OCM memory in platform DTS is necessary to have reference to amba bus. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Add pinctrl nodeMichal Simek
Add pinctrl node to DTSI. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Cleanup address-cells and size-cellsMichal Simek
Remove unneeded address-cells form intc node because it is already setup in parent node. Add missing address-cells and size-cells to eth node to be shared for every platform DTSes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Clean up timer device tree nodesMichal Simek
Separate IRQ cells from each other for easier reading. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Use the zynq binding with macbMichal Simek
Use the new zynq binding for macb ethernet, since it will disable half duplex gigabit like the Zynq TRM says to do. Also allow the compatible cadence gem binding that won't disable half duplex but works otherwise. Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Fix GEM register area sizeMichal Simek
The size of the GEM's register area is only 0x1000 bytes. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28spi: Fix zynq SPI bindingMichal Simek
Zynq is using Cadence IP where binding is documented in the Linux kernel and there is no reason to use different binding. Synchronize it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Remove 222 MHz OPPMichal Simek
Due to dependencies between timer and CPU frequency, only changes by powers of two are allowed. The clocksource driver prevents other changes, but with cpufreq and its governors it can result in being spammed with error messages constantly. Hence, remove the 222 MHz OPP. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Migrate UART to Cadence bindingMichal Simek
The Zynq UART is Cadence IP and the driver has been renamed accordingly. Migrate the DT to use the new binding for the UART driver. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Acked-by: Rob Herring <robh@kernel.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Add a fixed regulator for CPU voltageMichal Simek
To silence the warning cpufreq_cpu0: failed to get cpu0 regulator: -19 from the cpufreq driver regarding a missing regulator, add a fixed regulator to the DT. Zynq does not support voltage scaling and the CPU rail should always be supplied with 1 V, hence it is added in the SOC-level dtsi. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Add missing nodes to DTSIMichal Simek
Add ADC, CAN, GPIO, MC, DMA, DEVCFG, USB, Watchdog IPs to DTSI. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28ARM: zynq: DT: Use the right names for nodesMichal Simek
Based on SPEC you right names with addresses. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-01spi: zynq_spi: Add fdt support in driverJagan Teki
Now zynq spi driver platform data is controlled by devicetree, enable the status by saying "okay" on respective board dts to use the devicetree generated platdata. Ex: &spi1 { status = "okay"; }; Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
2015-07-01dts: zynq: Add zynq spi controller nodesJagan Teki
This patch adds zynq spi controller nodes in zynq-7000.dtsi. Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
2014-05-15zynq: import zynq-7000.dtsi from Linux KernelMasahiro Yamada
Our current motivation is to use OF initialization for RAM and UART. But adding full DTS would be helpful in future, for instance, for OF configuration of Ethernet, MMC, USB, etc. This commit imports arch/arm/boot/dts/zynq-7000.dtsi from Linux 3.15-rc5 and adjusts the license comment block for SPDX. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Suggested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-01-10dts: zynq: Add basic fdt supportJagannadha Sutradharudu Teki
This patch provides a basic fdt support for zynq u-boot. zynq-7000.dtsi-> initial arch dts file zynq-zed.dts -> initial zed board dts file more devices should be added in subsequent patches. u-boot build: once configuring of a board done for building dtb with zynq-zed.dts as an input zynq-uboot> make DEVICE_TREE=zynq-zed Enabled CONFIG_OF_SEPARATE for building dtb separately. There is a new binary called u-boot-dtb.bin which is a u-boot with devicetree supported. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>