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2016-12-09ARM: uniphier: remove unneeded parenthesesMasahiro Yamada
Just a cosmetic cleanup. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: update DRAM init code for LD11 SoCMasahiro Yamada
Introduce run-time DDR PHY training. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: support DDR PHY parameter dump command for LD11Masahiro Yamada
Add the LD11 SoC data and adjuts the printf() format because this is a 64-bit SoC. Otherwise, 16-digits pointer addresses would break the log format. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: refactor DDR PHY parameter dump commandMasahiro Yamada
Do not hard-code the number of DX blocks because it is a different value for LD11 SoC. Move the macro NR_DATX8_PER_DDRPHY to ddrphy-training.c since it is the last user. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: rework existing DDR PHY code to reuse for LD11 SoCMasahiro Yamada
The DDR PHY register view of LD11 is slightly different from that of LD4/Pro4/sLD8, but it will be possible to share the register macros (and I want to re-use as much code as possible). Change the code in the more flexible form. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: fix DRAM init poll address for LD4, Pro4, sLD8Masahiro Yamada
The status register should be polled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: rename ddrphy-ld20-regs.h to ddruqphy-regs.hMasahiro Yamada
This PHY might be used for other SoCs in the future. Avoid including the SoC name in the header name. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: update DRAM init code for LD20 SoC (3rd)Masahiro Yamada
- Constify UMC setting data arrays - Merge data arrays *_d0 and *_d1. - Add PHY parameters for LD20 C1 board Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-10ARM: uniphier: update DRAM init code for LD20 SoC (2nd)Masahiro Yamada
- Do not reference CONFIG_DDR_FREQ; now the DDR frequency is passed from the uniphier_board_data structure - Constify parameter arrays - Tidy up cluttered macros - Lots of code cleanups - Lots of coding style fixes Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18ARM: uniphier: update DRAM init code for LD20 SoCMasahiro Yamada
Import the latest version from the Diag software. - Support LD21 SoC (including DDR chips in the package) - Per-board granule adjustment for both reference and TV boards - Misc cleanups Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-26treewide: fix "followings" to "following"Masahiro Yamada
Most of them are my mistakes. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-07-23ARM: uniphier: introduce flags to uniphier_board_data structureMasahiro Yamada
I need to add more board attributes, so the "flags" member will be handier than separate boolean ones. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-07-23ARM: uniphier: use (devm_)ioremap() instead of map_sysmem()Masahiro Yamada
This does not have much impact on behavior, but makes code look more more like Linux. The use of devm_ioremap() often helps to delete .remove callbacks entirely. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-05-25ARM: uniphier: add PH1-LD11 SoC supportMasahiro Yamada
This is a low-cost ARMv8 SoC from Socionext Inc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-05-25ARM: uniphier: rename UMC register macros of PH1-LD20Masahiro Yamada
Correct some register names. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-05-25ARM: uniphier: rename umc-ld20-regs.h to umc64-regs.hMasahiro Yamada
This header will be shared between PH1-LD11 and PH1-LD20 (and hopefully new ARMv8 SoCs developed in the future), so umc64-regs.h would be a better fit. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-04-24ARM: uniphier: add PH1-LD20 SoC supportMasahiro Yamada
This is the first ARMv8 SoC from Socionext Inc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-31ARM: uniphier: rename function names ph1_* to uniphier_*Masahiro Yamada
Eliminate the "ph1"_ prefixes from function names because "uniphier_" describes the SoC familiy better. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-23ARM: uniphier: drop ifdef in ddrphy-regs.hMasahiro Yamada
The ifdef conditionals in header files prevent us from multi-SoC support in a single U-Boot image. Detect SoC specific parameters run-time rather than define them statically with an ifdef in ddrphy-regs.h. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-23ARM: uniphier: drop PH1- prefix from CONFIG options and file namesMasahiro Yamada
The current CONFIG names like "CONFIG_ARCH_UNIPHIER_PH1_PRO4" is too long. It would not hurt to drop "PH1_" because "UNIPHIER_" already well specifies the SoC family. Also, rename files for consistency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-08ARM: uniphier: fix build error when CONFIG_CMD_DDRMPHY_DUMP=yMasahiro Yamada
The build fails if compiled with CONFIG_CMD_DDRMPHY_DUMP=y since commit 46abfcc99e04 ("ARM: uniphier: rework struct uniphier_board_data"). Fixes: 46abfcc99e04 ("ARM: uniphier: rework struct uniphier_board_data") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-28ARM: uniphier: rename variable for DRAM controller base addressMasahiro Yamada
Rename the variable that contains the base address for consistency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-28ARM: uniphier: deprecate umc_dram_init_{start, poll}Masahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-28ARM: uniphier: remove unused macros for UMC base addressesMasahiro Yamada
These macros are no longer used. These base addresses are SoC-dependent, so they should not be placed in the header. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-28ARM: uniphier: rework DRAM size handling in UMC init codeMasahiro Yamada
Currently, DRAM size is converted twice: size in byte -> size in Gbit -> enum Optimize the code by converting the "size in byte" into enum directly. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-28ARM: uniphier: optimize PH1-Pro4 UMC init code with "for" loopMasahiro Yamada
Now this code can be re-written with a "for" statement instead of calling the same function multiple times. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-28ARM: uniphier: optimize PH1-LD4 UMC init code with "for" loopMasahiro Yamada
Now this code can be re-written with a "for" statement instead of calling the same function multiple times. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-28ARM: uniphier: optimize PH1-sLD8 UMC init code with "for" loopMasahiro Yamada
Now this code can be re-written with a "for" statement instead of calling the same function multiple times. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-28ARM: uniphier: refactor UMC init code for PH1-LD4Masahiro Yamada
Move frequency-dependent register settings to arrays for clean-up. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-28ARM: uniphier: support more DRAM use cases for PH1-sLD8Masahiro Yamada
Support DDR3-1600 / 512MB DDR size. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-28ARM: uniphier: refactor UMC init code for PH1-sLD8Masahiro Yamada
Move frequency-dependent register settings to arrays for clean-up. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-28ARM: uniphier: refactor DDR-PHY init codeMasahiro Yamada
The if-else statements for the frequency-dependent register settings seem clumsy. Moving them to arrays would make it cleaner. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-28ARM: uniphier: remove unused argument of ph1_ld4_ddrphy_init()Masahiro Yamada
The DDR PHY settings no longer depend on the DRAM size. Drop the argument from the init function. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-28ARM: uniphier: merge DDR PHY init code for 3 SoCsMasahiro Yamada
Now these three are almost the same. The only difference is the DTPR1 register dependency on the DRAM size, but it can be ignored. (It has already been ignored in PH1-sLD8 and PH1-Pro4.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-28ARM: uniphier: add a field to specify DDR3+Masahiro Yamada
Add a field to distinguish DDR3+ from (standard) DDR3. It also allows to delete CONFIG_DDR_STANDARD (this is not a software configuration, but a board attribute). Default DDR3 spec for each SoC: PH1-LD4, PH1-sLD8: DDR3+ Others: DDR3 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-28ARM: uniphier: disable debug circuit clocks for PH1-Pro4Masahiro Yamada
These settings control the clocks around the memory controller. The debug ability is unneeded once it works properly. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-28ARM: uniphier: remove UMC_INITCTL* and UMC_DRMR* settingsMasahiro Yamada
These settings were used only for the PH1-sLD3 and older SoCs. The PH1-LD4 and newer one just ignore them because their DDR-PHY take care of such timing parameters instead. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-28ARM: uniphier: refactor UMC init code for ProXstream2Masahiro Yamada
Currently, a dummy value is defined for the UMC_SPCCTLA register when the DRAM size is zero. This seems weird because the controller does not need setting in the first place if the size is zero. Also, redefine enum dram_size to represent the DRAM size per 16-bit unit. This makes things simpler because the channel 0 and 1 are connected with 32-bit width DRAM, while the channel 2 is connected with 16-bit width one. I am renaming SIZE_* into DRAM_SZ_* (and also FREQ_* to DRAM_FREQ_* for consistency) while I am here because SIZE_* might be easily mixed-up with the macros in include/linux/sizes.h. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-28ARM: uniphier: use pr_err() where possibleMasahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-28ARM: uniphier: optimize ProXstream2 UMC init code with "for" loopMasahiro Yamada
Now this code can be re-written with a "for" statement instead of calling the same function multiple times. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-28ARM: uniphier: rework struct uniphier_board_dataMasahiro Yamada
This commit reworks "struct uniphier_board_data" with an array of DRAM channel data in it. It will allow further cleanups by means of "for" statements that iterate over the DDR channels. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-28ARM: uniphier: remove unused umc_polling()Masahiro Yamada
This function is unused. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14ARM: uniphier: adjust DDR clock delay line for ProXstream2Masahiro Yamada
It turned out that DDR channel 2 was not working on ProXstream2 Vodka board. Add the missing ACBLDR0 register setting to adjust the delay between the clock lines and the address/command lines. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14ARM: uniphier: move cmd_ddrmphy.c to fix build errorMasahiro Yamada
If CONFIG_CMD_DDRMPHY_DUMP is enabled, the build fails. Fixes: 93d92d46cd01 ("ARM: uniphier: add dump command for DDR Multi PHY registers") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14ARM: uniphier: fix makefiles to build cmd_ddr(m)phy.cMasahiro Yamada
The U-Boot proper building needs to descend arch/arm/mach-uniphier/dram to build these commands. Fixes: 93d92d46cd01 ("ARM: uniphier: add dump command for DDR Multi PHY registers") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14ARM: uniphier: support some more DRAM use cases on PH1-Pro4 boardsMasahiro Yamada
Some of PH1-Pro4 boards are equipped with larger amount of DRAM than the reference board. Add UMC settings to support them. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-01-19ARM: uniphier: remove unneeded if conditionalsMasahiro Yamada
The if block does the same as the else block does. The conditional is not necessary at all. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-01-19ARM: uniphier: move UMC register macros to umc-regs.hMasahiro Yamada
The umc-proxstream2.c defiens the same macros as in umc-regs.h. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-01-12ARM: uniphier: add dump command for DDR Multi PHY registersMasahiro Yamada
The ProXstream2/PH1-LD6b is integrated with a new IP for DDR PHY which is not register-compatible with the former SoCs. Add a new command to support the register dump of this IP. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-01-12ARM: uniphier: add DRAM init code for ProXstream2/PH1-LD6bMasahiro Yamada
As mentioned in the log of commit 019df879a93e2 (ARM: uniphier: add ProXstream2 and PH1-LD6b support), the DRAM init code was missing for a long time. Finally, here it is. SPL works now. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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