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2017-01-17ARM: uniphier: refactor MEMCONF init codeMasahiro Yamada
Currently, memconf-sld3.c and memconf-pxs2.c duplicate the code. There are 3 patterns in terms of MEMCONF init: - DRAM 2 channels: LD4, sLD8, Pro4, Pro5, LD11 - DRAM 3 channels: sLD3 - DRAM 3 channels (Ch2 is disable by MEMCONF[21]): Pxs2, LD20 All of them can be moved into a single file by a little more refactoring. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-17ARM: uniphier: split out UMC clock enableMasahiro Yamada
The clock enable bits for UMC are more SoC-specific than for the other hardware blocks. Separate the UMC clocks and the other clocks for better code reuse across SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-17ARM: uniphier: remove unneeded argument of uniphier_ld20_pll_init()Masahiro Yamada
At first, we thought the LD20 PLL setting would be board dependent, but this argument turned out unneeded after all. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-12-12Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini
2016-12-09ARM: uniphier: remove unneeded parenthesesMasahiro Yamada
Just a cosmetic cleanup. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-12-09ARM: uniphier: remove unneeded initializerMasahiro Yamada
This will be used to store the return value of readl(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-12-09spl: uniphier: Drop spl_board_announce_boot_device()Simon Glass
This function is not used anymore. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-12-09spl: Add a name to the SPL load-image methodsSimon Glass
It is useful to name each method so that we can print out this name when using the method. Currently this happens using a separate function. In preparation for unifying this, add a name to each method. The name is only available if we have libcommon support (i.e can use printf()). Signed-off-by: Simon Glass <sjg@chromium.org>
2016-10-29ARM: uniphier: update DRAM init code for LD11 SoCMasahiro Yamada
Introduce run-time DDR PHY training. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: support DDR PHY parameter dump command for LD11Masahiro Yamada
Add the LD11 SoC data and adjuts the printf() format because this is a 64-bit SoC. Otherwise, 16-digits pointer addresses would break the log format. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: refactor DDR PHY parameter dump commandMasahiro Yamada
Do not hard-code the number of DX blocks because it is a different value for LD11 SoC. Move the macro NR_DATX8_PER_DDRPHY to ddrphy-training.c since it is the last user. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: rework existing DDR PHY code to reuse for LD11 SoCMasahiro Yamada
The DDR PHY register view of LD11 is slightly different from that of LD4/Pro4/sLD8, but it will be possible to share the register macros (and I want to re-use as much code as possible). Change the code in the more flexible form. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: do not run harmful code for USB boot mode of LD11 ES3Masahiro Yamada
The USB boot without the stand-by MPU is available on ES3 or later of LD11 SoC, but the code in this if-conditional block must not be run when booting from USB. Check if the boot device is USB, and skip the code in the case. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: enable clocks to MIO/STDMAC on LD11 if USB is enabledMasahiro Yamada
At the moment, the clk driver is not clever enough to automatically enable parent clocks like Linux. Enable the STDMAC clock explicitly if USB is enabled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: fix DRAM init poll address for LD4, Pro4, sLD8Masahiro Yamada
The status register should be polled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: rename ddrphy-ld20-regs.h to ddruqphy-regs.hMasahiro Yamada
This PHY might be used for other SoCs in the future. Avoid including the SoC name in the header name. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: update DRAM init code for LD20 SoC (3rd)Masahiro Yamada
- Constify UMC setting data arrays - Merge data arrays *_d0 and *_d1. - Add PHY parameters for LD20 C1 board Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: remove unused board attribute macrosMasahiro Yamada
After SoC evaluation, they turned out unnecessary. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: enable SSC for more PLLs for LD20 SoCMasahiro Yamada
For Electro-Magnetic Compatibility. Set CPLL, SPLL2, MPLL, VPPLL, GPPLL, DPLL* to SSC rate 1 percent. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: remove unneeded mdelay() in PLL setting functionMasahiro Yamada
This delay is already cared by the callers of this function. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-29ARM: uniphier: adjust fdt_file environment handling to latest LinuxMasahiro Yamada
The environment fdt_file is useful to remember the appropriate DTB file name. Adjust it to the recent renaming in the upstream kernel. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-18ARM: uniphier: remove unnecessary EHCI reset deassertionMasahiro Yamada
It is now deasserted by the reset controller driver. Drop the ad-hoc code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-18ARM: dts: uniphier: sync DT with latest LinuxMasahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-18ARM: uniphier: fix addresses of Cortex-A72 gear setting macrosMasahiro Yamada
My mistake during copy-paste work. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-13libfdt: Bring in upstream stringlist functionsSimon Glass
These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org>
2016-10-10ARM: uniphier: insert udelay() just before support_card_reset_deassert()Masahiro Yamada
As for LD11/LD20, we can no longer rely on the udelay() in the PLL init functions. udelay(200) is needed here to keep the ethernet device in the reset state for enough time. Anyway, 200 usec is quite short for humans, so nobody cares it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-10ARM: uniphier: add work-around for VBO noise problemMasahiro Yamada
Raise the VDD09 voltage line to 1.0V to suppress VBO noise. This errata work-around code is needed only for ES1. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-10ARM: uniphier: update DRAM init code for LD20 SoC (2nd)Masahiro Yamada
- Do not reference CONFIG_DDR_FREQ; now the DDR frequency is passed from the uniphier_board_data structure - Constify parameter arrays - Tidy up cluttered macros - Lots of code cleanups - Lots of coding style fixes Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-10ARM: uniphier: enable SSC for DPLL (DRAM PLL) on LD11 SoCMasahiro Yamada
For Electro-Magnetic Compatibility test. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-10ARM: uniphier: do not setup pins for System Bus on NAND boot modeMasahiro Yamada
For LD11 and LD20 SoCs, the System Bus and NAND are multiplexed in the same I/O pins. When booting from a NAND device, pin-mux for the System Bus must not be set-up because they are exclusive with each other. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-06spl: Pass spl_image as a parameter to load_image() methodsSimon Glass
Rather than having a global variable, pass the spl_image as a parameter. This avoids BSS use, and makes it clearer what the function is actually doing. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-06spl: Convert spl_board_load_image() to use linker listSimon Glass
Add a linker list declaration for this method and remove the explicit switch() code. Update existing users. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-06spl: Convert boot_device into a structSimon Glass
At present some spl_xxx_load_image() functions take a parameter and some don't. Of those that do, most take an integer but one takes a string. Convert this parameter into a struct so that we can pass all functions the same thing. This will allow us to use a common function signature. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-06spl: Add a parameter to spl_parse_image_header()Simon Glass
Instead of using the global spl_image variable, pass the required struct in as an argument. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-09-22ARM: uniphier: add PLL init code for LD11 SoCMasahiro Yamada
- Initialize PLLs (SPL initializes only DPLL to save the precious SPL memory footprint) - Adjust CPLL/MPLL to the final tape-out frequency - Set the Cortex-A53 clock to the maximum frequency since it is running at 500MHz (SPLL/4) on startup Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-22ARM: uniphier: move CONFIG_SPL_* to defconfig or selectMasahiro Yamada
As I repeated in the ML, I am unhappy with config entries with bare defaults. Kick them out of arch/arm/mach-uniphier/Kconfig. Currently, CONFIG_SPL_SERIAL_SUPPORT is not user-configurable (build fails without it), but it should be fixed later anyway, so I am moving CONFIG_SPL_SERIAL_SUPPORT to defconfigs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-09-18Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini
2016-09-18ARM: uniphier: update DRAM init code for LD20 SoCMasahiro Yamada
Import the latest version from the Diag software. - Support LD21 SoC (including DDR chips in the package) - Per-board granule adjustment for both reference and TV boards - Misc cleanups Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18ARM: uniphier: add PLL init code for LD20 SoCMasahiro Yamada
Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot proper. Split the common code into pll-base-ld20.c for easier re-use. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18ARM: uniphier: collect clock/PLL init code into a single directoryMasahiro Yamada
Now PLLs for DRAM controller are initialized in SPL, and the others in U-Boot proper. Setting up all of them in a single directory will be helpful when we want to share code between SPL and U-Boot proper. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18ARM: uniphier: move PLL init code to U-Boot proper where possibleMasahiro Yamada
The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18ARM: uniphier: rename CONFIG_DPLL_SSC_RATE_1PERMasahiro Yamada
Basically, this should not be configured by users. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18ARM: uniphier: move XIRQ pin-mux settings of LD11/LD20Masahiro Yamada
This is the last code in the mach-uniphier/pinctrl/ directory. Push the remaining code out to delete the directory entirely. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18ARM: uniphier: consolidate System Bus pin-mux settings for LD11/LD20Masahiro Yamada
Use the pin-mux data in the pinctrl drivers by directly calling pinctrl_generic_set_state(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18ARM: uniphier: consolidate NAND pin-mux settingsMasahiro Yamada
The NAND subsystem has not supported the Driver Model yet, but the NAND pin-mux data are already in the pinctrl drivers. Use them by calling pinctrl_generic_set_state() directly. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18ARM: uniphier: remove ad-hoc pin-mux code for sLD3Masahiro Yamada
These settings are nicely cared by the pinctrl driver now. Remove. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18ARM: uniphier: remove redundant pin-muxing for EA24 pin of sLD3 SoCMasahiro Yamada
This is enabled by default for all the supported boot modes. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16Convert CONFIG_SPL_SERIAL_SUPPORT to KconfigSimon Glass
Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16Convert CONFIG_SPL_NAND_SUPPORT to KconfigSimon Glass
Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16Convert CONFIG_SPL_MMC_SUPPORT to KconfigSimon Glass
Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
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