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trini: Disable CONFIG_SPL_USE_ARCH_MEMSET on orangepi_2
Signed-off-by: Tom Rini <trini@konsulko.com>
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This is an weak function present on all archs so we should have it in the
common header file. Remove it from arch-specific headers and add a
function comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
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By making dram_init_banksize() return an error code we can drop the
wrapper. Adjust this and clean up all implementations.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
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At present we cannot use this function as an init sequence call without a
wrapper, since it returns the RAM size. Adjust it to set the RAM size in
global_data instead, and return 0 on success.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
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It looks like only cm5200 and tqm8xx use this feature, so we don't really
need it in generic code. Drop it and have the users access gd->board_type
directly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
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The board is now manufactured by Aries Embedded GmbH , rename it.
Signed-off-by: Marek Vasut <marex@denx.de>
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The board is now manufactured by Aries Embedded GmbH , rename it.
Signed-off-by: Marek Vasut <marex@denx.de>
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The OrangePi PC 2 is a typical SBC with the 64-bit Allwinner H5 SoC.
Add a (64-bit only) defconfig defining the required options to build
the U-Boot proper.
Create a new .dts file for it by including the (32-bit) H3 SoC .dtsi
and changing the differing components accordingly.
This is a preliminary device tree mostly for U-Boot's own sake, it
is expected to be updated once the official DT gets accepted upstream.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
[squash the commits, update the commit message]
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
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The Allwinner H5 Soc is bascially an H3 with high SRAM and ARMv8 cores.
As the peripherals and the pinmuxing are almost identical, we piggy
back on the shared MACH_SUN8I_H3_H5 config symbol.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
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The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores.
To allow sharing the clocks, GPIO and driver code easily, create an
architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol.
Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and
let it be selected by a new shared Kconfig option.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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The DRAM controller in the Allwinner H5 SoC is again very similar to
the one in the H3 and A64.
Based on the existing socid parameter, add support for this controller
by reusing the bulk of the code and only deviating where needed.
These new bits set or cleared here and there have been mostly found by
looking at DRAM register dumps after using the H5 boot0 and comparing
them to what we set in the code. So for now it's mostly unclear what
those bits actually mean - hence the missing names and comments.
Also add the delay line parameters taken from the boot0 and libdram
disassembly.
Register setup differences between H5 and H3 are courtesy of Jens Kuske.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Every armv8 board needs the memory map, so change the #ifdef to
ARM64 to avoid enumerating every single board or SoC.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
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Traditionally Allwinner SoCs have their boot ROM mapped just below 4GB,
while the first SRAM region is mapped at address 0.
With the extended physical memory support of the A80 this was changed,
so the BROM is now at address 0 and the SRAM region starts right behind
this at 64KB. This configuration seems to be called "high SRAM".
Instead of enumerating the SoCs which have copied this configuration,
let's call a spade a spade and introduce a Kconfig option for this setup.
SoCs implementing this (A80, A64 and H5, so far), can then select this
configuration.
Simplify the config header definition on the way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
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Instead of enumerating all SoC families that need that bit set, let's
just express this more clearly: The SMP bits needs to be set on
SMP capable ARMv7 CPUs. It's much easier in Kconfig to express it the
other way round, so we use ! CPU_IS_UP and ! ARM64.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Some Freescale boards used an extra version of the constant to hold the
Generic Timer frequency. This can easily be covered by the now unified
COUNTER_FREQUENCY constant, so remove this extra variable from those
boards.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
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Many ARMv8 boards define a constant COUNTER_FREQUENCY to specify the
frequency of the ARM Generic Timer (aka. arch timer).
ARMv7 boards traditionally used CONFIG_TIMER_CLK_FREQ for the same
purpose. It seems useful to unify them.
Since there are less occurences of the latter version, lets convert all
users over to COUNTER_FREQUENCY.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
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If we take the liberty to use register r0 to perform our bit set, we
should be nice enough to tell the compiler about it.
Add r0 to the clobber list to avoid potential mayhem.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Jagan Teki <jagan@openedev.com>
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This patch adds a call to dm_remove_devices_flags() to
announce_and_cleanup() so that drivers that have one of the removal flags
set (e.g. DM_FLAG_ACTIVE_DMA_REMOVE) in their driver struct, may do some
last-stage cleanup before the OS is started.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
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MiQi is rk3288 based development board with 1 or 2 GB SDRAM, 16 GB eMMC,
micro SD card interface, 4 USB 2.0 ports, HDMI, gigabit Ethernet and
expansion ports.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Eddie Cai <eddie.cai.linux@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Sort rk3288 boards in alphabetical order.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Eddie Cai <eddie.cai.linux@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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The (shared) rk3399.dtsi had defined the 'rockchip,vbus-gpio'
properties for each USB 3.0 controller.
As the GPIO usage will vary (e.g. one of those GPIOs shuts down one of
the regulators on the RK3399-Q7) between boards, we move this from the
shared dtsi into the device tree file for the EVB board which these
GPIO definitions match.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
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The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399
in a Qseven-compatible form-factor.
These changes add a device-tree describing the board and its
interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card).
This includes the following changes from the original development:
* dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile
* dts: rk3399-puma: add gmac for the RK3399-Q7
This change enables the Gigabit Ethernet support on the RK3399-Q7.
* dts: rk3399-puma: use serial0 for stdout
* dts: rk3399-puma: prepare the sdmmc node for SPL booting
* dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash
The RK3399-Q7 (Puma) unsually (this is a build-time option for
customised boards) has an on-module SPI-flash connected to SPI1.
As of today, this is a Winbond W25Q32DW (32MBit) device.
The SPI5 controller is routed to the Q7 edge connector and provides
general-purpose SPI connectivity for customer base-boards.
With some minor improvements on integration into our outbound tree
- explicitly modelled the SPI flash as 'spiflash' under spi0
[dts: rk3399-puma: explicitly model spi-flash under spi1]
- renamed the aliases to spi0 and spi1 to allow easier use of
commands and legacy (SPL) infrastructure... i.e. the controllers
will be 0 and 1 for 'sf probe', 'sspi', etc.
[dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands]
* dts: rk3399-puma: include SPI in the spl-boot-order property
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
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For the initial validation of the RK3399-Q7 (Puma), the DDR3 has been
clocked at 666MHz (i.e. DDR3-1333) using the same (safe) settings as
used in Rockchip's MiniLoader.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
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The RK3399 does not have any boot selection pins and the BootROM probes
the boot interfaces using the following boot-order:
1. SPI
2. eMMC (sdhci in DTS)
3. SD card (sdmmc in DTS)
4. USB loader
For ease of deployment, the SPL stage should mirror the boot order of
the ROM and use the same probing order (assuming that valid images can
be detected by SPL) unless instructed otherwise. The boot-order can
then be configured via the 'u-boot,spl-boot-order' property in the
chosen-node of the DTS.
While this approach is easily extensible to other boards, it is only
implemented for the RK3399 for now, as the large SRAM on the RK3399
makes this easy to fit the needed infrastructure into SPL and our
production setup already runs with DM, OF_CONTROL and BLK in SPL.
The new boot-order property is expected to be used in conjunction with
FIT images (and all legacy image formats disabled via Kconfig).
A boot-sequence with probing and fallthroughs from SPI via eMMC to SD
card (i.e. &spiflash, &sdhci, &sdmmc) has been validated on the RK3399-Q7.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
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The Rock is a RK3188 based single board computer by Radxa.
Currently it still relies on the proprietary DDR init and
cannot use the generic SPL, but at least is able to boot
a linux kernel and system up to a regular login prompt.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fix sort order in defconfig, enable CONFIG_SPL_TINY_MEMSET:
Signed-off-by: Simon Glass <sjg@chromium.org>
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firefly have a usb host. add dts node to provide power supply
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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This change adds the gmac node (i.e. the GMAC Ethernet controller) as
defined in the Linux DTS.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
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The GMAC in the RK3399 is very similar to the RK3288 variant (i.e. it
is a Designware GMAC core and requires similar configuration as the
RK3288 to switch it to RGMII and set up the TX/RX delays for Gigabit).
The key difference is that the register offsets (within the GRF block)
and bit-offsets (within those registers) used to hold the configuration
differ between the various RK32/33 CPUs.
This change refactors the gmac_rockchip.c driver to use a function
table (selected via driver_data) to factor out these differences. Each
function's implementation then matches the underlying processor.
Some collateral changes are needed in the definitions describing the
bits and offsets in the GRF are needed to prefix each set of symbolic
constants with the SoC name to avoid name clashes... and in doing so,
the shifts for masks and constants have been moved into the header
files for readability (and to make it easier to stay below 80 chars).
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fixed commit message typo s/factor our/factor out/:
Signed-off-by: Simon Glass <sjg@chromium.org>
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To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this
point), we need support for additional pin-configuration. This commit
adds the pinctrl support for GMAC in RGMII signalling mode:
* adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID
* adds the required defines (in the GRF support) for configuring the
GPIOC pins for RGMII
* configures the RGMII pins (in GPIOC) when requested via pinctrl
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
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An earlier upstream change contained an unconditional debug message
which would show up as a message similar to the following in the
U-Boot startup (after the ATF and before the U-Boot banner):
time 159f019, 0
This commit removes this message (instead of making if conditional on
being a debug-build), as it doesn't pertain to any initialisation done
in this file.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Designware HDMI controller and phy are used in other SoCs as well. Split
out platform independent code.
DW HDMI has 8 bit registers but they can be represented as 32 bit
registers as well. Add support to select access mode.
EDID reading code use reading by blocks which is not supported by other
SoCs in general. Make it more general using byte by byte approach, which
is also used in Linux driver.
Finally, not all DW HDMI controllers are accompanied with DW HDMI phy.
Support custom phys by making controller code independent from phy code.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Tested-by: Nickey Yang <nickey.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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The armclk starts in slow mode (24MHz) on the rk3188, which results in U-Boot
startup taking a lot of time (U-Boot itself, but also the rc4 decoding done
in the bootrom).
With default pmic settings we can always reach a safe frequency of 600MHz
which is also the frequency the proprietary loader left the armclk at,
without needing access to the systems pmic.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
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The armclk starts in slow mode (24MHz) on the rk3188, which makes the whole
startup take a lot of time. We therefore want to at least move to the safe
600MHz value we can use with default pmic settings.
This is also the freqency the proprietary sdram-init leaves the cpu at.
For boards that have pmic control later in u-boot, we also add the option
to set the maximum frequency of 1.6GHz, if they so desire.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
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In the beginning, we did SPL -> TPL -> U-Boot, but after clarification
of the real ordering swapped SPL and TPL.
It seems some renames were forgotten and may confuse future readers, so
also swap these to reflect the actual ordering.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
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There was still a static ram value set in the rk3188-board from the
time where we didn't have actual sdram init code.
Now the sdram init leaves the ram information in SYS_REG2 and we can
decode it similarly to the rk3288.
Right now we have two duplicates of that code, which is still ok and
doesn't really count as common code yet, but if we get a third copy
at some point from a newer soc, we should think about moving that to
a more general position.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
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Right now we're setting the wrong value of 0 as base in the ram_info struct,
which is obviously wrong for the rk3188. So instead set the correct value
we already have in CONFIG_SYS_SDRAM_BASE.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
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Commit c67c8c604b6c ("board_init.c: Always use memset()") dropped the naive
memset alternative from board_init_f_init_reserve.
So activate CONFIG_TPL_LIBGENERIC for that common memset implementation.
We cannot use the ARCH-specific memset, as that would incur 200bytes of
additional TPL size, space we do not have.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Rockchip spl driver needs using spl_early_init().
Fixes: b3d2861e (spl: Remove overwrite of relocated malloc limit)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
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The SPL binary needs to be prefixed with the boot magic ('RK33' for
the RK3399) on the Rockchip platform and starts execution of the
instruction word following immediately after this boot magic.
This poses a challenge for AArch64 (ARMv8) binaries, as the .text
section would need to start on the odd address, violating natural
alignment (and potentially triggering a fault for any code that
tries to access 64bit values embedded in the .text section).
A quick and easy fix is to have the .text section include the 'RK33'
magic and pad it with a boot0 hook to insert 4 bytes of padding at the
start of the section (with the intention of having mkimage overwrite
this padding with the appropriate boot magic). This avoids having to
modify the linker scripts or more complex logic in mkimage.
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
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This includes Marvell mvpp2 patches with the ethernet support for the
ARMv8 Armada 7k/8k platforms. The ethernet patches are all acked by Joe
and he is okay with me pushing them via the Marvell tree.
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Change the buck8's min-microvolt to 750000.
Whent thor protocol is used, board_usb_init() should be tried to set to
750000. But it was returned -EINVAL, because '750000' too lower than
2850000. (thor command doesn't work fine because of this problem.)
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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Trats has the i2c gpio for fuel-gaugge.
This patch s for preparing to use the fuel-gauge.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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Introduce CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK to disable the external clock
loopback and use the internal one on SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0
register's SDMMC_SPARE1 bits being set to 0xfffd according to the TRM.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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This patch adds board support for the Toradex Apalis TK1 a computer on
module which can be used on different carrier boards.
The module consists of a Tegra TK1 SoC, a PMIC solution, 2 GB of DDR3L
RAM, a bunch of level shifters, an eMMC, a TMP451 temperature sensor
chip, an I210 gigabit Ethernet controller and a SGTL5000 audio codec.
Furthermore, there is a Kinetis MK20DN512 companion micro controller for
analogue, CAN and resistive touch functionality.
For the sake of ease of use we do not distinguish between different
carrier boards for now as the base module features are deemed
sufficient enough for regular booting.
The following functionality is working so far:
- eMMC boot, environment storage and Toradex factory config block
- Gigabit Ethernet
- MMC/SD cards (both MMC1 as well as SD1 slot)
- USB client/host (dual role OTG port as client e.g. for DFU/UMS or host,
other two ports as host)
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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The default configuration for the COMPHY-0 port should be 1G, as its
used as 1G SGMII connection. This change is necessary to get the
MAC2 port (SGMII) working on this DB.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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This commit adds the description of the PPv2.2 hardware block for the
Marvell Armada 7K and Armada 8K processors, and their corresponding Armada
7040 and 8040 Development boards.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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