summaryrefslogtreecommitdiff
path: root/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
AgeCommit message (Expand)Author
2011-09-30powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_enYork Sun
2011-09-30powerpc/mpc8xxx: Extend CWL tableYork Sun
2011-07-11powerpc/mpc8xxx: Allow override DDR read-to-write turnaround timeYork Sun
2011-04-04powerpc/8xxx: Fix typo for address hashing messageKumar Gala
2011-04-04powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq()Kumar Gala
2011-03-24powerpc/mpc8xxx: disable rcw_en bit for non-DDR3York Sun
2011-03-05powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registersYork Sun
2011-02-11powerpc/8xxx: Add additional cycle to write-to-read turnaound for DDR3York Sun
2011-01-25powerpc/8xxx: Fix compile warning when build for a DDR1 or DDR2 boardKumar Gala
2011-01-20mpc85xx: Enable unique mode registers and dynamic ODT for DDR3York Sun
2011-01-208xxx/ddr: add support to only compute the ddr sdram sizeHaiying Wang
2010-10-20Disable unused chip-select for DDR controller interleavingYork Sun
2010-08-31Fix parameters to support RDIMM for P2020DSYork Sun
2010-07-26powerpc/8xxx: Improvement to DDR parametersyork
2010-07-26powerpc/8xxx: Enable DDR3 RDIMM supportyork
2010-07-26powerpc/8xxx: Enabled address hashing for 85xxyork
2010-07-26powerpc/8xxx: Enable quad-rank DIMMs.york
2010-07-26powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4york
2010-04-27fsl-ddr: Add extra cycle to turnaround timesDave Liu
2010-04-21Move arch/ppc to arch/powerpcStefan Roese