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path: root/arch/x86/cpu/ivybridge/cpu.c
AgeCommit message (Expand)Author
2015-04-18x86: chromebook_link: dts: Add PCH and LPC devicesSimon Glass
2015-04-18dm: x86: pci: Convert chromebook_link to use driver model for pciSimon Glass
2015-04-17x86: Split up arch_cpu_init()Simon Glass
2015-04-17x86: Add a x86_ prefix to the x86-specific PCI functionsSimon Glass
2015-01-13x86: ivybridge: Update microcode early in bootSimon Glass
2015-01-13x86: ivybridge: Drop support for ROM cachingSimon Glass
2014-12-14x86: Add post failure codes for bist and carBin Meng
2014-11-21x86: ivybridge: Add LAPIC supportSimon Glass
2014-11-21x86: ivybridge: Add early init for PCH devicesSimon Glass
2014-11-21x86: ivybridge: Perform Intel microcode update on bootSimon Glass
2014-11-21x86: ivybridge: Check BIST value on bootSimon Glass
2014-11-21x86: ivybridge: Perform initial CPU setupSimon Glass
2014-11-21x86: ivybridge: Add early LPC init so that serial worksSimon Glass
2014-11-21x86: ivybridge: Enable PCI in early initSimon Glass
2014-11-21x86: chromebook_link: Implement CAR support (cache as RAM)Simon Glass
2014-11-21x86: Add chromebook_link boardSimon Glass
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